CN102738094A - Semiconductor packaging structure for stacking and manufacturing method thereof - Google Patents
Semiconductor packaging structure for stacking and manufacturing method thereof Download PDFInfo
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- CN102738094A CN102738094A CN2012101679218A CN201210167921A CN102738094A CN 102738094 A CN102738094 A CN 102738094A CN 2012101679218 A CN2012101679218 A CN 2012101679218A CN 201210167921 A CN201210167921 A CN 201210167921A CN 102738094 A CN102738094 A CN 102738094A
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Abstract
The invention discloses a semiconductor packaging structure for stacking and a manufacturing method thereof. The semiconductor packaging structure comprises a bottom substrate, a chip, an annular switchover substrate and packaging colloid. The bottom substrate is provided with a plurality of welding pads and a chip bearing area; the chip is fixedly arranged on the chip bearing area of the bottom substrate; a plurality of switchover assemblies and an opening are arranged on the annular switchover substrate; the switchover assemblies surround the opening and are electrically connected with the welding pads of the bottom substrate; the packaging colloid is filled in a gap between the bottom substrate and the annular switchover substrate, and is filled in the opening of the annular switchover substrate; and the packaging colloid in the opening is exposed to one top surface of the chip. With the adoption of the annular switchover substrate, the upper side and the lower side of a packaged body are slightly different in coefficient of thermal expansion, so that the warping rate is relatively lowered.
Description
Technical field
The invention relates to a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof, particularly relevant for a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof of utilizing annular interposer substrate to reduce the warpage defective.
Background technology
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the package design that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages product to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), stacked package body in stacked package body (POP) and the packaging body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can be subdivided into stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side again according to the arrangements of chips mode.Moreover; Said stacked package body (POP); Its structure is meant that completion one earlier has first packaging body of substrate; Then pile up another second complete packaging body in the upper surface of first packaging body again, second packaging body sees through suitable adapter assembly (like the tin ball) and is electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is to utilize another packing colloid that embedding such as the element of second packaging body, adapter assembly and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.
In the structure of existing stacked package body (POP); The substrate of first packaging body (following packaging body) of its bottom is generally tellite; And packing colloid generally is the epoxy resin base material that is doped with solid filling, and is to utilize transfer casting (transfer molding) technology to make.In recent years, in order to satisfy the lightening requirement of electronic product, the thickness of the following packaging body of existing stacked package body (POP) encapsulating structure is gradually by slimming to 350 micron below (μ m).Yet; Under the situation that the thickness of packaging body reduces gradually down; The overall construction intensity of following packaging body also can be weakened gradually; And (coefficient of thermal expansion CTE) there are differences and has the thermal stress effect to pull, thereby produces the phenomenon of warpage (warpage) more easily because the thermal coefficient of expansion between tellite and the packing colloid.Above-mentioned warping phenomenon normally forms warpage towards tellite at periphery by packing colloid.Simultaneously; Because down the integral thickness attenuation of packaging body also can make the thermal diffusivity variation of chip; Therefore when the heat energy of chip can't be timely and effectively when derive the outside; It is more obvious that above-mentioned warping phenomenon can become, and when serious even can cause packing colloid or tellite to produce slight crack (crack), and then significantly influences the production reliability and the useful life of the following packaging body of stacked package body (POP).
So, be necessary to provide a kind of semiconductor packaging structure that is used to pile up, to solve the existing in prior technology problem.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof, to solve existing technological existing warpage of stacked package body (POP) and heat dissipation problem.
Main purpose of the present invention is to provide a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof; It is to set up an annular interposer substrate at the following packaging body of stacked package body (POP); And between substrate and annular interposer substrate, fill packing colloid; The upper and lower sides of packaging body has less thermal expansion coefficient difference so that when reducing integral thickness, keep down as far as possible, produces the probability of warpage with relative minimizing, and then improves the production reliability and the useful life of packaging body down.
Secondary objective of the present invention is to provide a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof; Wherein the opening part of annular interposer substrate can be set up a fin; The end face of the hot contact chip of fin; And said fin also can have several ribs, extends to several corner positions by the opening part of annular interposer substrate, and the heat energy that therefore can rapidly chip be produced upwards and is outwards derived; And then help improving radiating efficiency that descends packaging body and the structural strength that increases annular interposer substrate, produce the probability of warpage with relative minimizing Yin Gaowen.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of semiconductor packaging structure that is used to pile up, and it comprises: a substrate, a chip, an annular interposer substrate and a packing colloid.Said substrate has a upper surface and a lower surface, and said upper surface has several weld pads and a chip bearing district.Said chip is fixedly arranged on the chip bearing district of said substrate.Said annular interposer substrate has several adapter assemblies, several connection pads and an opening; Said adapter assembly is located at a lower surface of said annular interposer substrate; Said connection pad is located at a upper surface of said annular interposer substrate; Said opening runs through said annular interposer substrate, said adapter assembly be centered around said opening around and electrically connect the weld pad of said substrate.Said packing colloid is filled in the gap that forms between said substrate and the annular interposer substrate; And be filled in the opening of said annular interposer substrate; And coat said chip and adapter assembly, the packing colloid in the wherein said opening exposes an end face of said chip.
Moreover one embodiment of the invention provides a kind of manufacturing approach of the semiconductor packaging structure that is used to pile up.At first, a substrate is provided, said substrate has a upper surface and a lower surface, and said upper surface has several weld pads and a chip bearing district.Then, a chip is fixedly arranged on the chip bearing district of said substrate.Then; One annular interposer substrate is provided; And several adapter assemblies of a lower surface through said annular interposer substrate electrically connect the weld pad of said substrate; Wherein said annular interposer substrate offers an opening, said adapter assembly be centered around said opening around, and a upper surface of said annular interposer substrate is provided with several connection pads.And; One packing colloid is inserted in the opening that reaches said annular interposer substrate in the gap that forms between said substrate and the annular interposer substrate; Said packing colloid coats said chip and adapter assembly, and the packing colloid in the said opening exposes an end face of said chip.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 is the cutaway view of the upper and lower packaging body of one embodiment of the invention stacked package body.
Fig. 2 is the cutaway view of the upper and lower packaging body of another embodiment of the present invention stacked package body.
Fig. 3 is the cutaway view of the upper and lower packaging body of further embodiment of this invention stacked package body.
Fig. 3 A is the top view of the following packaging body of Fig. 3 of the present invention.
Fig. 4 is the cutaway view of the upper and lower packaging body of yet another embodiment of the invention stacked package body.
Fig. 5 A, 5B and 5C are the schematic flow sheets of the manufacturing approach of Fig. 1 of the present invention semiconductor packaging structure (following packaging body) of being used to pile up.
Fig. 6 A and 6B are the schematic flow sheets of the manufacturing approach of Fig. 3 of the present invention semiconductor packaging structure (following packaging body) of being used to pile up.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to illustration the present invention in order to the specific embodiment of implementing.Moreover, the direction term that the present invention mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward " or " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to restriction the present invention.
Please with reference to shown in Figure 1; The semiconductor packaging structure that is used to pile up of first embodiment of the invention is mainly used in the packaging body once 100 as stacked type packaging body (POP); And in order to combine packaging body 200 on; Hereinafter, the said semiconductor packaging structure that is used to pile up promptly directly is called packaging body 100 down.In the present embodiment, said down packaging body 100 comprises: a substrate 10, a chip 11, one annular interposer substrate 12 and a packing colloid 13.The present invention will specify detail structure, assembled relation and the operation principles thereof of above-mentioned each element of present embodiment one by one in hereinafter.
Please with reference to shown in Figure 1; The substrate 10 of one embodiment of the invention can be selected from the tellite of the no core layer (coreless) of thickness between 50 to 200 μ m (micron) or be selected from pliability film substrate (flexible tape substrate); For example being selected from the additional layers that thickness is the no core layer of 150 or 180 μ m (build-up) tellite (comprising 4 layers of circuit layer) or thickness is the pliability film substrate of 64 μ m, but is not limited to this.Said substrate 10 is not had a core layer and will be helped reducing relatively its substrate thickness.Said substrate 10 has a upper surface and a lower surface, and the surface circuit of said upper surface exposes has several weld pads 101 and a chip bearing district 102.Said weld pad 101 is matrix (array) shape usually and is arranged on the said upper surface.Said chip bearing district 102 is meant a middle section of said upper surface, in said chip bearing district 102, also is distributed with several weld pads 101 usually.The surface circuit of said lower surface is also exposed to have several weld pads (not indicating), and by the weld pad solder bond of these lower surfaces several metal ball 103 is arranged, with the electric terminal of using as said substrate 10 I/O.
Please with reference to shown in Figure 1, the chip 11 of one embodiment of the invention can be various semiconductor chips, for example high frequency chip, CPU (CPU) chip or memory body chip (like DRAM or FLASH) etc., but do not limit.Said chip 11 can be the form of flip-chip (flip chip) or the form of routing chip (wire bonding chip).With the flip-chip is example, the active surface of said chip 11 down, and through several projection 111 solder bond and be fixedly arranged on the weld pad 101 in chip bearing district 102 of said substrate 10.Can be filled with a underfill (underfill) 112 between the upper surface of said chip 11 and said substrate 10, but also can omit.The thickness of said chip 11 can be between 0.1 to 0.04mm, for example is 0.1,0.08,0.06,0.05 or 0.04 etc.Said projection 111 can be selected from tin projection (bumps), golden projection or copper post projection (Cu pillar bumps) etc., and the height of said projection 111 is about 30 to 50 μ m, for example is 40 μ m.
Please with reference to shown in Figure 1; The annular interposer substrate 12 of one embodiment of the invention can be selected from thickness between 100 to 150 μ m and the tellite of tool core layer; For example be selected from the tellite that thickness is the no core layer of 140 μ m (comprising 2 layers of circuit layer), but be not limited to this.Said annular interposer substrate 12 has core layer will help under less substrate thickness, guaranteeing that it has enough structural strengths.The surface circuit of a lower surface of said annular interposer substrate 12 exposes has several weld pads (indicating); And several adapter assemblies 121 are arranged by the weld pad solder bond of these lower surfaces; Said adapter assembly 121 for example is tin projection, golden projection or copper post projection etc.; The height of said adapter assembly 121 is about 15 to 25 μ m, for example is 20 μ m.
Moreover; Said annular interposer substrate 12 offers an opening 122; Said opening 122 runs through said annular interposer substrate 12; And corresponding to said chip bearing district 102 and chip 11, and the length and width size of said opening 122 (for example 11 * 11mm) obviously greater than the length and width sizes of said chip bearing district 102 or said chip 11 (for example 10 * 10mm).Said adapter assembly 121 be centered around said opening 122 around and electrically connect the weld pad 101 of said substrate 10.The surface circuit of one upper surface of said annular interposer substrate 12 is in addition exposed to have several connection pads 123, and the opening diameter of said connection pad 123 is about 0.2mm, and its spacing is between 0.3 to 0.085mm, for example is 0.3,0.2,0.15,0.1 or 0.085mm etc.
Please with reference to shown in Figure 1; The packing colloid 13 of one embodiment of the invention is filled in the gap 14 that forms between said substrate 10 and the annular interposer substrate 12; And be filled in the opening 122 of said annular interposer substrate 12, and coat said chip 11 and adapter assembly 121.The height in said gap 14 is about 15 to 25 μ m, for example is 20 μ m.Be positioned at said opening 122 packing colloid 13 a upper surface and expose the end face (back side) of said chip 11.Said packing colloid 13 generally is the epoxy resin base material that is doped with solid filling, and said solid filling can be silica dioxide granule or alumina particle etc.The height of a upper surface that is positioned at the packing colloid 13 of said opening 122 can be lower than or be substantially equal to the height of the upper surface of said annular interposer substrate 12 slightly.
Please with reference to shown in Figure 1; The last packaging body 200 of one embodiment of the invention can be various forms of packaging bodies; The present invention does not limit; For example said go up packaging body 200 be selected from one have a stacked chips packaging body, the lower surface of its substrate is provided with several metal ball 21, can supply solder bond on the connection pad 123 of the upper surface of said annular interposer substrate 12; So that indirect forms electrical connection with said substrate 10 and chip 11, so said packaging body down 100 reaches goes up the framework that packaging body 200 can constitute stacked type packaging body (POP) jointly.
According to present embodiment; Because the following packaging body 100 of stacked package body (POP) is set up said annular interposer substrate 12; And between said substrate 10 and annular interposer substrate 12, fill said packing colloid 13; Suitably select the substrate kind of said substrate 10 and annular interposer substrate 12 simultaneously; Therefore can make the both sides up and down of said packing colloid 13 have similar substrate properties, so that when reducing said packaging body 100 integral thickness down, keep the said both sides up and down of packaging body 100 down to have less thermal expansion coefficient difference as far as possible; Produce the probability of warpage with the said packaging body down 100 of relative minimizing, and then improve the said production reliability and the useful life of packaging body 100 down.
Please with reference to shown in Figure 2; The semiconductor packaging structure that is used to pile up of another embodiment of the present invention is similar in appearance to Fig. 1 embodiment of the present invention; And roughly continue to use similar elements title and figure number; But the difference characteristic of present embodiment is: the following packaging body 100 of present embodiment is further set up a fin 15, and said fin 15 is embedded in the opening 122 of said annular interposer substrate 12.The upper surface that is positioned at the packing colloid 13 of said opening 122 is lower than the upper surface of said annular interposer substrate 12 slightly; So that be embedded said fin 15, the thickness of said fin 15 is substantially equal to the difference in height that forms between the upper surface of upper surface and said annular interposer substrate 12 of said packing colloid 13.The lower surface of said fin 15 directly amplexiforms on the packing colloid 13 at said opening 122 places, and the end face (back side) of the said chip 11 of the also hot contact of the lower surface of said fin 15.
In the present embodiment, said fin 15 also can select corresponding said opening 122 that at least one filler hole 151 is set.When transferring casting (transfer molding) technology; Said filler hole 151 can make things convenient for a sealing syringe to be inserted into the space in the said opening 122, said packing colloid 13 is filled out in the space and the gap 14 between said substrate 10 and the annular interposer substrate 12 in the said opening 122.Moreover, having a heat-conducting layer 16 between the end face of a lower surface of said fin 15 and said chip 11, said heat-conducting layer 16 can be selected from heat conduction elargol coating, indium layer or indium tin layer.Said heat-conducting layer 16 is in order to guarantee the hot annexation of said fin 15 and chip 11.
According to present embodiment; Said packaging body 100 same said annular interposer substrate 12 capable of using down make the both sides up and down of said packing colloid 13 have similar substrate properties; So that when reducing by said time packaging body 100 integral thickness; Keep the said both sides up and down of packaging body 100 down to have less thermal expansion coefficient difference as far as possible, produce the probability of warpage with the said packaging body 100 down of relative minimizing, and then improve the said production reliability and the useful life of packaging body 100 down.Further; In the present embodiment; Opening 122 places of said annular interposer substrate 12 more set up said fin 15, the end face of the said chip 11 of said fin 15 hot contacts, and the heat energy that therefore can rapidly said chip 11 be produced is upwards derived; And then help improving the said radiating efficiency of packaging body 100 down, and reduce said packaging body 100 down produces warpage because of high temperature probability relatively.
Please with reference to shown in Fig. 3 and the 3A; The semiconductor packaging structure that is used to pile up of further embodiment of this invention is similar in appearance to Fig. 2 embodiment of the present invention; And roughly continue to use similar elements title and figure number; But the difference characteristic of present embodiment is: the fin 15 of the following packaging body 100 of present embodiment is to be positioned on the upper lip of opening 122 of said annular interposer substrate 12; Said fin 15 has more several ribs 152 (shown in Fig. 3 A) simultaneously, and said ribs 152 is extended to several corner positions or its adjacent domain of a upper surface of said annular interposer substrate 12 by said opening 122 places.The upper surface that is positioned at the packing colloid 13 of said opening 122 is substantially equal to the upper surface of said annular interposer substrate 12; Therefore the lower surface of said fin 15 still can amplexiform on the packing colloid 13 at said opening 122 places, and the end face (back side) that the lower surface of said fin 15 also can the said chip 11 of hot contact.The quantity of the corner of said ribs 152 and said annular interposer substrate 12 for example is all 4, but is not limited to this.The thickness of said fin 15 is basically less than the thickness of said annular interposer substrate 12, for example be said annular interposer substrate 12 thickness 1/2,1/3,1/4 or 1/5 etc.
According to present embodiment; Said packaging body 100 same said annular interposer substrate 12 capable of using down make the both sides up and down of said packing colloid 13 have similar substrate properties; So that when reducing by said time packaging body 100 integral thickness; Keep the said both sides up and down of packaging body 100 down to have less thermal expansion coefficient difference as far as possible, produce the probability of warpage with the said packaging body 100 down of relative minimizing, and then improve the said production reliability and the useful life of packaging body 100 down.Further; In the present embodiment, opening 122 places of said annular interposer substrate 12 more set up said fin 15, and the end face of the said chip 11 of said fin 15 hot contacts; The heat energy that therefore can rapidly said chip 11 be produced upwards and is outwards derived; And then help improving the said radiating efficiency of packaging body 100 down, and increase the structural strength of said annular interposer substrate 12, produce the probability of warpage because of high temperature with the said packaging body 100 down of relative minimizing.
Please with reference to shown in Figure 4; The semiconductor packaging structure that is used to pile up of yet another embodiment of the invention is similar in appearance to Fig. 1 embodiment of the present invention; And roughly continue to use similar elements title and figure number; But the difference characteristic of present embodiment is: the annular interposer substrate 12 of the following packaging body 100 (semiconductor packaging structure) of present embodiment and said going up between the packaging body 200 are folded with an organic spacer substrate (organic interposer) 17 in addition; Said organic spacer substrate 17 can be selected from the tellite or the pliability film substrate of the no core layer of thickness between 50 to 100 μ m; For example being selected from the additional layers that thickness is the no core layer of 90 μ m (build-up) tellite (comprising 2 layers of circuit layer) or thickness is the pliability film substrate of 75 μ m, but is not limited to this.
According to present embodiment; Said packaging body 100 same said annular interposer substrate 12 capable of using down make the both sides up and down of said packing colloid 13 have similar substrate properties; So that when reducing by said time packaging body 100 integral thickness; Keep the said both sides up and down of packaging body 100 down to have less thermal expansion coefficient difference as far as possible, produce the probability of warpage with the said packaging body 100 down of relative minimizing, and then improve the said production reliability and the useful life of packaging body 100 down.Further; In the present embodiment; When the thickness of said annular interposer substrate 12 has been designed to make the both sides up and down of said packing colloid 13 to have similar substrate properties (containing thermal coefficient of expansion); But when said annular interposer substrate 12 can't provide enough weld pads heavily to distribute (redistribution) demand or radiating requirements under limited thickness, present embodiment can satisfy heavy distributed needs of weld pad or radiating requirements through the said organic spacer substrate 17 of extra use.
Please with reference to shown in Fig. 5 A, 5B and the 5C, it discloses the schematic flow sheet of the manufacturing approach of the semiconductor packaging structure (following packaging body 100) that Fig. 1 embodiment of the present invention is used to pile up.
At first, shown in Fig. 5 A, a substrate 10 is provided earlier, said substrate 10 has a upper surface and a lower surface, and said upper surface has several weld pads 101 and a chip bearing district 102; Then, a chip 11 is fixedly arranged on the chip bearing district 102 of said substrate 10.
Subsequently; Shown in Fig. 5 A and 5B; One annular interposer substrate 12 is provided again; And several adapter assemblies 121 of a lower surface through said annular interposer substrate 12 electrically connect the weld pad 101 of said substrate 10, and wherein said annular interposer substrate 12 offers an opening 122, said adapter assembly 121 be centered around said opening 122 around
At last; Shown in Fig. 5 B and 5C; Before inserting said packing colloid 13, on the opening 122 of said annular interposer substrate 12, stick earlier the provisional glued membrane 30 of one deck, perhaps also can said provisional glued membrane 30 be placed on the inner top surface of a die cavity of a mold (not illustrating) in advance; When all components with Fig. 5 A was put between a said mold and the bed die (not illustrating) and carries out matched moulds, said provisional glued membrane 30 just can change on the opening 122 that is attached to said annular interposer substrate 12; Then; Insert between said substrate 10 and the annular interposer substrate 12 packing colloid 13 in the gap 14 that forms and in the opening 122 of said annular interposer substrate 12; Said packing colloid 13 coats said chip 11 and adapter assembly 121, and the packing colloid 13 in the said opening 122 exposes an end face of said chip 11.After the step of said packing colloid 13 is inserted in completion, promptly remove said provisional glued membrane 30.Through above-mentioned steps, the present invention can accomplish the manufacturing of the semiconductor packaging structure (following packaging body 100) that is used to pile up.
Moreover; As shown in Figure 1; The present invention also can make said packaging body down 100 further combine packaging body 200 on; Metal ball 21 solder bond of the wherein said upward lower surface of packaging body 200 are on the connection pad 123 of the upper surface of said annular interposer substrate 12, and so said packaging body down 100 reaches goes up the framework that packaging body 200 can constitute stacked type packaging body (POP) jointly.
Please with reference to shown in Fig. 6 A and the 6B, it discloses the schematic flow sheet of the manufacturing approach of the semiconductor packaging structure (following packaging body 100) that Fig. 3 embodiment of the present invention is used to pile up.Each step of the manufacturing approach of present embodiment is roughly similar in appearance to each step of manufacturing approach of Fig. 5 A to 5C embodiment of the present invention; And roughly continue to use similar elements title and figure number, but the difference characteristic of present embodiment is: the following packaging body 100 (semiconductor packaging structure) of Fig. 3 is directly to replace said provisional glued membrane 30 with a fin 15.Therefore; Before the step of inserting said packing colloid 13; The present invention is provided with a fin 15 at opening 122 places of said annular interposer substrate 12 earlier; Said fin 15 corresponding said openings 122 have several filler holes 151, and said fin 15 can select to be positioned at said opening 122 (as shown in Figure 2), or are positioned on the upper lip of said opening 122 (as shown in Figure 3); And, in the step of inserting said packing colloid 13, insert said packing colloid 13 through the filler hole 151 of said fin 15.Just; When transferring casting (transfer molding) technology; Said filler hole 151 can make things convenient for a sealing syringe to be inserted into the space in the said opening 122, said packing colloid 13 is filled out in the space and the gap 14 between said substrate 10 and the annular interposer substrate 12 in the said opening 122.
Moreover, in the present embodiment, having a heat-conducting layer 16 between the end face of a lower surface of said fin 15 and said chip 11, said heat-conducting layer 16 is in order to guarantee the hot annexation of said fin 15 and chip 11.After the step of inserting said packing colloid 13, said fin 15 directly is retained on the annular interposer substrate 12 of said packaging body 100 down, does not remove.In addition, can omit former underfill 112 between the upper surface of said chip 11 and said substrate 10, and directly replace to fill said packing colloid 13.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (20)
1. semiconductor packaging structure that is used to pile up, it is characterized in that: the said semiconductor packaging structure that is used to pile up comprises:
One substrate has a upper surface and a lower surface, and said upper surface has several weld pads and a chip bearing district;
One chip is fixedly arranged on the chip bearing district of said substrate;
One annular interposer substrate; Have several adapter assemblies, several connection pads and an opening; Said adapter assembly is located at a lower surface of said annular interposer substrate; Said connection pad is located at a upper surface of said annular interposer substrate, and said opening runs through said annular interposer substrate, said adapter assembly be centered around said opening around and electrically connect the weld pad of said substrate; And
One packing colloid; Be filled in the gap that forms between said substrate and the annular interposer substrate; And be filled in the opening of said annular interposer substrate, and coating said chip and adapter assembly, the packing colloid in the wherein said opening exposes an end face of said chip.
2. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said substrate is selected from the tellite or the pliability film substrate of no core layer.
3. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said annular interposer substrate is selected from the tellite of tool core layer.
4. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: be provided with a fin on the packing colloid of said opening part in addition, the end face of the said chip of the hot contact of said fin.
5. the semiconductor packaging structure that is used to pile up as claimed in claim 4 is characterized in that: said fin is positioned at said opening, or is positioned on the upper lip of said opening.
6. the semiconductor packaging structure that is used to pile up as claimed in claim 4 is characterized in that: have a heat-conducting layer between a lower surface of said fin and the end face of said chip.
7. the semiconductor packaging structure that is used to pile up as claimed in claim 6 is characterized in that: said heat-conducting layer is selected from heat conduction elargol coating, indium layer or indium tin layer.
8. the semiconductor packaging structure that is used to pile up as claimed in claim 4 is characterized in that: said fin has several ribs, and said ribs is extended to several corner positions of a upper surface of said annular interposer substrate by said opening part.
9. the semiconductor packaging structure that is used to pile up as claimed in claim 4 is characterized in that: the corresponding said opening of said fin has at least one filler hole.
10. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said semiconductor packaging structure is as the packaging body once of stacked type packaging body, and combines packaging body on through said connection pad.
11. the semiconductor packaging structure that is used to pile up as claimed in claim 10 is characterized in that: the annular interposer substrate of said semiconductor packaging structure and said going up between the packaging body are folded with an organic spacer substrate in addition.
12. the semiconductor packaging structure that is used to pile up as claimed in claim 11 is characterized in that: said organic spacer substrate is selected from the tellite or the pliability film substrate of no core layer.
13. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: be filled with a said packing colloid or a underfill between the upper surface of said chip and said substrate.
14. the manufacturing approach of a semiconductor packaging structure that is used to pile up is characterized in that: said manufacturing approach comprises step:
One substrate is provided, and said substrate has a upper surface and a lower surface, and said upper surface has several weld pads and a chip bearing district;
One chip is fixedly arranged on the chip bearing district of said substrate;
One annular interposer substrate is provided; And several adapter assemblies of a lower surface through said annular interposer substrate electrically connect the weld pad of said substrate; Wherein said annular interposer substrate offers an opening; Said adapter assembly be centered around said opening around, and a upper surface of said annular interposer substrate is provided with several connection pads; And
One packing colloid is inserted in the opening that reaches said annular interposer substrate in the gap that forms between said substrate and the annular interposer substrate; Said packing colloid coats said chip and adapter assembly, and the packing colloid in the said opening exposes an end face of said chip.
15. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14 is characterized in that: before inserting the step of said packing colloid, above said annular interposer substrate, use the provisional glued membrane of one deck earlier; And, after inserting the step of said packing colloid, remove said provisional glued membrane again.
16. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14; It is characterized in that: before inserting the step of said packing colloid; Opening part in said annular interposer substrate is provided with a fin earlier, and the corresponding said opening of said fin has several filler holes; And, in inserting the step of said packing colloid, insert said packing colloid through the filler hole of said fin.
17. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 16; It is characterized in that: said fin has several ribs, and said ribs is extended to several corner positions of a upper surface of said annular interposer substrate by said opening part.
18. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 16 is characterized in that: said fin is positioned at said opening, or is positioned on the upper lip of said opening.
19. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14; It is characterized in that: after inserting the step of said packing colloid; With the once packaging body of said semiconductor packaging structure as the stacked type packaging body, and through packaging body in the said connection pad combination one.
20. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 19 is characterized in that: the annular interposer substrate of said semiconductor packaging structure and said going up between the packaging body are folded with an organic spacer substrate in addition.
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