Summary of the invention
The object of the invention is exactly to avoid checking the too low radiation problem that needs frequent inspection to cause of effective percentage because of breast X-ray for young woman, and the problem such as expensive of mammary gland magnetic resonance imaging, a kind of easy and early stage apparatus for evaluating of young woman's breast cancer of having no side effect is proposed.
The present invention is by the following technical solutions:
The early stage risk assessment device of breast carcinoma, comprises frequency sweep sine wave generating circuit, voltage/current conversion circuit, impedance matching circuit, test electrode array, amplitude processing unit, slave computer, host computer, the first power supply and second source.
The outfan of frequency sweep sine wave generating circuit is connected with voltage/current conversion circuit input, the outfan of voltage/current conversion circuit is connected with impedance matching circuit input, impedance matching circuit outfan is connected with test electrode array, and test electrode array is placed on tested object mammary gland tissue; Amplitude processing unit input is connected to the outfan of voltage/current conversion circuit, and the outfan of amplitude processing unit is connected to the I/O mouth of slave computer; The first power supply connects frequency sweep sinewave circuit, voltage/current conversion circuit, test electrode array and slave computer; Second source connects amplitude processing unit; The control mouth of test electrode array is connected the I/O mouth of slave computer with the control mouth of frequency sweep sinewave circuit; Slave computer has been connected transfer of data by I/O mouth with host computer input.
Described frequency sweep sine wave generating circuit is by the first chip IC 1, the first crystal oscillator X1, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the first potentiometer Re1, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the four capacitor C 4, the five capacitor C 5, the 6th capacitor C 6, the seven capacitor C 7 and the 8th capacitor C 8 form.
In frequency sweep sine wave generating circuit, 5 feet of the first chip IC 1,10 feet, 19 feet and 24 feet are connected to ground; 6 feet of the first chip IC 1,11 feet, 18 feet and 23 feet are connected to power supply; 4 feet of the first chip, 3 feet, 2 feet, 1 foot, 28 feet, 27 feet, 26 feet, eight data pin of 25 foot connect 8 I/O mouths of slave computer successively; 7 feet of the first chip IC 1,8 feet and three, 22 foot are controlled 3 I/O mouths that pin is connected respectively slave computer; 9 feet of the first chip connect the 3rd pin of the first crystal oscillator X1; The 2nd pin of the first crystal oscillator X1 is connected to ground; The 4th pin of the first crystal oscillator X1 is connected to power supply; 12 feet of the first chip IC 1 connect one end of the first resistance R 1; The other end of the first resistance R 1 is connected to ground; 21 feet of the first chip IC 1 connect one end of the second resistance R 2, one end of one end of the second capacitor C 2, the 5th capacitor C 5 and one end of the first inductance L 1; Second capacitor C 2 other ends connect the other end of the first inductance L 1, one end of one end of the 3rd capacitor C 3, the second inductance L 2 and one end of the 6th capacitor C 6; The other end of the 3rd capacitor C 3 connects the other end of the second inductance L 2, one end of one end of the 4th capacitor C 4, the 3rd inductance L 3 and one end of the 7th capacitor C 7; The other end of the 4th capacitor C 4 connects 16 feet of the other end of the 3rd inductance L 3, one end of one end of the 8th capacitor C 8, the 3rd resistance R 3 and the first chip IC 1; 16 feet of the first chip IC 1 are the outfan SIA of frequency sweep sine wave generating circuit; The other end of the other end of the other end of the other end of the other end of the other end of the second resistance R 2, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8 and the 3rd resistance R 3 is connected to ground; 15 feet of the first chip IC 1 connect one end of the first capacitor C 1 and 2 ends of the first potentiometer Re1; The other end of the first capacitor C 1 is connected to ground; 1 end of the first potentiometer Re1 connects power supply, and 3 ends are connected to ground; Other pin of the first chip IC 1 is unsettled; The first described chip IC 1 model is AD9850.
Voltage/current conversion circuit is by the second chip IC 2, the first amplifier A1, the second amplifier A2, and the 4th resistance R 4, the five resistance R 5, the six resistance R 6, the seven resistance R 7 and the 9th capacitor C 9, the ten capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12 form.
In voltage/current conversion circuit, input SIA connects 1 foot of the second chip IC 2 and one end of the 9th capacitor C 9; The other end of the 9th capacitor C 9 connects 3 feet, the first in-phase input end of amplifier A1 of the second chip IC 2, one end of one end of the 11 capacitor C 11 and the 6th resistance R 6; 2 feet of the first chip IC 1 connect the outfan of the first amplifier A1, one end of one end of the tenth capacitor C 10, the 7th resistance R 7; The reverse input end of the first amplifier A1 connects one end of the other end of the tenth capacitor C 10, the other end of the 7th resistance R 7 and the 5th resistance R 5; The 5th other end of resistance R 5 is, the other end of the 11 capacitor C 11 is connected to ground; The other end of the 6th resistance R 6 connects inverting input and the outfan of the second amplifier A2 simultaneously; 5 feet of the second chip IC 2 and 4 foot short circuits are also connected one end of the 4th resistance R 4, the other end of the 4th resistance R 4 connects the second in-phase input end of amplifier A2 and one end of the 12 capacitor C 12, the other end of the 12 capacitor C 12 is the outfan Iout of voltage/current conversion circuit, and other foot of the second chip IC 2 is unsettled; The second described chip IC 2 models are AD830.
Impedance matching circuit is comprised of the 4th inductance L 4, the five inductance L 5, the six inductance L 6, the seven inductance L 7, the eight inductance L 8 and the 9th inductance L 9.
In impedance matching circuit, one end of the 4th inductance L 4 is impedance matching circuit input; The other end of the 4th inductance L 4 connects one end of the 5th inductance L 5; The other end of the 5th inductance L 5 connects one end of the 6th inductance L 6; The other end of the 6th inductance L 6 connects one end of the 7th inductance L 7; The other end of the 7th inductance L 7 connects one end of the 8th inductance L 8; The other end of the 8th inductance L 8 connects one end of the 9th inductance L 9; The other end of the 9th inductance L 9 is the outfan of impedance matching circuit.
Amplitude processing unit is comprised of the 3rd chip IC 3, the eight resistance R 8, the nine resistance R 9, the ten resistance R 10, the 13 capacitor C 13.
In amplitude processing unit, circuit input end PeakIn connects one end of the 8th resistance R 8; The other end of the 8th resistance R 8 connects 5 feet of the 3rd chip IC 3, one end of the 9th resistance R 9; The other end of the 9th resistance R 9 connects 9 feet and 3 feet of the 3rd chip IC 3; One end of the tenth resistance R 10 connects 6 feet of the 3rd chip IC 3; The other end of the tenth resistance R 10 is connected to ground; 4 feet of the 3rd chip IC 3 connect one end of the 13 capacitor C 13; The other end of the 13 capacitor C 13 is connected to ground; 8 foot ground connection of the 3rd chip IC 3; 1 foot of the 3rd chip IC 3 and 14 feet are connected respectively to two I/O mouths of slave computer; 3 feet of the 3rd chip IC 3 are the outfan of amplitude processing unit; The model of the 3rd described chip IC 3 is PKD01.
Test electrode array circuit comprises four-core sheet IC4, the 5th chip IC the 5, the 11 resistance R 11, the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R the 14, the 15 resistance R the 15, the 16 resistance R the 16, the 17 resistance R the 17, the 14 capacitor C the 14, the 15 capacitor C the 15, the 16 capacitor C the 16, the 17 capacitor C the 17, the 18 capacitor C the 18, the 19 capacitor C the 19, the 20 capacitor C 20, central electrode P0 and be evenly distributed on its outside six copper electrode P1, P2, P3, P4, P5, P6.
In test electrode array circuit, the outfan Lout of impedance matching circuit connects 6 feet of four-core sheet IC4, one end of 1 foot, 3 feet, 5 feet, 9 feet, 11 feet, 13 feet and the 11 resistance R 11 of the 5th chip IC 5; The other end ground connection of the 11 resistance R 11; 14 feet of four-core sheet IC4 connect the 12 one end of resistance R 12, one end of the 14 capacitor C 14, the first electrode P1; 15 feet of four-core sheet IC4 connect the 13 one end of resistance R 13, one end of the 15 capacitor C 15, the second electrode P2; 12 feet of four-core sheet IC4 connect the 14 one end of resistance R 14, one end of the 16 capacitor C 16, third electrode P3; 1 foot of four-core sheet IC4 connects the 15 one end of resistance R 15, one end of the 17 capacitor C 17, the 4th electrode P4; 5 feet of four-core sheet IC4 connect the 16 one end of resistance R 16, one end of the 18 capacitor C 18, the 5th electrode P5; 2 feet of four-core sheet IC4 connect the 17 one end of resistance R 17, one end of the 19 capacitor C 19, the 6th electrode P6; The other end of the 12 resistance R 12 connects 12 feet of the 5th chip IC 5; The other end of the 13 resistance R 13 connects 10 feet of the 5th chip IC 5; The other end of the 14 resistance R 14 connects 8 feet of the 5th chip IC 5; The other end of the 15 resistance R 15 connects 6 feet of the 5th chip IC 5; The other end of the 16 resistance R 16 connects 4 feet of the 5th chip IC 5; The other end of the 17 resistance R 17 connects 2 feet of the 5th chip IC 5; Three channel selecting control pin 11 feet, 10 feet, 9 feet of four-core sheet IC4 connect respectively 3 I/O mouths of slave computer; The 14 other end of capacitor C 14 is, the other end of the 15 capacitor C 15, the 16 other end of capacitor C 16, the other end of the 17 capacitor C 17, the 18 other end of capacitor C 18, the other end of the 19 capacitor C 19 are connected to ground; Described four-core sheet IC4 model is CD4051, and the model of the 5th chip IC 5 is CD4069.
Compared with prior art, the invention has the beneficial effects as follows:
This is a kind of portable checkout gear, and this detection method is harmless, and without particular job environmental requirement, it is convenient to check, and device is simple, with low cost, can easily predict the degree of risk of mammary gland tissue generation pathological changes.
The specific embodiment
Below in conjunction with accompanying drawing, the present invention is further illustrated.
Research shows, biological tissue is comprised of a large amount of cells, the extracellular fluid existing between cell and cell.Wherein dissolving the ion of a large amount of amorphs, thereby extracellular fluid has good electric conductivity.Verified, intracellular fluid also has good electric conductivity, has finally been proposed the concept of equivalent model by more early stage scientist's theories.Comprising individual cells equivalent-circuit model in biological tissue as shown in Figure 1.In figure, Re is resistanceper unit length of external fluid, and Ce is extracellular fluid shunt capacitance; Rm is the resistance of cell membrane, and Cm is cell membrane shunt capacitance; Ri is intracellular fluid resistance, and Ci is intracellular fluid shunt capacitance.In low frequency situation (<1MHz), the ohmic leakage Rm of cell membrane is very large, can be considered open circuit; And the shunt capacitance Ci of inside and outside liquid, Ce is very little, also can be considered open circuit.So just drawn the simple equivalent circuit model of the biological tissue shown in Fig. 2.Ri now just, Re, Cm represents the inside and outside liquid resistance of certain cell and cell membrane electric capacity, but represents the inside and outside liquid resistance of equivalence and the membrane capacitance of whole biological tissue, Here it is so-called three elements model.
The invention provides the early stage risk assessment device of breast carcinoma of a set of employing resonant frequency method.This principle of device is, both sides mammary gland tissue is applied to identical frequency sweep AC signal, by data acquisition unit, gathers series of voltage signal, formed one group of voltage curve.This group voltage signal curve is carried out to feature extraction and analysis, whether extremely assess mammary gland tissue.The method can not only be measured the impedance operator of mammary gland tissue, and to distinguish easily the risk that this mammary gland tissue suffers from breast cancer by the scan mode of resonant frequency point be lower than average level or higher than average level.
As shown in Figure 3, the early stage risk assessment device of breast carcinoma, comprises frequency sweep sine wave generating circuit 1, voltage/current conversion circuit 2, impedance matching circuit 3, test electrode array 4, amplitude processing unit 5, slave computer 6, host computer 7, the first power supply 8 and second source 9.
The outfan of frequency sweep sine wave generating circuit is connected with voltage/current conversion circuit input, the outfan of voltage/current conversion circuit is connected with impedance matching circuit input, impedance matching circuit outfan is connected with test electrode array, and test electrode array is placed on tested object mammary gland tissue; Amplitude processing unit input is connected to the outfan of voltage/current conversion circuit, and the outfan of amplitude processing unit is connected to the I/O mouth of slave computer; The first power supply connects frequency sweep sinewave circuit, voltage/current conversion circuit, test electrode array and slave computer; Second source connects amplitude processing unit; The control mouth of test electrode array is connected the I/O mouth of slave computer with the control mouth of frequency sweep sinewave circuit; Slave computer has been connected transfer of data by I/O mouth with host computer input.
As shown in Figure 4, described frequency sweep sine wave generating circuit is output as the voltage sine wave of different frequency.This circuit is by the first chip IC 1, the first crystal oscillator X1, the first resistance R 1, the second resistance R 2, the three resistance R 3, the first potentiometer Re1, the first capacitor C 1, the second capacitor C 2, the three capacitor C 3, the 4th capacitor C 4, the five capacitor C 5, the six capacitor C 6, the seven capacitor C 7 and the 8th capacitor C 8 form.
In frequency sweep sine wave generating circuit, 5 feet of the first chip IC 1,10 feet, 19 feet and 24 feet are connected to ground; 6 feet of the first chip IC 1,11 feet, 18 feet and 23 feet are connected to power supply; 4 feet of the first chip, 3 feet, 2 feet, 1 foot, 28 feet, 27 feet, 26 feet, eight data pin of 25 foot connect 8 I/O mouths of slave computer successively; 7 feet of the first chip IC 1,8 feet and three, 22 foot are controlled 3 I/O mouths that pin is connected respectively slave computer; 9 feet of the first chip connect the 3rd pin of the first crystal oscillator X1; The 2nd pin of the first crystal oscillator X1 is connected to ground; The 4th pin of the first crystal oscillator X1 is connected to power supply; 12 feet of the first chip IC 1 connect one end of the first resistance R 1; The other end of the first resistance R 1 is connected to ground; 21 feet of the first chip IC 1 connect one end of the second resistance R 2, one end of one end of the second capacitor C 2, the 5th capacitor C 5 and one end of the first inductance L 1; Second capacitor C 2 other ends connect the other end of the first inductance L 1, one end of one end of the 3rd capacitor C 3, the second inductance L 2 and one end of the 6th capacitor C 6; The other end of the 3rd capacitor C 3 connects the other end of the second inductance L 2, one end of one end of the 4th capacitor C 4, the 3rd inductance L 3 and one end of the 7th capacitor C 7; The other end of the 4th capacitor C 4 connects 16 feet of the other end of the 3rd inductance L 3, one end of one end of the 8th capacitor C 8, the 3rd resistance R 3 and the first chip IC 1; 16 feet of the first chip IC 1 are the outfan SIA of frequency sweep sine wave generating circuit; The other end of the other end of the other end of the other end of the other end of the other end of the second resistance R 2, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8 and the 3rd resistance R 3 is connected to ground; 15 feet of the first chip IC 1 connect one end of the first capacitor C 1 and 2 ends of the first potentiometer Re1; The other end of the first capacitor C 1 is connected to ground; 1 end of the first potentiometer Re1 connects power supply, and 3 ends are connected to ground; Other pin of the first chip IC 1 is unsettled; The high integration product DDS chip AD9850 that the first described chip IC 1 adopts advanced direct digital frequency synthesis technology to produce.
As shown in Figure 5, voltage/current conversion circuit input connects the output of frequency sweep sine wave generating circuit, and the voltage of frequency sweep sine wave generating circuit output is converted into constant current output.This circuit is by the second chip IC 2, the first amplifier A1, the second amplifier A2, and the 4th resistance R 4, the five resistance R 5, the six resistance R 6, the seven resistance R 7 and the 9th capacitor C 9, the ten capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12 form.
In voltage/current conversion circuit, input SIA connects 1 foot of the second chip IC 2 and one end of the 9th capacitor C 9; The other end of the 9th capacitor C 9 connects 3 feet, the first in-phase input end of amplifier A1 of the second chip IC 2, one end of one end of the 11 capacitor C 11 and the 6th resistance R 6; 2 feet of the first chip IC 1 connect the outfan of the first amplifier A1, one end of one end of the tenth capacitor C 10, the 7th resistance R 7; The reverse input end of the first amplifier A1 connects one end of the other end of the tenth capacitor C 10, the other end of the 7th resistance R 7 and the 5th resistance R 5; The 5th other end of resistance R 5 is, the other end of the 11 capacitor C 11 is connected to ground; The other end of the 6th resistance R 6 connects inverting input and the outfan of the second amplifier A2 simultaneously; 5 feet of the second chip IC 2 and 4 foot short circuits are also connected one end of the 4th resistance R 4, the other end of the 4th resistance R 4 connects the second in-phase input end of amplifier A2 and one end of the 12 capacitor C 12, the other end of the 12 capacitor C 12 is the outfan Iout of voltage/current conversion circuit, and other foot of the second chip IC 2 is unsettled; High-speed, video difference amplifier chip AD830 that the second described chip IC 2 adopts AD company to produce.
As shown in Figure 6, the input of impedance matching circuit connects the output of voltage/current conversion circuit, is used for mating with the capacitive reactances of mammary gland tissue equivalence, thereby can under characteristic frequency, resonance occurs, and voltage is obtained minima; This circuit is comprised of the 4th inductance L 4, the five inductance L 5, the six inductance L 6, the seven inductance L 7, the eight inductance L 8 and the 9th inductance L 9.
In impedance matching circuit, one end of the 4th inductance L 4 is impedance matching circuit input; The other end of the 4th inductance L 4 connects one end of the 5th inductance L 5; The other end of the 5th inductance L 5 connects one end of the 6th inductance L 6; The other end of the 6th inductance L 6 connects one end of the 7th inductance L 7; The other end of the 7th inductance L 7 connects one end of the 8th inductance L 8; The other end of the 8th inductance L 8 connects one end of the 9th inductance L 9; The other end of the 9th inductance L 9 is the outfan of impedance matching circuit.
As shown in Figure 7, the input of amplitude processing unit connects the input of impedance matching circuit, is used for detecting the output voltage that impedance matching circuit is connected with mammary gland tissue.Amplitude processing unit is comprised of the 3rd chip IC 3, the eight resistance R 8, the nine resistance R 9, the ten resistance R 10, the 13 capacitor C 13.
In amplitude processing unit, circuit input end PeakIn connects one end of the 8th resistance R 8; The other end of the 8th resistance R 8 connects 5 feet of the 3rd chip IC 3, one end of the 9th resistance R 9; The other end of the 9th resistance R 9 connects 9 feet and 3 feet of the 3rd chip IC 3; One end of the tenth resistance R 10 connects 6 feet of the 3rd chip IC 3; The other end of the tenth resistance R 10 is connected to ground; 4 feet of the 3rd chip IC 3 connect one end of the 13 capacitor C 13; The other end of the 13 capacitor C 13 is connected to ground; 8 foot ground connection of the 3rd chip IC 3; 1 foot of the 3rd chip IC 3 and 14 feet are connected respectively to two I/O mouths of slave computer; 3 feet of the 3rd chip IC 3 are the outfan of amplitude processing unit; The monolithic peak detector PKD01 that the 3rd described chip IC 3 adopts AD company to produce.
As shown in Figure 8, test electrode array is placed on the mammary gland tissue of tested object, and circuit is used for gating and is placed on the electrode channel on mammary gland tissue.Test electrode array circuit comprises four-core sheet IC4, the 5th chip IC the 5, the 11 resistance R 11, the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R the 14, the 15 resistance R the 15, the 16 resistance R the 16, the 17 resistance R the 17, the 14 capacitor C the 14, the 15 capacitor C the 15, the 16 capacitor C the 16, the 17 capacitor C the 17, the 18 capacitor C the 18, the 19 capacitor C the 19, the 20 capacitor C 20, central electrode P0 and be evenly distributed on its outside six copper electrode P1, P2, P3, P4, P5, P6.
In test electrode array circuit, the outfan Lout of impedance matching circuit connects 6 feet of four-core sheet IC4, one end of 1 foot, 3 feet, 5 feet, 9 feet, 11 feet, 13 feet and the 11 resistance R 11 of the 5th chip IC 5; The other end ground connection of the 11 resistance R 11; 14 feet of four-core sheet IC4 connect the 12 one end of resistance R 12, one end of the 14 capacitor C 14, the first electrode P1; 15 feet of four-core sheet IC4 connect the 13 one end of resistance R 13, one end of the 15 capacitor C 15, the second electrode P2; 12 feet of four-core sheet IC4 connect the 14 one end of resistance R 14, one end of the 16 capacitor C 16, third electrode P3; 1 foot of four-core sheet IC4 connects the 15 one end of resistance R 15, one end of the 17 capacitor C 17, the 4th electrode P4; 5 feet of four-core sheet IC4 connect the 16 one end of resistance R 16, one end of the 18 capacitor C 18, the 5th electrode P5; 2 feet of four-core sheet IC4 connect the 17 one end of resistance R 17, one end of the 19 capacitor C 19, the 6th electrode P6; The other end of the 12 resistance R 12 connects 12 feet of the 5th chip IC 5; The other end of the 13 resistance R 13 connects 10 feet of the 5th chip IC 5; The other end of the 14 resistance R 14 connects 8 feet of the 5th chip IC 5; The other end of the 15 resistance R 15 connects 6 feet of the 5th chip IC 5; The other end of the 16 resistance R 16 connects 4 feet of the 5th chip IC 5; The other end of the 17 resistance R 17 connects 2 feet of the 5th chip IC 5; Three channel selecting control pin 11 feet, 10 feet, 9 feet of four-core sheet IC4 connect respectively 3 I/O mouths of slave computer; The 14 other end of capacitor C 14 is, the other end of the 15 capacitor C 15, the 16 other end of capacitor C 16, the other end of the 17 capacitor C 17, the 18 other end of capacitor C 18, the other end of the 19 capacitor C 19 are connected to ground; Described four-core sheet IC4 model is selected 8 passage numeral control simulation electronic switch chip CD4051, and the 5th chip IC 5 is selected the chip CD4069 being comprised of six COS/MOS inverter circuits.
As shown in Figure 9 and Figure 10, serial data reception, demonstration and the storage of epigynous computer section are to be write and made by VC++.Native system can receive the real-time voltage value of the electrode that multiway analog switch controls in real time, and is stored etc. pending.
Display section mainly shows patient number, patient name, and electrode numbering, the scanning time started, during the end of scan 5, breast numbering, resonant frequency, Scan out.
Communication protocol: the communication of upper and lower computer communicates by corresponding software protocol is set, and software protocol content comprises: the data signal of data frame head, serial ports selection, data format, each path electrode, data storage method etc.Whether host computer is opened serial ports inquiry slave computer reception buffer zone all the time data, in slave computer, have after the voltage data of AD conversion, serial ports occurs and interrupt sending a frame partial data to host computer, host computer receives that data are sent in document and store etc. pending.
The operation principle of apparatus of the present invention: in this cover system, carry out identical scanning imaging system, measurement and record data process on two breast.Host computer receives the frequency sweep amplitude response voltage signal of the 200KHz-800KHz by each electrode on the breast of both sides of slave computer transmission, can draw thus two groups, and every group is comprised of six frequency sweep amplitude response voltage signal curves.Based on impedance matching circuit and mammary gland tissue generation resonance principle, the feature relevant to symmetry in two suite lines extracted, adopt artificial neural network (ANN) classification, the methods such as support vector machine (SVM) classification are to mammary cancer risk layering, i.e. " high-risk " crowd and " low-risk " crowd.By the classification results of this several method, with clinical diagnosis interpretation of result comparison, and draw one group of experimenter's characteristic working curve (ROC curve).ROC curve is the aggregative indicator of reflection sensitivity and specificity continuous variable, and it is that to take True Positive Rate (sensitivity) be vertical coordinate, and false negative rate (1-specificity) is the curve of abscissa drafting.
By AUC(, refer to ROC area under a curve), pass judgment on the diagnostic value of this device.Larger AUC value, experimenter's work of the ROC Curves representative in the close upper left corner is the most accurate, so AUC is larger, diagnostic accuracy is higher.
Other components selection: the STC12C5A60S2/AD/PWM series monolithic that slave computer selects macrocrystalline science and technology to produce.The high performance operational amplifier OPA452 that the Dou Shi BB company that the first amplifier A1 and the second amplifier A2 select produces.