CN102655169B - Semiconductor device with overvoltage protection and two-way polarity device based on semiconductor device - Google Patents
Semiconductor device with overvoltage protection and two-way polarity device based on semiconductor device Download PDFInfo
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- CN102655169B CN102655169B CN201210116554.9A CN201210116554A CN102655169B CN 102655169 B CN102655169 B CN 102655169B CN 201210116554 A CN201210116554 A CN 201210116554A CN 102655169 B CN102655169 B CN 102655169B
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Abstract
The invention relates to a semiconductor device, in particular relates to a semiconductor device with overvoltage protection and a two-way polarity device based on the semiconductor device. The semiconductor device is implemented by the following technical scheme: the semiconductor device comprises a substrate, first areas and second areas, wherein the upper part of each first area is at least provided with one second area; a first opening area is formed between the adjacent first areas on the substrate; each first opening area is provided with a third area which is used for connecting the substrate and the adjacent first areas and is of a second conduction type; the lower part of the substrate is provided with a fourth area which is of the second conduction type; a first insulating layer is arranged above the third area, extends along the two sides corresponding to the third area and covers a part of the first area; the second area and the first area are respectively connected with a first metal contact; and the fourth area is connected with a second metal contact. The semiconductor device has the advantages that the overcurrent performance is higher and the reliability of the device is improved.
Description
Technical field
The present invention relates to semiconductor device, particularly a kind of have the semiconductor device of overvoltage protection and a two-way polarity device based on this device.
Background technology
Known invention multilayered semiconductor protection device, in the place in the intersection adjacent cathodes region of negative electrode base and anode base, place a low puncture voltage region, be similar to a trigger, and this trigger extension is connected across on two bases, if the U.S. Patent number of L.R. Avery is 5, 072, 273 patent is announced low trigger voltage semiconductor protection device, the conduction mode of this device is better than relying on the method for PN junction puncture voltage between anode base and negative electrode base, solve because the defect of semi-conducting material itself cannot make breakdown threshold voltage and on the whole border of PN junction between described base, reached the problem of uniformity, but also limit this kind of overcurrent ability to bear that protection device is total simultaneously.
As shown in Figure 1, multilayered semiconductor overvoltage protector of the prior art is by forming below: N-type substrate 1, territory, p type island region 2, P+ region 1, N+ region 1, N+ region 25, N+ region 36, P+ region 27, connect P+ region 1 and N+ region 1 Metal Contact 1, be connected the Metal Contact 29 in N+ region 36 and P+ region 27, when add bias voltage between Metal Contact 1 and Metal Contact 29, Metal Contact 1 is negative with respect to Metal Contact 29, PN junction between N-type substrate 1 and territory, p type island region 2 and between N+ region 25 and territory, p type island region 2 is reverse biased, because the potential gradient of PN junction between N+ region 25 and territory, p type island region 2 is higher than the potential gradient of PN junction between N-type substrate 1 and territory, p type island region 2, PN junction puncture required electric field strength first the PN junction between N+ region 25 and territory, p type island region 2 form, the breakdown current of the PN junction between N+ region 25 and territory, p type island region 2 increases, cause increasing from the electrical potential difference between part N+ region 1 and the territory, p type island region 2 of P+ region one 3 distal-most end, can be from N+ region 1 to territory, p type island region 2 to electronics until the PN junction potential barrier at this place is enough low, and then these electronics are collected by back-biased PN junction between N-type substrate 1 and territory, p type island region 2, make the negative electrical charge occurring at N-type substrate 1 be gathering shape, thereby reduce the barrier height of PN junction between N-type substrate 1 and P+ region 27, make hole flow into N-type substrate 1 from P+ region 27, these holes can be collected by PN junction between N-type substrate 1 and territory, p type island region 2, thereby further cause electronics to flow out from N+ region 1, this positive feedback mechanism finally causes this multilayer device to enter the conducting state of low-resistance.
Visible, turn on process betides the edge in N+ region 1, and the current density of the PN junction between territory, p type island region 2 and N+ region 1 will easily and comparatively fast reach the critical value can bear of semi-conducting material, thus fragile device.
Summary of the invention
The object of this invention is to provide a kind of semiconductor device with overvoltage protection, it has higher overcurrent performance, has improved the reliability of device.
Above-mentioned technical purpose of the present invention is achieved by the following technical programs: have the semiconductor device of overvoltage protection, it comprises:
Be the substrate of the first conduction type,
Be located at the first area that at least two of described substrate top are the second conduction type,
Be located at the second area that is the first conduction type on top, described first area;
The top of each first area is at least provided with a second area; Described substrate forms the first open area between adjacent first area; Each the first open area place is provided with the 3rd region that is the second conduction type that connects described substrate and adjacent first area;
The bottom of described substrate is provided with the 4th region that is the second conduction type; Described the 3rd top, region is provided with the first insulating barrier, and described the first insulating barrier extends and first area, cover part along the both sides in corresponding the 3rd region; Second area and first area are all connected with the first Metal Contact; Described the 4th joint area has the second Metal Contact.
In turn on process, because puncture voltage can flow into two adjacent first areas by the 3rd region simultaneously, thereby strengthen the electrical potential difference at the second area edge in these two first areas simultaneously, thereby background technology relatively, the present invention has higher overcurrent capability, has improved the reliability of device.
The present invention also aims to provide a kind of two-way polar semiconductor device with overvoltage protection, it comprises:
Be the substrate of the first conduction type,
Be located at the first area that at least two of described substrate top are the second conduction type,
Be located at the 5th region that at least two of described substrate bottom are the second conduction type,
Be located at the second area that is the first conduction type on top, described first area,
Be located at the 6th region that is the first conduction type of described the 5th bottom, region;
The top of each first area is at least provided with a second area; The bottom in each the 5th region is at least provided with the 6th region;
Described substrate forms the first open area between adjacent first area; Each the first open area place is provided with the 3rd region that is the second conduction type that connects described substrate and adjacent first area;
Described substrate forms the second open area between adjacent the 5th region; Each the second open area place is provided with a SECTOR-SEVEN territory that is the second conduction type that connects described substrate and adjacent the 5th region;
Described the 3rd top, region is provided with the first insulating barrier, and described corresponding the first insulating barrier extends and first area, cover part along the both sides in corresponding the 3rd region;
The below in described SECTOR-SEVEN territory is provided with the second insulating barrier, and described corresponding the second insulating barrier extends and the 5th region, cover part along the both sides in corresponding SECTOR-SEVEN territory;
Second area and first area are all connected with the first Metal Contact; The 5th region and the 6th region are all connected with the 3rd Metal Contact.
In sum, the present invention has following beneficial effect: the present invention, in turn on process, has higher overcurrent capability, thereby has improved device reliability of operation, has also improved useful life.
Brief description of the drawings
Fig. 1 is background technology structural representation;
Fig. 2 is embodiment 1 structural representation;
Fig. 3 is embodiment 2 structural representations.
In figure, 1, N-type substrate, 2, territory, p type island region, 3, P+ region one, 4, N+ region one, 5, N+ region two, 6, N+ region three, 7, P+ region two, 8, Metal Contact one, 9, Metal Contact two, 10, substrate, 11, first area, 12, the first open area, 13, second area, 14, the 3rd region, 15, the 4th region, 16, the first insulating barrier, 17, the first Metal Contact, 18, the second Metal Contact, 19, the 5th region, 20, the 6th region, 21, the second open area, 22, SECTOR-SEVEN territory, 23, the second insulating barrier, 24, the 3rd Metal Contact.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
This specific embodiment is only explanation of the invention; it is not limitation of the present invention; those skilled in the art are reading after this specification and can make to the present embodiment the amendment that there is no creative contribution as required, but as long as within the scope of claim of the present invention, are all subject to the protection of Patent Law.
Embodiment 1: a kind of semiconductor device with overvoltage protection, as shown in Figure 2, it comprises:
Be the substrate 10 of the first conduction type,
Be located at the first area 11 that at least two of described substrate 10 tops are the second conduction type,
Be located at the second area that is the first conduction type 13 on 11 tops, described first area;
The top of each first area 11 is at least provided with a second area 13; Described substrate 10 forms the first open area 12 between adjacent first area 11; 12 places, each the first open area are provided with the 3rd region 14 that is the second conduction type that connects described substrate 10 and adjacent first area 11;
The bottom of described substrate 10 is provided with the 4th region 15 that is the second conduction type; 14 tops, described the 3rd region are provided with the first insulating barrier 16, and described the first insulating barrier 16 extends and first area, cover part 11 along the both sides in corresponding the 3rd region 14; Second area 13 is all connected with the first Metal Contact 17 with first area 11; Described the 4th region 15 is connected with the second Metal Contact 18.
Described the first conduction type is N-type, and described the second conduction type is P type.
When add bias voltage between the first Metal Contact 17 and the second Metal Contact 18, the first Metal Contact 17 is negative with respect to the second Metal Contact 18, PN junction between PN junction, first area 11 and the 3rd region 14 between substrate 10 and first area 11, is reverse biased, because the electric-force gradient of the PN junction between first area 11 and the 3rd region 14 is higher than the electric-force gradient of PN junction between substrate 10 and first area 11, so puncture the PN junction first betiding between first area 11 and the 3rd region 14, along with the increase of breakdown current, cause the electrical potential difference between second area 13 and first area 11 to increase, when PN junction is herein down to when enough low, electronics enters first area 11 from second area 13, these electronics are collected by back-biased PN junction between substrate 10 and first area 11, and these electronics are gathering shape at substrate 10, thereby reduce the barrier height of PN junction between substrate 10 and the 4th region 15, thereby make hole flow into substrate 10 from the 4th region 15, make these holes collected by the PN junction between substrate 10 and first area 11, thereby further cause electronics to flow out from second area 13, this positive feedback mechanism finally causes the present embodiment to enter low-resistance conducting state.
In turn on process, because puncture voltage can flow into two adjacent first areas 11 that are positioned at 12 both sides, corresponding the first open area by the 3rd region 14 simultaneously, thereby strengthen the electrical potential difference at second area 13 edges in these two first areas 11 simultaneously, thereby make the present embodiment there is higher overcurrent capability.
The present embodiment can adopt common technology, as: photoetching, Implantation, diffusion, vacuum and plasma process preparation, can also adopt semiconductor planar technique simultaneously, also can adopt semiconductor one side and/or the preparation of two-sided mesa technique.
Embodiment 2: a kind of two-way polar semiconductor device with overvoltage protection, as shown in Figure 3, it comprises:
Be the substrate 10 of the first conduction type,
Be located at the first area 11 that at least two of described substrate 10 tops are the second conduction type,
Be located at the 5th region 19 that at least two of described substrate 10 bottoms are the second conduction type,
Be located at the second area that is the first conduction type 13 on 11 tops, described first area,
Be located at the 6th region 20 that is the first conduction type of 19 bottoms, described the 5th region;
The top of each first area 11 is at least provided with a second area 13; The bottom in each the 5th region 19 is at least provided with the 6th region 20;
Described substrate 10 forms the first open area 12 between adjacent first area 11; 12 places, each the first open area are provided with the 3rd region 14 that is the second conduction type that connects described substrate 10 and adjacent first area 11;
Described substrate 10 forms the second open area 21 between adjacent the 5th region 19; 21 places, each the second open area are provided with a SECTOR-SEVEN territory 22 that is the second conduction type that connects described substrate 10 and adjacent the 5th region 19;
14 tops, described the 3rd region are provided with the first insulating barrier 16, and described corresponding the first insulating barrier 16 extends and first area, cover part 11 along the both sides in corresponding the 3rd region 14;
The below in described SECTOR-SEVEN territory 22 is provided with the second insulating barrier 23, and described corresponding the second insulating barrier 23 extends and the 5th region 19, cover part along the both sides in corresponding SECTOR-SEVEN territory 22;
Second area 13 is all connected with the first Metal Contact 17 with first area 11; The 5th region 19 and the 6th region 20 are all connected with the 3rd Metal Contact 24.
Described the first conduction type is N-type, and described the second conduction type is P type.
The conduction mode of the present embodiment is similar to Example 1, and can realize two-way admittance.
The present embodiment can adopt common technology, as: photoetching, Implantation, diffusion, vacuum and plasma process preparation, can also adopt semiconductor planar technique simultaneously, also can adopt semiconductor one side and/or the preparation of two-sided mesa technique.
Claims (2)
1. a semiconductor device with overvoltage protection, is characterized in that, it comprises:
Be the substrate (10) of the first conduction type,
Be located at the first area (11) that at least two of described substrate (10) top are the second conduction type,
Be located at the second area that is the first conduction type (13) on top, described first area (11);
The top of each first area (11) is at least provided with a second area (13); Described substrate (10) forms the first open area (12) between adjacent first area (11); The 3rd region (14) that is the second conduction type that connects described substrate (10) and adjacent first area (11) is located to be provided with in each the first open area (12);
The bottom of described substrate (10) is provided with the 4th region (15) that is the second conduction type; Described the 3rd top, region (14) is provided with the first insulating barrier (16), and described corresponding the first insulating barrier (16) extends and first area, cover part (11) along the both sides in corresponding the 3rd region (14); Second area (13) is all connected with the first Metal Contact (17) with first area (11); Described the 4th region (15) is connected with the second Metal Contact (18).
2. a two-way polar semiconductor device with overvoltage protection, is characterized in that, it comprises:
Be the substrate (10) of the first conduction type,
Be located at the first area (11) that at least two of described substrate (10) top are the second conduction type,
Be located at the 5th region (19) that at least two of described substrate (10) bottom are the second conduction type,
Be located at the second area that is the first conduction type (13) on top, described first area (11),
Be located at the 6th region (20) that is the first conduction type of described the 5th bottom, region (19);
The top of each first area (11) is at least provided with a second area (13); The bottom in each the 5th region (19) is at least provided with the 6th region (20);
Described substrate (10) forms the first open area (12) between adjacent first area (11); The 3rd region (14) that is the second conduction type that connects described substrate (10) and adjacent first area (11) is located to be provided with in each the first open area (12);
Described substrate (10) forms the second open area (21) between adjacent the 5th region (19); A SECTOR-SEVEN territory (22) that is the second conduction type that connects described substrate (10) and adjacent the 5th region (19) is located to be provided with in each the second open area (21);
Described the 3rd top, region (14) is provided with the first insulating barrier (16), and described corresponding the first insulating barrier (16) extends and first area, cover part (11) along the both sides in corresponding the 3rd region (14);
The below in described SECTOR-SEVEN territory (22) is provided with the second insulating barrier (23), and described corresponding the second insulating barrier (23) extends and the 5th region (19), cover part along the both sides in corresponding SECTOR-SEVEN territory (22);
Second area (13) is all connected with the first Metal Contact (17) with first area (11); The 5th region (19) is all connected with the 3rd Metal Contact (24) with the 6th region (20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210116554.9A CN102655169B (en) | 2012-04-20 | 2012-04-20 | Semiconductor device with overvoltage protection and two-way polarity device based on semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210116554.9A CN102655169B (en) | 2012-04-20 | 2012-04-20 | Semiconductor device with overvoltage protection and two-way polarity device based on semiconductor device |
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| Publication Number | Publication Date |
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| CN102655169A CN102655169A (en) | 2012-09-05 |
| CN102655169B true CN102655169B (en) | 2014-07-23 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072273A (en) * | 1990-05-04 | 1991-12-10 | David Sarnoff Research Center, Inc. | Low trigger voltage SCR protection device and structure |
| US5502317A (en) * | 1993-07-14 | 1996-03-26 | Texas Instruments Incorporated | Silicon controlled rectifier and method for forming the same |
| EP0624906B1 (en) * | 1993-05-13 | 2001-08-08 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Integrated structure circuit for the protection of power devices against overvoltages |
| US7196889B2 (en) * | 2002-11-15 | 2007-03-27 | Medtronic, Inc. | Zener triggered overvoltage protection device |
| CN202585416U (en) * | 2012-04-20 | 2012-12-05 | 谢可勋 | Semiconductor device with overvoltage protection and bidirectional polarity device based on device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6815775B2 (en) * | 2001-02-02 | 2004-11-09 | Industrial Technology Research Institute | ESD protection design with turn-on restraining method and structures |
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2012
- 2012-04-20 CN CN201210116554.9A patent/CN102655169B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072273A (en) * | 1990-05-04 | 1991-12-10 | David Sarnoff Research Center, Inc. | Low trigger voltage SCR protection device and structure |
| EP0624906B1 (en) * | 1993-05-13 | 2001-08-08 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Integrated structure circuit for the protection of power devices against overvoltages |
| US5502317A (en) * | 1993-07-14 | 1996-03-26 | Texas Instruments Incorporated | Silicon controlled rectifier and method for forming the same |
| US7196889B2 (en) * | 2002-11-15 | 2007-03-27 | Medtronic, Inc. | Zener triggered overvoltage protection device |
| CN202585416U (en) * | 2012-04-20 | 2012-12-05 | 谢可勋 | Semiconductor device with overvoltage protection and bidirectional polarity device based on device |
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| CN102655169A (en) | 2012-09-05 |
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Address after: 313000 Zhejiang City, Huzhou Province, the town of Wuxing District, the town of standard factory building 2, building 1, eight Co-patentee after: ZHEJIANG MJ TECHNOLOGYCO.,LTD. Patentee after: Xie Kexun Address before: 313000 Zhejiang City, Huzhou Province, the town of Wuxing District, the town of standard factory building 2, building 1, eight Co-patentee before: ZHEJIANG MEIJING TECHNOLOGY Co.,Ltd. Patentee before: Xie Kexun |
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Effective date of registration: 20190918 Address after: 233000 Room 1402, Ziyang Building, Pearl Plaza, Huaishang District, Bengbu City, Anhui Province Patentee after: Bengbu HRABERO Intellectual Property Service Co.,Ltd. Address before: 313000 Zhejiang City, Huzhou Province, the town of Wuxing District, the town of standard factory building 2, building 1, eight Co-patentee before: ZHEJIANG MJ TECHNOLOGYCO.,LTD. Patentee before: Xie Kexun |
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Effective date of registration: 20221031 Address after: 257000 Lijin Economic Development Zone, Dongying City, Shandong Province Patentee after: SHANDONG DADONGLIAN PETROLEUM EQUIPMENT Co.,Ltd. Address before: 233000 Room 1402, Ziyang Building, Pearl Plaza, Huaishang District, Bengbu City, Anhui Province Patentee before: Bengbu HRABERO Intellectual Property Service Co.,Ltd. |
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