CN102544009A - High-mobility CMOS (complementary Metal oxide semiconductor) integrated unit - Google Patents
High-mobility CMOS (complementary Metal oxide semiconductor) integrated unit Download PDFInfo
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a high-mobility CMOS (complementary metal oxide semiconductor) integrated unit, belonging to the technical field of semiconductor integration. The high-mobility CMOS integrated unit integrates the indium gallium arsenic NMOSFET with high electron mobility and the germanium PMOSFET with high hole mobility on the monocrystalline silicon substrate in a plane mode, can realize integrated CMOS devices with different channel materials and excellent characteristics, has the potential of replacing traditional silicon-based CMOS devices, and has practical application value in the post-Mole era. The CMOS integrated unit can be integrated with traditional silicon-based devices, III-V compound semiconductor devices and other devices, so that the single-chip integration of a multifunctional module is realized, the power consumption is reduced, and the performance is improved.
Description
Technical field
The present invention relates to semiconductor integrated technology field, relate in particular to a kind of high mobility CMOS integrated unit.
Background technology
Semiconductor technology is regarded as the important symbol of weighing a national science technological progress and overall national strength as the core and the basis of information industry.In in the past more than 40 year; The integrated circuit technique that is the basis with silicon CMOS technology follow Moore's Law through the characteristic size of reduction of device improve chip operating rate, increase integrated level and reduce cost, the characteristic size of integrated circuit evolves to nanoscale by micro-meter scale.But after the grid length of MOS device was reduced to 90 nanometers, the thickness of gate oxide will be less than 1.2 nanometers, and Moore's Law begins to face the double challenge from physics and technical elements.
Academia and industrial circle generally believe: adopt the high mobility channel material to substitute the important development direction that the traditional silicon material will be the CMOS technology, wherein germanium and III-V family semiconductor channel material are most likely at recent realization large-scale application.The high preparation PMOSFET that is fit to of the hole mobility of germanium; And the high preparation NMOSFET that is fit to of the electron mobility of III-V family semi-conducting material; What tool was used potential quality in the III-V family semi-conducting material be indium gallium arsenic material, and the cmos device that indium gallium arsenic NMOSFET and germanium PMOSFET are combined becomes the problem effective way that the solution silicon base CMOS runs into.Yet with integrated emphasis and the difficult point that has become current research of indium gallium arsenic NMOSFET and germanium PMOSFET plane.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention is to provide a kind of high mobility CMOS integrated unit, so that indium gallium arsenic NMOSFET and germanium PMOSFET plane are integrated on the monocrystalline substrate, realizes having the integrated CMOS device of different channel material and excellent.
(2) technical scheme
For achieving the above object; The invention provides a kind of high mobility CMOS integrated unit; This high mobility CMOS integrated unit comprises monocrystalline substrate, resilient coating, barrier layer, P type light dope indium gallium arsenic single crystal layer, N type heavy doping indium gallium arsenic single crystal layer, first barrier layer, second barrier layer, a N type heavy doping germanium single crystal layer, the 2nd N type heavy doping germanium single crystal layer, N type light dope germanium single crystal layer, P type heavy doping germanium single crystal layer, the 3rd N type heavy doping germanium single crystal layer, indium gallium arsenic NMOSFET gate oxide, indium gallium arsenic NMOSFET grid metal level, indium gallium arsenic NMOSFET grid side wall, indium gallium arsenic NMOSFET source leakage extraction electrode, isolated area, germanium PMOSFET grid passivation layer, germanium PMOSFET gate oxide, germanium PMOSFET grid metal level, germanium PMOSFET grid side wall and germanium PMOSFET source leakage extraction electrode, and wherein indium gallium arsenic NMOSFET is raceway groove and backing material with said P type light dope indium gallium arsenic single crystal layer; Germanium PMOSFET is raceway groove and backing material with said N type light dope germanium single crystal layer; Said isolated area is isolated with said indium gallium arsenic NMOSFET and said germanium PMOSFET; Said monocrystalline substrate is positioned at the bottom of said high mobility CMOS integrated unit; Said resilient coating is stacked on said monocrystalline substrate; Said barrier layer is stacked on the said resilient coating; Said P type light dope indium gallium arsenic single crystal laminated is on said barrier layer.
In the such scheme, said resilient coating is used to filter dislocation, discharges stress, and said resilient coating is the GaAs of low-temperature epitaxy, and its surface is complementary with lattice of said barrier layer material, and said buffer layer thickness is between 1 nanometer to 3 micron; Said barrier layer is the single crystalline layer of GaAs or indium gallium phosphorus, each atomicity ratio indium in the indium gallium phosphorus: gallium: phosphorus=0.5: 0.5: 1, the thickness of said barrier layer is between 1 nanometer to 2 micron.
In the such scheme; Indium, gallium, arsenic atomicity ratio indium in said P type light dope indium gallium arsenic single crystal layer and the said N type heavy doping indium gallium arsenic single crystal layer: gallium: arsenic=x: (1-x): 1; The span of x can be set between 0＜x＜0.6, and the thickness of said P type light dope indium gallium arsenic single crystal layer is between 1 nanometer to 100 nanometer.
In the such scheme; Said first barrier layer and said second barrier layer are used to suppress its germanium single crystal and counterdiffusion doping effect between the indium gallium arsenic single crystal up and down; And improve said indium gallium arsenic NMOSFET gate dielectric layer and channel interface; Reduce interface state density, said first barrier layer, said P type light dope indium gallium arsenic single crystal layer and said barrier layer form the superlattice SQW simultaneously, help improving said indium gallium arsenic NMOSFET channel electron mobility; Said first barrier layer and said second barrier layer are the single crystalline layer of indium phosphide, gallium phosphide, indium aluminium phosphorus, indium gallium phosphorus, aluminum phosphate or gallium aluminium phosphorus; Each atomicity ratio indium in the indium aluminium phosphorus: aluminium: phosphorus=y: (1-y): 1; The span of y can be set between 0＜y＜1; Each atomicity ratio indium in the indium gallium phosphorus: gallium: phosphorus=z: (1-z): 1, the span of z can be set between 0＜z＜1, each atomicity ratio indium in the gallium aluminium phosphorus: gallium: phosphorus=a: (1-a): 1; The span of a is set between 0＜a＜1; Said first barrier layer and the said second barrier layer difference are that first barrier layer is doped single crystal layer not, and said second barrier layer is the heavy doping of N type, and the thickness on said first barrier layer and said second barrier layer is between 3 dust to 20 nanometers.
In the such scheme; The raceway groove of said indium gallium arsenic NMOSFET and substrate are said P type light dope indium gallium arsenic single crystal layer; P type light dope element is one or more of magnesium, beryllium, zinc; The grid of said indium gallium arsenic NMOSFET are followed successively by said first barrier layer, said indium gallium arsenic NMOSFET gate oxide and said indium gallium arsenic NMOSFET grid metal level from bottom to up, and both sides are indium gallium arsenic NMOSFET grid side walls; Said first barrier layer is on said P type light dope indium gallium arsenic single crystal layer; Said indium gallium arsenic NMOSFET gate oxide is the oxide of high-k; That these oxides comprise is aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, tantalum base oxide; Doped chemical in the oxide can be aluminium, zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, phosphorus; Ratio=the m of the atomic quantity of the atomic quantity of doped chemical and total metallic element in the oxide: (1-m), the span of m can be set to 0≤m＜1, and the thickness of said indium gallium arsenic NMOSFET gate oxide is between 3 dust to 100 nanometers; One deck or above multiple metal material layer multiple layer combination that said indium gallium arsenic NMOSFET grid metal level is tantalum nitride, titanium nitride, gold, titanium, nickel, platinum or aluminium form, and said indium gallium arsenic NMOSFET grid side wall is silicon dioxide, silicon nitride or nitrogen-oxygen-silicon.
In the such scheme; The source of said indium gallium arsenic NMOSFET is followed successively by said N type heavy doping indium gallium arsenic single crystal layer, said second barrier layer, said the 2nd N type heavy doping germanium single crystal layer, said the 3rd N type heavy doping germanium single crystal layer and said indium gallium arsenic NMOSFET source leakage extraction electrode composition from bottom to up with leaking; Wherein said N type heavy doping indium gallium arsenic single crystal layer, said second barrier layer are identical with the doping content of said the 3rd N type heavy doping germanium single crystal layer; The doping content of said the 2nd N type heavy doping germanium single crystal layer is the doping content sum of an above-mentioned N type heavy doping indium gallium arsenic single crystal layer doping content and a said N type heavy doping germanium single crystal layer; The heavy doping element is one or more of nitrogen, phosphorus, sulphur, selenium, tellurium; Said indium gallium arsenic NMOSFET source leakage extraction electrode is that one or more layers metallization of nickel, gold, nisiloy, palladium, titanium, copper, platinum, zinc, cadmium forms; The thickness of said N type heavy doping indium gallium arsenic single crystal layer is between 3 dust to 50 nanometers, and upper surface and said P type light dope indium gallium arsenic single crystal layer are at same horizontal plane.
In the such scheme, a said N type heavy doping germanium single crystal layer is identical with the thickness of said the 2nd N type heavy doping germanium single crystal layer, between 3 dusts-50 nanometer; Said N type light dope germanium single crystal layer is identical with the thickness of said the 3rd N type heavy doping germanium single crystal layer, and between 1 nanometer-200 nanometer, the thickness of P type heavy doping germanium single crystal layer is less than the thickness of said N type light dope germanium single crystal layer.
In the such scheme, said germanium PMOSFET is N type light dope raceway groove and backing material with said N type light dope germanium single crystal layer, and doped chemical can be one or more of nitrogen, phosphorus, sulphur, selenium, tellurium.The grid of said germanium PMOSFET are followed successively by said germanium PMOSFET grid passivation layer, said germanium PMOSFET gate oxide and said germanium PMOSFET grid metal level from bottom to up; Both sides are said germanium PMOSFET grid side wall; Said germanium PMOSFET grid passivation layer can be silicon, germanium oxynitride, silica, aluminium nitride, alumina nitrogen; The channel interface of the said germanium PMOSFET of passivation reduces interface state density, and thickness is between 3 dusts-50 nanometer; Said germanium PMOSFET gate oxide can be the oxide of high-k; Comprise aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, tantalum base oxide, the doped chemical in the oxide can be aluminium, zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, phosphorus, the ratio=n of the atomic quantity of the atomic quantity of doped chemical and total metallic element in the oxide: (1-n); The span of n can be set to 0≤n＜1; The thickness of said germanium PMOSFET gate oxide is between 3 dusts-100 nanometer, and said germanium PMOSFET grid metal level can form for the one deck or the above multiple metal material layer multilevel metallization of tantalum nitride, titanium nitride, gold, titanium, nickel, platinum or aluminium, and said germanium PMOSFET grid side wall can be silicon dioxide, silicon nitride or nitrogen-oxygen-silicon.
In the such scheme; The source of said germanium PMOSFET is leaked and is leaked extraction electrode by said P type heavy doping germanium single crystal layer and said germanium PMOSFET source and form, and the doped chemical in the said P type heavy doping germanium single crystal layer can be one or more of boron, magnesium, beryllium, aluminium, gallium, zinc; Extraction electrode and said indium gallium arsenic NMOSFET source are leaked in said germanium PMOSFET source, and to leak extraction electrode identical, can be that one or more layers metallization of nickel, gold, silicon, palladium, titanium, copper, platinum, zinc, cadmium is drawn and formed.
In the such scheme, indium gallium arsenic NMOSFET and germanium PMOSFET are kept apart by isolated area in the said high mobility CMOS integrated unit.Said isolated area can be silicon dioxide, silicon nitride or nitrogen-oxygen-silicon, and the degree of depth of said isolated area is greater than the thickness sum of said P type light dope indium gallium arsenic single crystal layer, said first barrier layer, a said N type heavy doping germanium single crystal layer and said N type light dope germanium single crystal layer.
In the such scheme, said indium gallium arsenic NMOSFET and said germanium PMOSFET are integrated on the monocrystalline substrate, and the source of said indium gallium arsenic NMOSFET and germanium PMOSFET and the upper surface of leakage are in same plane.
In the such scheme; The source of said indium gallium arsenic NMOSFET is higher than indium gallium arsenic raceway groove upper surface with the leakage upper surface; Have the source and leak the effect that promotes, the source is made up of said N type heavy doping indium gallium arsenic single crystal layer, said second barrier layer, said the 2nd N type heavy doping germanium single crystal layer and said the 3rd N type heavy doping germanium single crystal layer with leaking from bottom to up successively.
In the such scheme, it all is the germanium single crystal layer that upper surface is leaked in the source of said indium gallium arsenic NMOSFET and said germanium PMOSFET, can adopt metal of the same race to metallize and draw, and can realize simultaneously that the metallic electrode of indium gallium arsenic NMOSFET and germanium PMOSFET source leakage is drawn.
In the such scheme; A said N type heavy doping germanium single crystal layer is between said barrier layer and said N type light dope germanium single crystal layer; Communicating in order to source leakage, first barrier layer, the P type light dope indium gallium arsenic single crystal layer that prevents germanium PMOSFET forms path and causes component failure, and the thickness of a said N type heavy doping germanium single crystal layer is between 3 dust to 50 nanometers.
In the such scheme; Said first barrier layer, said P type light dope indium gallium arsenic single crystal layer and said barrier layer form the superlattice SQW; Charge carrier is confined to said P type light dope indium gallium arsenic single crystal layer channel surface, reduces scattering, improve said indium gallium arsenic NMOSFET channel electron mobility.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
This high mobility CMOS integrated unit provided by the invention, the source region of indium gallium arsenic NMOSFET and drain region and raceway groove have the effect that lifting is leaked in the source not at same horizontal plane, help reducing the source-drain series resistance of NMOSFET, improve the characteristic of indium gallium arsenic NMOSFET.The upper surface that leak in the source of indium gallium arsenic NMOSFET and germanium PMOSFET is in same plane, and indium gallium arsenic NMOSFET and germanium PMOSFET are that the plane is integrated, help the expansion of CMOS integrated technology subsequent technique.It all is germanium single crystal that upper surface is drawn in the source leakage of indium gallium arsenic NMOSFET and germanium PMOSFET; Can adopt metallization of the same race and metal of the same race to draw; Can realize simultaneously that metallization and the electrode that leak in indium gallium arsenic NMOSFET and germanium PMOSFET source draw, the minimizing processing step reduces cost.The gate medium of indium gallium arsenic NMOSFET is made up of barrier layer and gate oxide lamination; With directly gate oxide growth is compared on channel material; There is the gate medium on barrier layer can effectively reduce the channel interface density of states; And barrier layer, P type light dope indium gallium arsenic single crystal layer, barrier layer can form the superlattice SQW, reduce the channel electrons scattering, improve electron mobility.And indium gallium arsenic NMOSFET and germanium PMOSFET be integrated on monocrystalline substrate and the III-V family semi-conducting material, and this device can integrate with traditional silicon base device and III-V family device, realizes that many device blocks monolithic is integrated, reduces power consumption, improves performance.
Description of drawings
Fig. 1 is the structural representation of high mobility CMOS integrated unit provided by the present invention; Wherein, 1 is monocrystalline substrate; 2 is resilient coating; 3 is barrier layer; 4a is a P type light dope indium gallium arsenic single crystal layer; 4b is a N type heavy doping indium gallium arsenic single crystal layer; 5a is first barrier layer; 5b is second barrier layer; 6a is a N type heavy doping germanium single crystal layer; 6b is the 2nd N type heavy doping germanium single crystal layer; 6c is a N type light dope germanium single crystal layer; 6d is a P type heavy doping germanium single crystal layer; 6e is the 3rd N type heavy doping germanium single crystal layer; 7 is indium gallium arsenic NMOSFET gate oxide; 8 is indium gallium arsenic NMOSFET grid metal levels; 9 is indium gallium arsenic NMOSFET grid side walls; 10 is that extraction electrode is leaked in indium gallium arsenic NMOSFET source; 11 is isolated area; 12 is germanium PMOSFET grid passivation layers; 13 is germanium PMOSFET gate oxide; 14 is germanium PMOSFET grid metal levels; 15 is germanium PMOSFET grid side walls; 16 is that extraction electrode is leaked in germanium PMOSFET source.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Present embodiment specifically describes a kind of high mobility CMOS integrated unit provided by the present invention.
As shown in Figure 1; High mobility CMOS integrated unit provided by the present invention, said high mobility CMOS integrated unit comprise monocrystalline substrate 1, resilient coating 2, barrier layer 3, P type light dope indium gallium arsenic single crystal layer 4a, N type heavy doping indium gallium arsenic single crystal layer 4b, the first barrier layer 5a, the second barrier layer 5b, a N type heavy doping germanium single crystal layer 6a, the 2nd N type heavy doping germanium single crystal layer 6b, N type light dope germanium single crystal layer 6c, P type heavy doping germanium single crystal layer 6d, the 3rd N type heavy doping germanium single crystal layer 6e, indium gallium arsenic NMOSFET gate oxide 7, indium gallium arsenic NMOSFET grid metal level 8, indium gallium arsenic NMOSFET grid side wall 9, indium gallium arsenic NMOSFET source leakage extraction electrode 10, isolated area 11, germanium PMOSFET grid passivation layer 12, germanium PMOSFET gate oxide 13, germanium PMOSFET grid metal level 14, germanium PMOSFET grid side wall 15 and germanium PMOSFET source leakage extraction electrode 16.
As shown in Figure 1, said monocrystalline substrate 1 is positioned at the bottom of said high mobility CMOS integrated unit; Said resilient coating 2 is stacked on the said monocrystalline substrate 1; Said barrier layer 3 is stacked on the said resilient coating 2; Said P type light dope indium gallium arsenic single crystal layer 4a is stacked on the said barrier layer 3.
As shown in Figure 1, the effect of said resilient coating 2 is that filter bit is wrong, discharges stress, and said resilient coating can be the GaAs of low-temperature epitaxy, and its surface is complementary with the lattice of barrier layer material, and said buffer layer thickness is 1 micron; Said barrier layer 3 can be GaAs, and the thickness of said barrier layer 3 is 1.5 microns;
Like Fig. 1, the raceway groove of indium gallium arsenic NMOSFET and substrate are said P type light dope indium gallium arsenic single crystal layer 4a in the said high mobility CMOS integrated unit, and doped chemical is a beryllium, and doping content is 5*10
17Cm
-3The grid of indium gallium arsenic NMOSFET are followed successively by the said first barrier layer 5a, said indium gallium arsenic NMOSFET gate oxide 7 and said indium gallium arsenic NMOSFET grid metal level 8 from bottom to up in the said high mobility CMOS integrated unit; Both sides are said indium gallium arsenic NMOSFET grid side wall 9; The said first barrier layer 5a is on said P type light dope indium gallium arsenic single crystal layer 4a, and said indium gallium arsenic NMOSFET gate oxide 7 is an aluminium oxide, and the thickness of said alumina layer is 10 nanometers; Said indium gallium arsenic NMOSFET grid metal level 8 is a tantalum nitride, and said indium gallium arsenic NMOSFET grid side wall 9 is a silicon dioxide.
As shown in Figure 1; The source of indium gallium arsenic NMOSFET is followed successively by said N type heavy doping indium gallium arsenic single crystal layer 4b, the said second barrier layer 5b, said the 2nd N type heavy doping germanium single crystal layer 6b, said the 3rd N type heavy doping germanium single crystal layer 6e and said indium gallium arsenic NMOSFET source leakage extraction electrode 10 compositions from bottom to up with leaking in the said high mobility CMOS integrated unit; The doping content of wherein said N type heavy doping indium gallium arsenic single crystal layer 4b, the said second barrier layer 5b and said the 3rd N type heavy doping germanium single crystal layer 6e is basic identical; Doped chemical is a sulphur, and doping content is 5*10
19Cm
-3, the doping content of said the 2nd N type heavy doping germanium single crystal layer 6b is 1*10
20Cm
-3, the doped chemical p and s respectively accounts for half the; It is nickel that extraction electrode 10 is leaked in said indium gallium arsenic NMOSFET source, and in metallization processes, nickel and germanium reaction generate germanium nickel, form ohmic contact; The thickness of said N type heavy doping indium gallium arsenic single crystal layer 4b is 20 nanometers, and the upper surface of said N type heavy doping indium gallium arsenic single crystal layer 4b and said P type light dope indium gallium arsenic single crystal layer 4a are at same horizontal plane.
As shown in Figure 1, indium, gallium, arsenic atomicity ratio indium among said P type light dope indium gallium arsenic single crystal layer 4a and the said N type heavy doping indium gallium arsenic single crystal layer 4b: gallium: arsenic=0.1: 0.9: 1, the thickness of said P type light dope indium gallium arsenic single crystal layer 4a is 60 nanometers; Said first barrier layer 5a and the said second barrier layer 5b are indium gallium phosphorus single crystalline layer; Each atomicity ratio indium in the gallium aluminium phosphorus: gallium: phosphorus=0.5: 0.5: 1; Said first barrier layer 5a and the said second barrier layer 5b difference are that the first barrier layer 5a is not for mixing; And the said second barrier layer 5b is the heavy doping of N type, and the thickness of said first barrier layer 5a and the said second barrier layer 5b is 3 nanometers; The thickness of said N type heavy doping germanium single crystal layer 6a and said the 2nd N type heavy doping germanium single crystal layer 6b is all 20 nanometers mutually, and the doped chemical of a said N type heavy doping germanium single crystal layer 6a is a phosphorus, and doping content is 5*10
19Cm
-3The thickness of said N type light dope germanium single crystal layer 6c and said the 3rd N type heavy doping germanium single crystal layer 6e is all 60 nanometers mutually.
As shown in Figure 1, germanium PMOSFET is raceway groove and backing material with said N type light dope germanium single crystal layer 6c in the said high mobility CMOS integrated unit, and doped chemical is a phosphorus, and doping content is 5*10
17Cm
-3The grid of said germanium PMOSFET are followed successively by said germanium PMOSFET grid passivation layer 12, said germanium PMOSFET gate oxide 13 and said germanium PMOSFET grid metal level 14 from bottom to up, and both sides are said germanium PMOSFET grid side wall 15; Said germanium PMOSFET grid passivation layer 12 is a germanium oxynitride, and thickness is 2 nanometers; Said germanium PMOSFET gate oxide 13 can be aluminium oxide, and the thickness of said germanium PMOSFET gate oxide 13 is 10 nanometers; Said germanium PMOSFET grid metal level 14 is a titanium nitride; Said germanium PMOSFET grid side wall 15 is a silicon dioxide.
As shown in Figure 1; The source of germanium PMOSFET is formed with leaking by said P type heavy doping germanium single crystal layer 6d and said germanium PMOSFET source leakage extraction electrode 16 in the said high mobility CMOS integrated unit; Doped chemical among the said P type heavy doping germanium single crystal layer 6d is a boron, and doping content is 5*10
19Cm
-3, extraction electrode 16 and said indium gallium arsenic NMOSFET source are leaked in said germanium PMOSFET source, and to leak extraction electrode 10 identical also be nickel, in the preparation process, and nickel and germanium interfacial reaction generation germanium nickel, formation ohmic contact.
As shown in Figure 1, indium gallium arsenic NMOSFET and said germanium PMOSFET are kept apart by isolated area 11 described in the said high mobility CMOS integrated unit.Said isolated area 11 is a silicon dioxide, and the degree of depth of said isolated area is 200 nanometers.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. high mobility CMOS integrated unit; It is characterized in that; This high mobility CMOS integrated unit comprises monocrystalline substrate, resilient coating, barrier layer, P type light dope indium gallium arsenic single crystal layer, N type heavy doping indium gallium arsenic single crystal layer, first barrier layer, second barrier layer, a N type heavy doping germanium single crystal layer, the 2nd N type heavy doping germanium single crystal layer, N type light dope germanium single crystal layer, P type heavy doping germanium single crystal layer, the 3rd N type heavy doping germanium single crystal layer, indium gallium arsenic NMOSFET gate oxide, indium gallium arsenic NMOSFET grid metal level, indium gallium arsenic NMOSFET grid side wall, indium gallium arsenic NMOSFET source leakage extraction electrode, isolated area, germanium PMOSFET grid passivation layer, germanium PMOSFET gate oxide, germanium PMOSFET grid metal level, germanium PMOSFET grid side wall and germanium PMOSFET source leakage extraction electrode, and wherein indium gallium arsenic NMOSFET is raceway groove and backing material with said P type light dope indium gallium arsenic single crystal layer; Germanium PMOSFET is raceway groove and backing material with said N type light dope germanium single crystal layer; Said isolated area is isolated with said indium gallium arsenic NMOSFET and said germanium PMOSFET; Said monocrystalline substrate is positioned at the bottom of said high mobility CMOS integrated unit; Said resilient coating is stacked on said monocrystalline substrate; Said barrier layer is stacked on the said resilient coating; Said P type light dope indium gallium arsenic single crystal laminated is on said barrier layer.
2. high mobility CMOS integrated unit according to claim 1; It is characterized in that; Said resilient coating is used to filter dislocation, discharges stress, and said resilient coating is the GaAs of low-temperature epitaxy; Its surface is complementary with lattice of said barrier layer material, and said buffer layer thickness is between 1 nanometer to 3 micron; Said barrier layer is the single crystalline layer of GaAs or indium gallium phosphorus, each atomicity ratio indium in the indium gallium phosphorus: gallium: phosphorus=0.5: 0.5: 1, the thickness of said barrier layer is between 1 nanometer to 2 micron.
3. high mobility CMOS integrated unit according to claim 1; It is characterized in that; Being used to of said first barrier layer and said second barrier layer suppressed its germanium single crystal and counterdiffusion doping effect between the indium gallium arsenic single crystal up and down; And improve said indium gallium arsenic NMOSFET gate dielectric layer and channel interface; Reduce interface state density, said first barrier layer, said P type light dope indium gallium arsenic single crystal layer and said barrier layer form the superlattice SQW simultaneously, help improving said indium gallium arsenic NMOSFET channel electron mobility; Said first barrier layer and said second barrier layer are the single crystalline layer of indium phosphide, gallium phosphide, indium aluminium phosphorus, indium gallium phosphorus, aluminum phosphate or gallium aluminium phosphorus; Each atomicity ratio indium in the indium aluminium phosphorus: aluminium: phosphorus=y: (1-y): 1; The span of y can be set between 0＜y＜1; Each atomicity ratio indium in the indium gallium phosphorus: gallium: phosphorus=z: (1-z): 1, the span of z can be set between 0＜z＜1, each atomicity ratio indium in the gallium aluminium phosphorus: gallium: phosphorus=a: (1-a): 1; The span of a is set between 0＜a＜1; Said first barrier layer and the said second barrier layer difference are that first barrier layer is doped single crystal layer not, and said second barrier layer is the heavy doping of N type, and the thickness on said first barrier layer and said second barrier layer is between 3 dust to 20 nanometers.
4. high mobility CMOS integrated unit according to claim 1; It is characterized in that; The source of said indium gallium arsenic NMOSFET is higher than indium gallium arsenic raceway groove upper surface with the leakage upper surface; Have the source and leak the effect that promotes, the source of said indium gallium arsenic NMOSFET is followed successively by said N type heavy doping indium gallium arsenic single crystal layer, said second barrier layer, said the 2nd N type heavy doping germanium single crystal layer, said the 3rd N type heavy doping germanium single crystal layer and said indium gallium arsenic NMOSFET source leakage extraction electrode from bottom to up with leakage and forms.
5. high mobility CMOS integrated unit according to claim 1; It is characterized in that; Said indium gallium arsenic NMOSFET and said germanium PMOSFET are integrated on the monocrystalline substrate, and the source of said indium gallium arsenic NMOSFET and germanium PMOSFET and the upper surface of leakage are in same plane.
6. high mobility CMOS integrated unit according to claim 1; It is characterized in that; It all is the germanium single crystal layer that upper surface is leaked in the source of said indium gallium arsenic NMOSFET and said germanium PMOSFET; Can adopt metal of the same race to metallize and draw, can realize simultaneously that the metallic electrode of indium gallium arsenic NMOSFET and germanium PMOSFET source leakage is drawn.
7. high mobility CMOS integrated unit according to claim 1; It is characterized in that; A said N type heavy doping germanium single crystal layer is between said barrier layer and said N type light dope germanium single crystal layer; Communicating in order to source leakage, first barrier layer, the P type light dope indium gallium arsenic single crystal layer that prevents germanium PMOSFET forms path and causes component failure, and the thickness of a said N type heavy doping germanium single crystal layer is between 3 dust to 50 nanometers.
8. high mobility CMOS integrated unit according to claim 1; It is characterized in that the degree of depth of said isolated area is greater than the thickness sum of said P type light dope indium gallium arsenic single crystal layer, said first barrier layer, a said N type heavy doping germanium single crystal layer and said N type light dope germanium single crystal layer.
9. high mobility CMOS integrated unit according to claim 1; It is characterized in that; Said first barrier layer, said P type light dope indium gallium arsenic single crystal layer and said barrier layer form the superlattice SQW; Charge carrier is confined to said P type light dope indium gallium arsenic single crystal layer channel surface, reduces scattering, improve said indium gallium arsenic NMOSFET channel electron mobility.
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