CN109950151A - PMOS transistor and forming method thereof - Google Patents
PMOS transistor and forming method thereof Download PDFInfo
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- CN109950151A CN109950151A CN201711390693.XA CN201711390693A CN109950151A CN 109950151 A CN109950151 A CN 109950151A CN 201711390693 A CN201711390693 A CN 201711390693A CN 109950151 A CN109950151 A CN 109950151A
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Abstract
A kind of PMOS transistor and forming method thereof, forming method includes: offer substrate；Gate structure is formed over the substrate；The first epitaxial layer and the second epitaxial layer on first epitaxial layer are formed on the substrate of the gate structure two sides, second epitaxial layer is interior doped with modulation ion.By adulterating modulation ion in second epitaxial layer, to reduce the Schottky barrier between subsequent formed plug and second epitaxial layer, reduce contact resistance between the two, and then improve the performance of formed semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of PMOS transistor and forming method thereof.
Background technique
In ic manufacturing process, after forming semiconductor device structure, need each semiconductor devices being connected to one
It rises and forms circuit.With the continuous development of ic manufacturing technology, requirement of the people to the integrated level and performance of integrated circuit
Become higher and higher.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, IC interior
Current densities are increasing, and this development is so that crystal column surface can not provide enough areas to make required for custom circuit
Interconnection line.
Needed for meeting the interconnection line after critical dimension reduction, at present different metal layer or metal layer with partly lead
The conducting of body device architecture is realized by interconnection structure.Interconnection structure includes interconnection line and the plug in contact hole,
For plug in contact hole for connecting semiconductor devices, interconnection line connects the plug on different semiconductor devices, thus
Form circuit.
As integrated circuit technology node constantly reduces, the reduction of device size, the contact area of plug are smaller and smaller,
Contact resistance between plug and transistor source and drain doped region increases with it, in order to reduce between plug and source and drain doping area
Contact resistance, metal silicide are introduced between plug and source and drain doping area.
But even if introducing metal silicide, the contact electricity of PMOS transistor in the formed semiconductor devices of the prior art
Resistance is still larger, to affect the electric property of formed semiconductor structure.
Summary of the invention
Problems solved by the invention is to provide a kind of PMOS transistor and forming method thereof, inserts plug and source and drain to reduce
Contact resistance between doped region improves the performance of formed semiconductor structure.
To solve the above problems, the present invention provides a kind of forming method of PMOS transistor, comprising:
Substrate is provided；Gate structure is formed over the substrate；First is formed on the substrate of the gate structure two sides
Epitaxial layer and the second epitaxial layer on first epitaxial layer, second epitaxial layer are interior doped with modulation ion.
Optionally, the modulation ion is Ni or Al.
Optionally, the ratio of second epitaxy layer thickness and first epitaxy layer thickness is in 8:1 to 12:1 range
It is interior.
Optionally, the thickness of second epitaxial layer is in 1nm to 10nm range.
Optionally, the doping concentration of ion is modulated described in second epitaxial layer in 5E12atom/cm3It arrives
5E14atom/cm3In range.
Optionally, also doped with ion is repaired in second epitaxial layer, the reparation ion is Pt.
Optionally, the doping concentration of ion is repaired described in second epitaxial layer in 5E12atom/cm3It arrives
5E14atom/cm3In range.
Optionally, the step of forming first epitaxial layer and second epitaxial layer includes: in the gate structure two
The substrate uplink of side forms opening；By the first epitaxy technique into the opening filling semiconductor material, to form described
One epitaxial layer；Second epitaxial layer is formed on first epitaxial layer by the second epitaxy technique.
Optionally, doping in situ is carried out during second epitaxy technique.
Optionally, process gas employed in second epitaxial process includes the first impurity gas；The modulation
Ion is Ni, and first impurity gas is Ni (MeC (NtBu) 2) 2；The modulation ion is Al, first impurity gas
For (CH3) 2AlH.
Optionally, process gas employed in second epitaxial process further includes the second impurity gas, and described
Two impurity gas are MeCpPtMe3.
Optionally, second epitaxy technique and second epitaxy technique are carried out in same process cavity.
Optionally, it is formed after first epitaxial layer and second epitaxial layer, further includes: metal front layer is formed,
Second epitaxial layer described in the metal front layer covering part；It is made annealing treatment, outside make at least partly thickness described second
Prolong layer to react with the metal front layer to form articulamentum.
Correspondingly, the present invention also provides a kind of PMOS transistors, comprising:
Substrate；Gate structure, the gate structure are located on the substrate；First epitaxial layer, first epitaxial layer position
In on the substrate of the gate structure two sides；Second epitaxial layer, second epitaxial layer are located on first epitaxial layer, and
Doped with modulation ion in second epitaxial layer.
Optionally, the conciliation ion is nickel ion or aluminium ion.
Optionally, the ratio of second epitaxy layer thickness and first epitaxy layer thickness is in 8:1 to 12:1 range
It is interior.
Optionally, the thickness of second epitaxial layer is in 1nm to 10nm range.
Optionally, the doping concentration of ion is modulated described in second epitaxial layer in 5E12atom/cm3It arrives
5E14atom/cm3In range.
Optionally, also doped with ion is repaired in second epitaxial layer, the reparation ion is Pt.
Optionally, the doping concentration of ion is repaired described in second epitaxial layer in 5E12atom/cm3It arrives
5E14atom/cm3In range.
Compared with prior art, technical solution of the present invention has the advantage that
Second epitaxial layer and first epitaxial layer collectively form the source and drain doping area of formed PMOS transistor,
Second epitaxial layer is located on first epitaxial layer, therefore subsequent formed plug contacts phase with second epitaxial layer
Even.Due in second epitaxial layer have modulation ion, the modulation ion can be effectively reduced subsequent formed plug with
Schottky barrier between second epitaxial layer, it is brilliant so as to effectively reduce subsequent formed plug and formed PMOS
Contact resistance between Ti Guan source and drain doping area is conducive to the performance for improving formed semiconductor structure.
In optinal plan of the present invention, the reparation ion is Ni, also doped with repairing ion in second epitaxial layer,
The reparation ion is Pt；Therefore the addition for repairing ion, can effectively inhibit spike defect in second epitaxial layer
The formation of (Spike defect) advantageously reduces tip and puts so as to effectively improve the quality of subsequent formed articulamentum
Electrical phenomena odds is conducive to the improvement of formed semiconductor structure performance.
In optinal plan of the present invention, the doping concentration for repairing ion is in 5E12atom/cm3To 5E14atom/cm3Model
In enclosing.The doping concentration for repairing ion should not it is too big also should not be too small.The doping concentration for repairing ion is too small, then
The inhibitory effect for repairing ion pair spike defect may be will affect, may result in form spike in the second epitaxial layer
The appearance of defect increases the probability that point discharge phenomenon occurs in formed semiconductor structure, to be easy to influence to form half
The stability and performance of conductor structure；The doping concentration for repairing ion is too big, then may will affect formed PMOS crystal
The performance in pipe source and drain doping area and the performance of formed articulamentum, to be easy to cause formed semiconductor structure performance
It degenerates.
Detailed description of the invention
Fig. 1 to Fig. 4 is that cross-section structure corresponding to each step of one embodiment of PMOS transistor forming method of the present invention shows
It is intended to.
Specific embodiment
It can be seen from background technology that even if the prior art introduces metal silicide, the PMOS in formed semiconductor devices is brilliant
Body pipe has that contact resistance is excessive between plug and source and drain doping area.Now in conjunction with a kind of structure point of PMOS transistor
The reason of analysing its contact resistance problems of too:
As described in the background art, in order to reduce the contact between the plug increasingly to take effect and transistor source and drain doped region
Resistance, the region that can be contacted between plug and source and drain doping area under normal conditions form articulamentum.Under normal circumstances, it connects
Layer is usually silicon-titanium compound (Ti-Silicide).
For NMOS transistor, silicon-titanium compound can be effectively reduced the Xiao Te between plug and source and drain doping area material
Base potential barrier, so as to effectively reduce the contact resistance between plug and source and drain doping area；But with for PMOS transistor,
Schottky barrier height (the Sehottky barrier between plug and source and drain doping area can not be effectively reduced in silicon-titanium compound
Height, SBH), to affect the reduction of contact resistance between the two, affect the performance of formed semiconductor structure.
To solve the technical problem, the present invention provides a kind of PMOS transistor and forming method thereof, by described the
Two epitaxial layers doping modulation ion is subtracted with reducing the Schottky barrier between subsequent formed plug and second epitaxial layer
Small contact resistance between the two, and then improve the performance of formed semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to figs. 1 to Fig. 4, show corresponding to each step of one embodiment of PMOS transistor forming method of the present invention
The schematic diagram of the section structure.
With reference to Fig. 1, substrate 110 is provided.
The substrate 110 is for providing technological operation platform.
It should be noted that the substrate 110 includes the PMOS area for being used to form PMOS transistor in the present embodiment
102.In addition, as shown in Figure 1, the substrate 110 further includes the NMOS area 101 for being used to form NMOS transistor.Specifically,
The PMOS area 102 and the NMOS area 101 are disposed adjacent.But in other embodiments of the invention, the PMOS area
Non-conterminous it can also be arranged with the NMOS area.
In the present embodiment, the PMOS transistor is fin formula field effect transistor, so also being formed on the substrate 110
There is fin 120.Specifically, the substrate 110 of the PMOS area 102 and the NMOS area 101 has been respectively formed on the fin
120.In other embodiments of the invention, the PMOS transistor is also possible to planar transistor, and the substrate is planar substrate.
In the present embodiment, the material of the substrate 110 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
To be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium on insulator lining
Bottom, glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate
Material can choose the material for being suitable for process requirements or being easily integrated.
The fin 120 is for providing the channel of formed transistor.
In the present embodiment, it is all monocrystalline silicon that the material of the fin 120 is identical as the material of the substrate 110.This hair
In bright other embodiments, the material of the fin can also be different from the material of the substrate, can be selected from germanium, germanium silicon, carbon silicon
Or GaAs etc. is suitable for forming the material of fin.
Specifically, the substrate 110 and the fin 120 can be formed simultaneously.Form the substrate 110 and the fin
The step of portion 120 includes: offer initial substrate；Fin mask layer (not shown) is formed in the initial substrate surface；With
The fin mask layer is initial substrate described in mask etching, forms the substrate 110 and on the substrate 110
Fin 120.
In the present embodiment, the PMOS transistor further include: separation layer (does not indicate) in figure, be located at adjacent fin 120 it
Between the substrate 110 on.
The separation layer covers the partial sidewall of the fin 120, and is lower than the fin 120 at the top of the separation layer
Top.Separation layer of the separation layer as semiconductor structure can play electricity between adjacent devices and adjacent fin
The effect of isolation.The separation layer is located on the substrate 110 of the fin 120 exposing, and the height of the separation layer is low
In the height of the fin 120.
In the present embodiment, the material of the separation layer is silica.In other embodiments of the invention, the separation layer
Material can also be other insulating materials such as silicon nitride or silicon oxynitride.
In the present embodiment, the step of forming the separation layer includes: on the substrate 110 that the fin 120 exposes
It is formed spacer material layer (not indicated in figure), the spacer material layer covers the top of the fin 120；Described in grinding removal
Spacer material layer on 120 top of fin；The segment thickness of remaining spacer material layer is removed by way of returning and carving, and exposes institute
Top and the partial sidewall for stating fin 120, form the separation layer；The fin mask layer is removed, to expose the fin
120 top.
It continues to refer to figure 1, forms gate structure 130 on the substrate 110.
The gate structure 130 is used to control the conducting and truncation of formed semiconductor structure channel.
In the present embodiment, there is the fin 120, therefore the gate structure 130 is across described on the substrate 110
The surface of fin 120 and covering fin 120 atop part and partial sidewall.In addition, the substrate 110 includes described
NMOS area 101 and the PMOS area 102, so forming institute in the NMOS area 101 and the PMOS area 102
State gate structure 130.
In the present embodiment, the gate structure 130 is polysilicon gate construction.The gate structure 130 includes being located at institute
State the gate dielectric layer (not indicating in figure) on substrate 110 and the gate electrode on the gate dielectric layer (not indicating in figure).Its
In, the material of the gate dielectric layer is silica, and the material of the gate electrode is polysilicon.
In other embodiments of the invention, the gate structure can also be metal gate structure, including be located at the substrate
On gate dielectric layer, the work-function layer on the gate dielectric layer and the electrode layer in the work-function layer.Its
In, the material of the gate dielectric layer can be high K dielectric material；The material of the work-function layer is p-type work function material, function
Range of function is 5.1eV to 5.5eV, specifically can be selected from one or more of TiN, TaN, TaSiN and TiSiN；The electricity
The material of pole layer can be selected from one of W, Al, Cu, Ag, Au, Pt, Ni and Ti or a variety of.
Specifically, also there is the fin 120, so forming the grid knot on the substrate 110 in the present embodiment
The step of structure 130 includes: the layer of dielectric material to be formed positioned at 120 surface of fin；It is formed on the dielectric layer material layer
Electrode material layer；It is sequentially etched the electrode material layer and the layer of dielectric material, until exposing the part table of the fin 120
Face, and form the gate structure 130.
It should be noted that being formed after the gate structure 130, the forming method in the present embodiment further include:
Side wall (not indicating in figure) is formed on the side wall of the gate structure 130, to protect the gate structure, and is defined subsequent
The position in formed source and drain doping area.In the present embodiment, the side wall is single layer structure, and the material of the side wall is silicon nitride.
In other embodiments of the invention, the material of the side wall can also for silica, silicon carbide, carbonitride of silicium, carbon silicon oxynitride,
Silicon oxynitride, boron nitride or boron carbonitrides, the side wall may be laminated construction.
Referring to figs. 2 and 3, the first epitaxial layer 141 is formed on the substrate 110 of 130 two sides of gate structure and is located at
The second epitaxial layer 142 on first epitaxial layer 141, second epitaxial layer 142 are interior doped with modulation ion.
The source and drain that first epitaxial layer 141 and second epitaxial layer 142 are used to constitute formed PMOS transistor is mixed
Miscellaneous area 140.
Due to having modulation ion in second epitaxial layer 141, the modulation ion can be effectively reduced subsequent institute's shape
At the Schottky barrier between plug and second epitaxial layer 141, so as to reduce between subsequent plug and leakage doped region
Contact resistance, be conducive to the performance for improving formed semiconductor structure.
It should be noted that the substrate 110 includes the PMOS area 102 and the NMOS area in the present embodiment
101, so being formed after the side wall, formed before first epitaxial layer 141, the forming method further include: described
Mask layer (not indicating in figure) is formed in NMOS area 101.
The fin 120 and the gate structure 130 in the conformal covering NMOS area 101 of mask layer, with protection
Structure in the NMOS area 101 prevents the formation process pair of first epitaxial layer 141 and second epitaxial layer 142
Structure in the NMOS area 101 causes adverse effect.
Specifically, the material of the mask layer is silicon nitride, formed by way of atomic layer deposition.The present invention other
In embodiment, the material of the mask layer is also selected from fire sand, nitrogen silicon boride, nitrogen silicon oxide carbide and silicon oxynitride
It is one or more.The material of the mask layer is different from the material of the fin 120, the material of the mask layer with it is described
The material of separation layer is not also identical.Formed the mask layer can also for chemical vapor deposition or physical vapour deposition (PVD) etc. other
Film deposition technique.
In the present embodiment, the modulation ion is Ni.In other embodiments of the invention, the modulation ion can also be
Al.The doping of Ni or Al can reduce the Schottky barrier between second epitaxial layer 142 and the plug, be subtracted with reaching
The purpose of small contact resistance.
Specifically, modulating the doping concentration of ion described in second epitaxial layer 142 in 5E12atom/cm3It arrives
Within the scope of 5E14atom/cm, that is to say, that the doping concentration of Ni is in 5E12atom/cm in second epitaxial layer 1423It arrives
Within the scope of 5E14atom/cm.
It is described modulation ion doping concentration should not it is too high also should not be too low.If the doping concentration of the modulation ion
It is too low, then it may will affect Schottky barrier between subsequent the formed plug of the modulation ion pair and source and drain doping area 140 and drop
Low function is unfavorable for reducing the reduction of contact resistance between plug and source and drain doping area 140；The doping of the modulation ion
If concentration is too high, the probability that spike defect is formed in second epitaxial layer 142 may be will increase, it is also possible to will affect
The performance of first epitaxial layer 141 and the constituted source and drain doping area 140 of the second epitaxial layer 142, may will affect to be formed
The performance of PMOS transistor.
It should be noted that the height of 142 proportion of the second epitaxial layer, will affect constituted source and drain doping area
140 performance, to influence the performance between formed semiconductor structure.In the present embodiment, second epitaxial layer 140 is thick
The ratio of degree and 140 thickness of the first epitaxial layer is in 8:1 to 12:1 range.
The ratio of second epitaxial layer, 140 thickness and 140 thickness of the first epitaxial layer should not it is too high also should not be too
Greatly.
If the ratio of 140 thickness of the second epitaxial layer and 140 thickness of the first epitaxial layer is too high, the source
Second epitaxial layer, 140 accounting is too high in leakage doped region 140, and the modulation ion in second epitaxial layer 140 may be right
The source and drain doping area 140 causes metal ion pollution, to cause the performance degradation in the source and drain doping area 140；Described
If two epitaxial layers, 140 thickness is too low with the ratio of 140 thickness of the first epitaxial layer, 140 thickness of the second epitaxial layer
It is too small, the function of reducing to Schottky barrier between subsequent formed plug and source and drain doping area 140 may be will affect, it is unfavorable
In the reduction for reducing contact resistance between plug and source and drain doping area 140.
Specifically, the thickness of second epitaxial layer 142 is in 1nm to 10nm range in the present embodiment.
It should be noted that in the present embodiment, also doped with reparation ion in second epitaxial layer 142.The reparation
Ion is used to inhibit the formation of spike defect (Spike defect) in second epitaxial layer 142, so as to effectively improve
The quality of second epitaxial layer 142, advantageously reduces point discharge phenomenon odds, is conducive to formed semiconductor
The improvement of structural behaviour.Specifically, the reparation ion is Pt.
Specifically, repairing the doping concentration of ion described in second epitaxial layer 142 in 5E12atom/cm3It arrives
5E14atom/cm3In range.
The doping concentration for repairing ion should not it is too big also should not be too small.The doping concentration for repairing ion is too small,
The inhibitory effect for repairing ion pair spike defect may then be will affect, may result in be formed in the second epitaxial layer 142
The appearance of spike defect increases the probability that point discharge phenomenon occurs in formed semiconductor structure, to be easy to influence institute's shape
At the stability and performance of semiconductor structure；The doping concentration for repairing ion is too big, then may be to the source and drain doping
Area 140 causes metal ion pollution, may will affect the source and drain doping area 140 performance and subsequent formed articulamentum
Performance, to be easy to cause the degeneration of formed semiconductor structure performance.
Specifically, form first epitaxial layer 141 and the step of the second epitaxial layer 142 include: as shown in Fig. 2,
110 uplink of substrate in 130 two sides of gate structure forms opening 143；With reference to Fig. 3, by the first epitaxy technique to described
Filling semiconductor material in opening 143, to form first epitaxial layer 141；Through the second epitaxy technique outside described first
Prolong and forms second epitaxial layer 142 on layer 141.
The opening 143 is for providing technique for the formation of first epitaxial layer 141 and second epitaxial layer 142
Space.
The fin 120 is also formed on substrate 110 described in the present embodiment, so the step of forming the opening 143
It include: to etch the fin of 130 two sides of gate structure in the PMOS area 102 using the mask layer as exposure mask
120, form the opening 143 being located in the 130 two sides fin 120 of gate structure.
First epitaxy technique and second epitaxy technique are used for the filling semiconductor material into the opening 143,
To be respectively formed first epitaxial layer 141 and second epitaxial layer 142.
Specifically, the material of first epitaxial layer 141 is the Si or SiGe of p-type doping, wherein Doped ions can be
B, Ga or In.So the step of first epitaxy technique includes: to be filled out by way of epitaxial growth into the opening 143
Fill Si or SiGe；And doping (In-situ dope) in situ is carried out during first epitaxy technique.
It should be noted that first epitaxial layer 141 can also pass through ion implanting in other embodiments of the invention
Etc. other modes realize doping, so formed first epitaxial layer the step of include: by way of epitaxial growth to described
Si or SiGe is filled in opening, to form the first semiconductor layer；It is formed after first semiconductor layer, to described the first half
Conductor layer carries out ion implanting, to form first epitaxial layer.
The concentration of Doped ions and the specific process parameter of first epitaxy technique in first epitaxial layer 141
It is related to the requirement of the specific performance of formed PMOS transistor, i.e., it is related to the design of formed PMOS transistor.The present invention exists
This is repeated no more.
The material of second epitaxial layer 142 is the Si or SiGe of p-type doping, and in second epitaxial layer 142 also
Doped with the modulation ion, so the step of second epitaxy technique includes: by way of epitaxial growth described
The second epitaxial layer 142 is formed on one epitaxial layer 142；And doping in situ is carried out during second epitaxy technique.
In the present embodiment, the modulation ion is Ni, so process gas employed in second epitaxial process
Including the first impurity gas, first impurity gas is Ni (MeC (NtBu)2)2.It should be noted that other realities of the invention
It applies in example, the modulation ion can also be Al, so first impurity gas can also be (CH3)2AlH。
In addition, in second epitaxial process, used process gas further include: NH3And H2.So described
Process gas employed in two epitaxy techniques be include first impurity gas, NH3And H2Mixed gas.
Also doped with the reparation ion in second epitaxial layer 142, the reparation ion is Pt, so described the
Process gas employed in two epitaxial process further includes the second impurity gas, and second impurity gas is
MeCpPtMe3。
It should be noted that carrying out first epitaxy technique and described second in same process cavity in the present embodiment
Epitaxy technique provides process efficiency so as to effectively reduce processing step, but also can guarantee the source and drain doping area
The stability of 140 forming processes is conducive to the performance for improving formed PMOS transistor.
In addition, first epitaxy technique and second epitaxy technique are carried out continuously in the present embodiment.That is,
After carrying out first epitaxy technique, first impurity gas is passed through into process cavity immediately and described second is mixed
Miscellaneous gas starts to carry out the second epitaxy technique, so as to which first epitaxial layer 141 and second extension is effectively ensured
Connection between layer 142, guarantees the integrality in the source and drain doping area 140, is conducive to the improvement of device performance.So described
The process of first epitaxy technique and second epitaxy technique can regard an epitaxial process as, only in the extension
The later period of growth course is passed through first impurity gas and second impurity gas.
With reference to Fig. 4, in the present embodiment, formed after first epitaxial layer 141 and second epitaxial layer 142, it is described
Forming method further include: form metal front layer, the second epitaxial layer 142 described in the metal front layer covering part；It is moved back
Fire processing, reacts second epitaxial layer 142 of at least partly thickness to form articulamentum 160 with the metal front layer.
It should be noted that in the present embodiment, formed first epitaxial layer 141 and second epitaxial layer 142 it
Afterwards, it is formed before the metal front layer, the forming method further include: the gate structure 130 on the region NMOS 101
Third epitaxial layer (not indicating in figure) is formed in the fin 120 of two sides.
The third epitaxial layer is used to constitute the source and drain doping area of formed NMOS transistor.
The material of the third epitaxial layer is the Si or SiC of n-type doping, and wherein Doped ions can be P, As or Sb.Institute
It include: in the NMOS area 101 in the fin 120 of 130 two sides of gate structure the step of the third epitaxial layer to be formed
Form opening (not shown)；Si or SiC is filled into the opening by way of epitaxial growth；It is raw in the extension
In long process, doping in situ is carried out, to form the third epitaxial layer.
It should be noted that in the present embodiment, it is rear to be formed with the source and drain doping area 140 being initially formed in PMOS area 102
Source and drain doping area in NMOS area 101, for be illustrated.In this process sequence, as shown in figure 4, the area PMOS
It is simply formed with side wall on domain 101 on the side wall of the gate structure 130, and the gate structure in the NMOS area 101
It is not simply formed with side wall on 130 side wall, is also formed with mask layer, therefore the source and drain doping area in the PMOS area 102
Distance is shorter between 140 and the gate structure 130, closer to the channel region of 130 lower section of gate structure, thus favorably
In the mobility for improving formed channel carriers, be conducive to the inhibition of short-channel effect.
So being formed after the third epitaxial layer, interlayer dielectric layer 150 is formed in the source and drain doping area 140.
The interlayer dielectric layer 150 is for realizing the electricity between adjacent semiconductor constructs and between adjacent metal structures
Isolation.
In the present embodiment, the material of the interlayer dielectric layer 150 is silica.In other embodiments of the invention, the layer
Between the material of dielectric layer be also selected from other dielectric materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride.
Specifically, also having the fin 120 on the substrate 110, separation layer, institute are filled between adjacent fin 120
It states and is also formed with gate structure 130 on fin 120.So the interlayer dielectric layer 150 be filled in adjacent gate structure 130 it
Between, it is located in the substrate 110, the fin 120, the separation layer and the source and drain doping area 140, and the layer
Between dielectric layer 150 top be higher than the gate structure 130 top.
It should be noted that when using rear grid technique, the gate structure is pseudo- grid knot in other embodiments of the invention
Structure, so the step of forming the interlayer dielectric layer includes: to be formed in the NMOS area after source and drain doping area, described
First medium layer is formed on the substrate that pseudo- grid structure is exposed, the first medium layer exposes dummy gate structure；Remove the puppet
Grid structure forms gate openings in the first medium layer；Gate structure is formed in the gate openings；Described
Second dielectric layer is formed on one dielectric layer and the gate structure, the second dielectric layer and the first medium layer are used for shape
At the interlayer dielectric layer.
The first medium layer is electrically isolated for realizing between adjacent semiconductor constructs, is also used to define the grid knot
The size of structure and position；The second dielectric layer is for realizing the electric isolution between adjacent semiconductor constructs.
Since the first medium layer and the second dielectric layer are used to form the interlayer dielectric layer, so described
One dielectric layer and the material of the second dielectric layer are silica.In other embodiments of the invention, the first medium layer and
The second dielectric layer may be other same or different insulating materials.
The technical solution that gate structure is formed in the gate openings, can refer to previous embodiment inner grid structure
Technical solution, the present invention details are not described herein.
It is formed after the interlayer dielectric layer 150, the contact hole formed through the interlayer dielectric layer 150 (is not marked in figure
Show), the source and drain doping area on the area PMOS 102 and the NMOS area is exposed in the contact hole bottom.
The contact hole is for exposing the source and drain doping area, so that the formation for subsequent plug provides Process ba- sis.
In the present embodiment, source and drain doping area 140 in the PMOS area includes first epitaxial layer 141 and described
Second epitaxial layer 142, second epitaxial layer 142 are located on first epitaxial layer 141；So in the PMOS area
Expose second epitaxial layer 142 in contact hole bottom in interlayer dielectric layer 150.
It is formed after the contact hole, in the source and drain doping area of the NMOS area 101 and the PMOS area 102
It is formed metal front layer (not indicated in figure).
The metal front floor with some materials in the source and drain doping area for reacting to form articulamentum 160, to reduce
Contact resistance between subsequent formed plug and the source and drain doping area.Specifically, in the contact hole bottom and side wall
Form the metal front layer.In the present embodiment, the material of the precursor metal layer is Ti.Form the precursor metal layer
Specific technical solution is same as the prior art, and details are not described herein by the present invention.
It is formed after the metal front layer, is made annealing treatment, the annealing makes the metal front layer and portion
The source and drain doping area material of thickness is divided to react, to form articulamentum 160: being formed by NMOS for NMOS area 101
For transistor, the material of the articulamentum 160 is silicon-titanium compound, so as to which plug and source and drain doping area is effectively reduced
Schottky barrier between material, so as to effectively reduce the contact resistance between plug and source and drain doping area；And for
PMOS area 102 is formed by for PMOS transistor, the material of the articulamentum 160 be modulated doped with doses from
The doping of the silicon-titanium compound of son, the modulation ion can be effectively reduced Xiao between 140 material of plug and source and drain doping area
Special base potential barrier, to can also effectively reduce the contact resistance between plug and source and drain doping area.Therefore it is described modulate from
The doping of son, is conducive to the performance for improving formed semiconductor structure.
The specific technical solution of the annealing is same as the prior art, and details are not described herein by the present invention.
It is formed after the articulamentum 160, fills conductive material into the contact hole for being formed with the articulamentum 160, with
Form plug 170.
The plug 170 is electrically connected for realizing source and drain doping area and external circuit.The material of the plug 170 selects
From one of tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper or a variety of.
With reference to Fig. 4, the schematic diagram of the section structure of one embodiment of PMOS transistor of the present invention is shown.
The PMOS transistor includes:
Substrate 110；Gate structure 130, the gate structure 130 are located on the substrate 110；First epitaxial layer 141,
First epitaxial layer 141 is located on the substrate 110 of 130 two sides of gate structure；Second epitaxial layer 142, outside described second
Prolong layer 142 to be located on first epitaxial layer 141, and doped with modulation ion in second epitaxial layer 142.
The substrate 110 is for providing technological operation platform.
It should be noted that the substrate 110 includes the PMOS area for being used to form PMOS transistor in the present embodiment
102.In addition, as shown in Figure 1, the substrate 110 further includes the NMOS area 101 for being used to form NMOS transistor.Specifically,
The PMOS area 102 and the NMOS area 101 are disposed adjacent.But in other embodiments of the invention, the PMOS area
Non-conterminous it can also be arranged with the NMOS area.
In the present embodiment, the PMOS transistor is fin formula field effect transistor, so also being formed on the substrate 110
There is fin 120.Specifically, the substrate 110 of the PMOS area 102 and the NMOS area 101 has been respectively formed on the fin
120.In other embodiments of the invention, the PMOS transistor is also possible to planar transistor, and the substrate is planar substrate.
In the present embodiment, the material of the substrate 110 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
To be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium on insulator lining
Bottom, glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate
Material can choose the material for being suitable for process requirements or being easily integrated.
The fin 120 is for providing the channel of formed transistor.
In the present embodiment, it is all monocrystalline silicon that the material of the fin 120 is identical as the material of the substrate 110.This hair
In bright other embodiments, the material of the fin can also be different from the material of the substrate, can be selected from germanium, germanium silicon, carbon silicon
Or GaAs etc. is suitable for forming the material of fin.
In the present embodiment, the PMOS transistor further include: separation layer (does not indicate) in figure, be located at adjacent fin 120 it
Between the substrate 110 on.
The separation layer covers the partial sidewall of the fin 120, and is lower than the fin 120 at the top of the separation layer
Top.Separation layer of the separation layer as semiconductor structure can play electricity between adjacent devices and adjacent fin
The effect of isolation.The separation layer is located on the substrate 110 of the fin 120 exposing, and the height of the separation layer is low
In the height of the fin 120.
In the present embodiment, the material of the separation layer is silica.In other embodiments of the invention, the separation layer
Material can also be other insulating materials such as silicon nitride or silicon oxynitride.
The gate structure 130 is used to control the conducting and truncation of formed semiconductor structure channel.
In the present embodiment, there is the fin 120, therefore the gate structure 130 is across described on the substrate 110
The surface of fin 120 and covering fin 120 atop part and partial sidewall.In addition, the substrate 110 includes described
NMOS area 101 and the PMOS area 102, so forming institute in the NMOS area 101 and the PMOS area 102
State gate structure 130.
In the present embodiment, the gate structure 130 is polysilicon gate construction.The gate structure 130 includes being located at institute
State the gate dielectric layer (not indicating in figure) on substrate 110 and the gate electrode on the gate dielectric layer (not indicating in figure).Its
In, the material of the gate dielectric layer is silica, and the material of the gate electrode is polysilicon.
It should be noted that also there is side wall (not indicating in figure) on 130 side wall of gate structure in the present embodiment,
To protect the gate structure, and define the position in subsequent formed source and drain doping area.In the present embodiment, the side wall is single
Layer structure, the material of the side wall are silicon nitride.In other embodiments of the invention, the material of the side wall can also be oxidation
Silicon, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, the side wall may be lamination
Structure.
The source and drain that first epitaxial layer 141 and second epitaxial layer 142 are used to constitute formed PMOS transistor is mixed
Miscellaneous area 140.
Due to having modulation ion in second epitaxial layer 141, the modulation ion can be effectively reduced subsequent institute's shape
At the Schottky barrier between plug and second epitaxial layer 141, so as to reduce between subsequent plug and leakage doped region
Contact resistance, be conducive to the performance for improving formed semiconductor structure.
In the present embodiment, the modulation ion is Ni.In other embodiments of the invention, the modulation ion can also be
Al.The doping of Ni or Al can reduce the Schottky barrier between second epitaxial layer 142 and the plug, be subtracted with reaching
The purpose of small contact resistance.
Specifically, modulating the doping concentration of ion described in second epitaxial layer 142 in 5E12atom/cm3It arrives
5E14atom/cm3In range, that is to say, that the doping concentration of Ni is in 5E12atom/cm in second epitaxial layer 1423It arrives
5E14atom/cm3In range.
It is described modulation ion doping concentration should not it is too high also should not be too low.If the doping concentration of the modulation ion
It is too low, then it may will affect Schottky barrier between subsequent the formed plug of the modulation ion pair and source and drain doping area 140 and drop
Low function is unfavorable for reducing the reduction of contact resistance between plug and source and drain doping area 140；The doping of the modulation ion
If concentration is too high, the probability that spike defect is formed in second epitaxial layer 142 may be will increase, it is also possible to will affect
The performance of first epitaxial layer 141 and the constituted source and drain doping area 140 of the second epitaxial layer 142, may will affect to be formed
The performance of PMOS transistor.
It should be noted that the height of 142 proportion of the second epitaxial layer, will affect constituted source and drain doping area
140 performance, to influence the performance between formed semiconductor structure.In the present embodiment, second epitaxial layer 140 is thick
The ratio of degree and 140 thickness of the first epitaxial layer is in 8:1 to 12:1 range.
The ratio of second epitaxial layer, 140 thickness and 140 thickness of the first epitaxial layer should not it is too high also should not be too
Greatly.
If the ratio of 140 thickness of the second epitaxial layer and 140 thickness of the first epitaxial layer is too high, the source
Second epitaxial layer, 140 accounting is too high in leakage doped region 140, and the modulation ion in second epitaxial layer 140 may be right
The source and drain doping area 140 causes metal ion pollution, to cause the performance degradation in the source and drain doping area 140；Described
If two epitaxial layers, 140 thickness is too low with the ratio of 140 thickness of the first epitaxial layer, 140 thickness of the second epitaxial layer
It is too small, the function of reducing to Schottky barrier between subsequent formed plug and source and drain doping area 140 may be will affect, it is unfavorable
In the reduction for reducing contact resistance between plug and source and drain doping area 140.
Specifically, the thickness of second epitaxial layer 142 is in 1nm to 10nm range in the present embodiment.
It should be noted that in the present embodiment, also doped with reparation ion in second epitaxial layer 142.The reparation
Ion is used to inhibit the formation of spike defect (Spike defect) in second epitaxial layer 142, so as to effectively improve
The quality of second epitaxial layer 142, advantageously reduces point discharge phenomenon odds, is conducive to formed semiconductor
The improvement of structural behaviour.Specifically, the reparation ion is Pt.
Specifically, repairing the doping concentration of ion described in second epitaxial layer 142 in 5E12atom/cm3It arrives
5E14atom/cm3In range.
The doping concentration for repairing ion should not it is too big also should not be too small.The doping concentration for repairing ion is too small,
The inhibitory effect for repairing ion pair spike defect may then be will affect, may result in be formed in the second epitaxial layer 142
The appearance of spike defect increases the probability that point discharge phenomenon occurs in formed semiconductor structure, to be easy to influence institute's shape
At the stability and performance of semiconductor structure；The doping concentration for repairing ion is too big, then may be to the source and drain doping
Area 140 causes metal ion pollution, may will affect the source and drain doping area 140 performance and subsequent formed articulamentum
Performance, to be easy to cause the degeneration of formed semiconductor structure performance.
Specifically, the material of first epitaxial layer 141 is the Si or SiGe of p-type doping, wherein Doped ions can be
B, Ga or In.
The PMOS transistor further include:
Third epitaxial layer (does not indicate) in figure, and the third epitaxial layer is located at gate structure in the NMOS area 101
In the fin 120 of 130 two sides；Interlayer dielectric layer 150, the interlayer dielectric layer 150 are located at the source and drain doping area 140；Plug
170, the plug 170 is located in the source and drain doping area 140 and through the interlayer dielectric layer 150；Articulamentum 160, it is described
Articulamentum 160 is located at least between the plug 170 and the source and drain doping area 170.
The third epitaxial layer is used to constitute the source and drain doping area of formed NMOS transistor.The third epitaxial layer
Material is the Si or SiC of n-type doping, and wherein Doped ions can be P, As or Sb.
The interlayer dielectric layer 150 is for realizing the electricity between adjacent semiconductor constructs and between adjacent metal structures
Isolation.
In the present embodiment, the material of the interlayer dielectric layer 150 is silica.In other embodiments of the invention, the layer
Between the material of dielectric layer be also selected from other dielectric materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride.
Specifically, also having the fin 120 on the substrate 110, separation layer, institute are filled between adjacent fin 120
It states and is also formed with gate structure 130 on fin 120.So the interlayer dielectric layer 150 be filled in adjacent gate structure 130 it
Between, it is located in the substrate 110, the fin 120, the separation layer and the source and drain doping area 140, and the layer
Between dielectric layer 150 top be higher than the gate structure 130 top.
The plug 170 is electrically connected for realizing source and drain doping area and external circuit.The material of the plug 170 selects
From one of tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper or a variety of.
The articulamentum 160 is for reducing the plug 170 and source and drain in the PMOS area 102 and the region NMOS 101
Schottky barrier height between doped region material reduces contact resistance.
For NMOS area 101 is formed by NMOS transistor, the material of the articulamentum 160 is the conjunction of silicon titanizing
Object, so as to the Schottky barrier being effectively reduced between plug and source and drain doping area material, so as to effectively reduce plug
Contact resistance between source and drain doping area；And for PMOS area 102 is formed by PMOS transistor, the connection
The material of layer 160 is the silicon-titanium compound that ion is modulated doped with doses, and the doping of the modulation ion can effectively drop
Schottky barrier between 140 material of undershoot plug and source and drain doping area, to can also effectively reduce plug and source and drain doping area
Between contact resistance.Therefore the doping of the modulation ion, is conducive to the performance for improving formed semiconductor structure.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from
It in the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim
Subject to limited range.
Claims (20)
1. a kind of forming method of PMOS transistor characterized by comprising
Substrate is provided；
Gate structure is formed over the substrate；
The first epitaxial layer and the second extension on first epitaxial layer are formed on the substrate of the gate structure two sides
Layer, second epitaxial layer are interior doped with modulation ion.
2. forming method as described in claim 1, which is characterized in that the modulation ion is Ni or Al.
3. forming method as described in claim 1, which is characterized in that second epitaxy layer thickness and first epitaxial layer
The ratio of thickness is in 8:1 to 12:1 range.
4. forming method as claimed in claim 1 or 3, which is characterized in that the thickness of second epitaxial layer is in 1nm to 10nm
In range.
5. forming method as described in claim 1, which is characterized in that modulate the doping of ion described in second epitaxial layer
Concentration is in 5E12atom/cm3To 5E14atom/cm3In range.
6. forming method as claimed in claim 1 or 2, which is characterized in that in second epitaxial layer also doped with repair from
Son, the reparation ion are Pt.
7. forming method as claimed in claim 6, which is characterized in that repair the doping of ion described in second epitaxial layer
Concentration is in 5E12atom/cm3To 5E14atom/cm3In range.
8. forming method as described in claim 1, which is characterized in that form first epitaxial layer and second epitaxial layer
The step of include:
Opening is formed on the substrate of the gate structure two sides；
By the first epitaxy technique into the opening filling semiconductor material, to form first epitaxial layer；
Second epitaxial layer is formed on first epitaxial layer by the second epitaxy technique.
9. forming method as claimed in claim 8, which is characterized in that carried out during second epitaxy technique in situ
Doping.
10. forming method as claimed in claim 8 or 9, which is characterized in that work employed in second epitaxial process
Skill gas includes the first impurity gas；
The modulation ion is Ni, and first impurity gas is Ni (MeC (NtBu)2)2；
The modulation ion is Al, and first impurity gas is (CH3)2AlH。
11. forming method as claimed in claim 10, which is characterized in that technique employed in second epitaxial process
Gas further includes the second impurity gas, and second impurity gas is MeCpPtMe3。
12. forming method as claimed in claim 8, which is characterized in that carry out the first extension work in same process cavity
Skill and second epitaxy technique.
13. forming method as described in claim 1, which is characterized in that form first epitaxial layer and second extension
After layer, further includes:
Form metal front layer, the second epitaxial layer described in the metal front layer covering part；
It is made annealing treatment, connect at least partly second epitaxial layer of thickness to be formed with metal front layer reaction
Layer.
14. a kind of PMOS transistor characterized by comprising
Substrate；
Gate structure, the gate structure are located on the substrate；
First epitaxial layer, first epitaxial layer are located on the substrate of the gate structure two sides；
Second epitaxial layer, second epitaxial layer are located on first epitaxial layer, and doped with tune in second epitaxial layer
Ion processed.
15. PMOS transistor as claimed in claim 14, which is characterized in that the conciliation ion is nickel ion or aluminium ion.
16. PMOS transistor as claimed in claim 14, which is characterized in that outside second epitaxy layer thickness and described first
Prolong the ratio of thickness degree in 8:1 to 12:1 range.
17. the PMOS transistor as described in claim 14 or 16, which is characterized in that the thickness of second epitaxial layer is in 1nm
Into 10nm.
18. PMOS transistor as claimed in claim 14, which is characterized in that modulation ion described in second epitaxial layer
Doping concentration is in 5E12atom/cm3To 5E14atom/cm3In range.
19. PMOS transistor as claimed in claim 14, which is characterized in that in second epitaxial layer also doped with repair from
Son, the reparation ion are Pt.
20. PMOS transistor as claimed in claim 19, which is characterized in that reparation ion described in second epitaxial layer
Doping concentration is in 5E12atom/cm3To 5E14atom/cm3In range.
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