CN102487049B - Semiconductor substrate and preparation method thereof - Google Patents
Semiconductor substrate and preparation method thereof Download PDFInfo
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- CN102487049B CN102487049B CN201010577093.6A CN201010577093A CN102487049B CN 102487049 B CN102487049 B CN 102487049B CN 201010577093 A CN201010577093 A CN 201010577093A CN 102487049 B CN102487049 B CN 102487049B
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- insulating protective
- perforate
- protective layer
- metal level
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor substrate and a preparation method thereof. The semiconductor substrate comprises a substrate, a first insulating protective layer, a metal layer, a second insulating protective layer, and a solder ball. More particularly, an electrical contact pad is arranged on the surface of the substrate; the first insulating protective layer is arranged on the substrate and enables the electrical contact pad to be exposed; the metal layer is arranged on the exposed electrical contact pad; the second insulating protective layer is arranged on the first insulating protective layer and enables a portion of the metal layer to be exposed; and the solder ball is arranged on the exposed metal layer. Because the second insulating protective layer is covered on a portion of the metal layer, when a temperature test is carried out on the semiconductor substrate, problems that the solder ball drops off or fractures and the like can be solved. Furthermore, the invention also provides a preparation method of the semiconductor substrate.
Description
Technical field
The present invention relates to a kind of semiconductor substrate and method for making thereof, especially design a kind of semiconductor substrate and method for making thereof of avoiding soldered ball to break.
Background technology
Flourish along with electronic industry, electronic product also marches toward multi-functional, high performance R&D direction gradually.The design of semiconductor chip at present includes routing type (wire bonding) and chip upside-down mounting type (flip chip) etc., so that chip is connect and to be placed on base plate for packaging, and gold thread or conductive projection are set between this chip and base plate for packaging, this chip is electrically connected on this base plate for packaging.
And, height multi-functional for reaching made kinetic power, long service life, the electrical stability of chip is quite important.Can be with reference to the 6th, 107,180 or 6,111, No. 321 United States Patent (USP)s of US, or refer to Fig. 1, be the generalized section of existing semiconductor element.
As shown in Figure 1; existing semiconductor element 1 comprises: have electric contact mat 100 wafer (Wafer) 10, be located on this wafer 10 and expose this electric contact mat 100 insulating protective layer 11, be located at the end bump metal layer (Under BumpMetal, UBM) 12 on this electric contact mat 100 exposing and be located at the soldered ball 16 on this UBM layer 12.
But, due to this wafer 10 and thermal coefficient of expansion (the Coefficient ofThermal Expansion of this UBM layer 12, CTE) do not mate, therefore in the time that this semiconductor element 1 carries out temperature test, easily cause this UBM layer 12 to be peeled off, make this soldered ball 16 problems such as (crack) that comes off or break, so that when follow-up while carrying out flip-chip (flip chip) manufacture method, this electric contact mat 100 cannot effectively be connected on base plate for packaging, and then cannot effectively produce electric connection, cause the rate of finished products of product to reduce.
Referring again to Fig. 2 A to 2B, it is the generalized section of the method for making of another existing semiconductor element 1 '.As shown in Figure 2 A, first there is the upper formation resistance layer 15 of wafer 10 ' of electric contact mat 100 ' one, and utilize the mode of exposure imaging to make this resistance layer 15 form perforate 150, to expose outside this electric contact mat 100 '.Then, form on the electric contact mat 100 ' of scolder (solder paste) 160 in this perforate 150 in (printing) mode of brushing.Finally, as shown in Figure 2 B, remove this resistance layer 15, then through reflow welding (reflow) manufacture method, make this scolder 160 form soldered ball 16 '.
But, because this scolder 160 forms in brushing mode, thereby be not easy to fill completely in this perforate 150, so that when after reflow welding manufacture method, this soldered ball 16 ' easily produces emptying aperture (void) phenomenon, and easily because of electron transfer (electro migration, EM) cause this soldered ball 16 ' to produce partial melting (local melting), make when follow-up while carrying out flip-chip (flipchip) manufacture method, this electric contact mat 100 ' cannot effectively be connected on base plate for packaging, and then cannot effectively produce electric connection, thereby the rate of finished products of product reduces.
Therefore, how to avoid the variety of problems of above-mentioned prior art, real is current target to be solved.
Summary of the invention
For overcoming the many disadvantages of prior art, the invention provides a kind of semiconductor substrate, comprising: substrate, has electric contact mat on its surface; The first insulating protective layer, is located on this substrate and electric contact mat, and this first insulating protective layer has the first perforate, makes this electric contact mat expose in this first perforate; Metal level, is located on the electric contact mat in this first perforate, and extends on the part surface of this first insulating protective layer; The second insulating protective layer, is located on this first insulating protective layer and metal level, and this second insulating protective layer has the second perforate, makes this metal level expose in this second perforate, and this second insulating protective layer covers the metal level being positioned on this first insulating protective layer; And soldered ball, be located on the metal level in this second perforate.
In above-mentioned semiconductor substrate, this metal level is end bump metal layer (Under BumpMetal), and the material that forms this end bump metal layer is as titanium/copper/nickel or titanium/nickel vanadium/copper.
In aforesaid semiconductor substrate, the material that forms this soldered ball is tin.
In aforesaid semiconductor substrate, this soldered ball has copper material.
The present invention further discloses a kind of method for making of semiconductor substrate, comprise: the substrate that has electric contact mat on a surface and cover the first insulating protective layer of this electric contact mat is provided, wherein, this first insulating protective layer has the first perforate, to make this electric contact mat expose in this first perforate; In this first perforate and form metal level on electric contact mat, and this metal level extends on the part surface of this first insulating protective layer; On this first insulating protective layer and metal level, form the second insulating protective layer, this second insulating protective layer has the second perforate, to make this metal level expose in this second perforate, and this second insulating protective layer covers the metal level being positioned on this first insulating protective layer; And form on the metal level of the soldered ball with copper material in this second perforate.
In above-mentioned method for making, the manufacture method of this soldered ball, comprising: form on the metal level of copper layer on this second insulating protective layer and in this second perforate; Form resistance layer on this copper layer, and this resistance layer has the 3rd perforate, to expose outside the copper layer on this metal level; Form on the copper layer of scolder in the 3rd perforate and in the 3rd perforate; Remove this resistance layer and under copper layer; And merge this scolder and under copper layer, the soldered ball that there is copper material to form this.
In above-mentioned method for making, can electroplate and form this scolder.
In above-mentioned semiconductor substrate and method for making thereof, this substrate can be wafer.
As from the foregoing; semiconductor substrate of the present invention and method for making thereof, the surrounding that is covered in this metal level by this second insulating protective layer is upper, than prior art; in the time that semiconductor substrate of the present invention carries out temperature test, can avoid the problems such as this soldered ball comes off or breaks.
Moreover, form this scolder by plating mode, can make this scolder be filled in completely in this perforate, than prior art, the present invention can avoid this soldered ball to produce emptying aperture phenomenon, and can avoid this soldered ball to cause being electrically connected bad situation because of partial melting.
Brief description of the drawings
Fig. 1 is the partial cutaway schematic of existing semiconductor element.
The generalized section of the method for making that Fig. 2 A to 2B is another existing semiconductor element.
The generalized section of the method for making that Fig. 3 A to 3H is semiconductor substrate of the present invention.
Main element symbol description
1,1 ' semiconductor element
10,10 ' wafer
100,100 ', 200 electric contact mats
11 insulating protective layers
12 end bump metal layers
15,25 resistance layers
150 perforates
16,16 ', 26 soldered balls
160,260 scolders
2 semiconductor substrates
20 substrates
21 first insulating protective layers
210 first perforates
22 metal levels
23 second insulating protective layers
230 second perforates
24 bronze medal layers
250 the 3rd perforates.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Must understand, appended graphic the illustrated structure of this specification, ratio, size etc., all contents in order to coordinate specification to disclose only, for those skilled in the art's understanding and reading, not in order to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", the term of " " and D score etc., also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, changing under technology contents, when being also considered as the enforceable category of the present invention without essence.
Refer to Fig. 3 A to 3H, disclosed the method for making of semiconductor substrate 2 of the present invention.
As shown in Figure 3A; the substrate 20 that has electric contact mat 200 on one surface and cover the first insulating protective layer 21 of this electric contact mat 200 is provided; wherein, this first insulating protective layer 21 has the first perforate 210, to make this electric contact mat 200 expose in this first perforate 210.In the present embodiment, this substrate 20 can be the wafer of chip upside-down mounting type.
As shown in Figure 3 B, form on the hole wall of metal level 22 in this first perforate 210 and on electric contact mat 200, and this metal level 22 extends on the part surface of this first insulating protective layer 21.
In the present embodiment, this metal level 22 is end bump metal layer (Under Bump Metal, UBM), and the material foot that forms this end bump metal layer for example: titanium/copper/nickel or titanium/nickel vanadium/copper.Moreover, can pass through the mode that sputter (sputter) or plating (plating) coordinate exposure imaging, carry out patterning manufacture method, to form this metal level 22.
As shown in Figure 3 C; form the second insulating protective layer 23 on this first insulating protective layer 21 and metal level 22; this second insulating protective layer 23 has the second perforate 230; to make this metal level 22 expose in this second perforate 230, and this second insulating protective layer 23 covers the metal level 22 being positioned on this first insulating protective layer 21.
As shown in Figure 3 D, in sputter (sputter) mode, form on the metal level 22 of copper layer 24 on this second insulating protective layer 23 and in this second perforate 230.
As shown in Fig. 3 E, form resistance layer 25 on this copper layer 24, and this resistance layer 25 can be photoresistance, therefore by the mode of exposure imaging, make this resistance layer 25 form the 3rd perforate 250 of patterning, to expose outside the copper layer 24 on this metal level 22.As shown in the figure, aforesaid the first perforate 210, the second perforate 230 and the 3rd perforate 250 arrange in correspondence with each other.
As shown in Fig. 3 F, in the 3rd perforate 250, in the second perforate 230 and on copper layer 24, form scolder (solder paste) 260 with plating mode.In the present embodiment, the material that forms this scolder 260 is tin.
As shown in Fig. 3 G, remove this photoresist layer 25, then etching removes the copper layer 24 under this photoresist layer 25, to retain the copper layer 24 under this scolder 260.
As shown in Fig. 3 H, through reflow welding (reflow) manufacture method, make this scolder 260 form soldered ball 26, the copper layer 24 under this scolder 260 can fuse in this soldered ball 26 simultaneously, to form on the metal level 22 of the soldered ball 26 with copper material in this second perforate 230.In follow-up manufacture method, this soldered ball 26 is electrically connected on base plate for packaging in flip-chip (flip chip) mode.
The present invention is covered on this metal level 22 by this second insulating protective layer 23; make this second insulating protective layer 23 can prevent that this metal level 22 from peeling off; therefore in the time that semiconductor substrate 2 carries out temperature test, this soldered ball 26 problems such as (crack) that can not come off or break.Therefore, when follow-up, while carrying out flip-chip manufacture method, this electric contact mat 200 can effectively be electrically connected on base plate for packaging, thus the rate of finished products of improving product.
Moreover, form this scolder 260 by plating mode, can make this scolder 260 be filled in completely in the 3rd perforate 250 and the second perforate 230, when after reflow welding manufacture method, fuse in this soldered ball 26 by copper layer 24 again, not only can avoid this soldered ball 26 to produce emptying aperture (void) phenomenon, and can avoid this soldered ball 26 to cause being electrically connected bad situation because of partial melting.Therefore, when follow-up, while carrying out flip-chip manufacture method, this electric contact mat 200 can effectively be electrically connected on base plate for packaging, thus the rate of finished products of improving product.
The present invention further provides a kind of semiconductor substrate 2, comprising: on surface, have electric contact mat 200 substrate 20, be located on this substrate 20 and expose this electric contact mat 200 the first insulating protective layer 21, be located at metal level 22 on this electric contact mat 200, be located at the second insulating protective layer 23 on this first insulating protective layer 21 and metal level 22 and be located at the soldered ball with copper material 26 on this metal level 22.
Described substrate 20 can be wafer.
The first described insulating protective layer 21 has the first perforate 210, to make this electric contact mat 200 expose in this first perforate 210.
Described metal level 22 is located on the electric contact mat 200 in this first perforate 210, and extends on the part surface of this first insulating protective layer 21.Moreover this metal level 22 is end bump metal layer (UBM), and the material that forms this UBM can be titanium/copper/nickel or titanium/nickel vanadium/copper.
The second described insulating protective layer 23 has the second perforate 230, and to make this metal level 22 expose in this second perforate 230, and this second insulating protective layer 23 covers the metal level 22 being positioned on this first insulating protective layer 21.
The described soldered ball with copper material 26 is located on the metal level 22 in this second perforate 230, and the material that forms this soldered ball 26 is tin.
In sum, semiconductor substrate of the present invention and method for making thereof, the surrounding that is covered in this metal level by this second insulating protective layer is upper, with in the time that semiconductor substrate carries out temperature test, this soldered ball problem such as can not come off or break.
Moreover, form scolder by plating mode, can make this scolder be filled in completely in this perforate, when after reflow welding manufacture method, not only can avoid this soldered ball to produce emptying aperture phenomenon, and can avoid this soldered ball to cause being electrically connected bad situation because of partial melting.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.Therefore the scope of the present invention, should be as listed in claims scope.
Claims (9)
1. a semiconductor substrate, comprising:
Substrate, has electric contact mat on its surface;
The first insulating protective layer, is located on this substrate and electric contact mat, and this first insulating protective layer has the first perforate, to make this electric contact mat expose in this first perforate;
Metal level, is located on the electric contact mat in this first perforate, and extends on the part surface of this first insulating protective layer;
The second insulating protective layer, be located on this first insulating protective layer and metal level, this second insulating protective layer has the second perforate, and to make this metal level expose in this second perforate, and this second insulating protective layer covers the metal level being positioned on this first insulating protective layer; And
Soldered ball, be located on the metal level in this second perforate, and this soldered ball comprises: be located at the copper layer on this metal level and be located at the scolder on this copper layer, and through reflow welding manufacture method, make this scolder form this soldered ball, this copper layer fuses in this soldered ball simultaneously, makes this soldered ball have copper material.
2. semiconductor substrate according to claim 1, wherein, this substrate is wafer.
3. semiconductor substrate according to claim 1, wherein, this metal level is end bump metal layer.
4. semiconductor substrate according to claim 3, wherein, the material that forms this end bump metal layer is titanium/copper/nickel or titanium/nickel vanadium/copper.
5. semiconductor substrate according to claim 1, wherein, the material that forms this soldered ball is tin.
6. a method for making for semiconductor substrate, comprising:
The substrate that has electric contact mat on one surface and cover the first insulating protective layer of this electric contact mat is provided, and wherein, this first insulating protective layer has the first perforate, to make this electric contact mat expose in this first perforate;
In this first perforate and form metal level on electric contact mat, and this metal level extends on the part surface of this first insulating protective layer;
On this first insulating protective layer and metal level, form the second insulating protective layer, this second insulating protective layer has the second perforate, to make this metal level expose in this second perforate, and this second insulating protective layer covers the metal level being positioned on this first insulating protective layer;
On metal level on this second insulating protective layer and in this second perforate, form copper layer;
On this copper layer, form scolder; And
Through reflow welding manufacture method, merge simultaneously this scolder and under copper layer, to form on the metal level of the soldered ball with copper material in this second perforate.
7. the method for making of semiconductor substrate according to claim 6, wherein, this substrate is wafer.
8. the method for making of semiconductor substrate according to claim 6, wherein, the manufacture method of this soldered ball, comprising:
Forming before this scolder, on this copper layer, form resistance layer, and this resistance layer has the 3rd perforate, to expose outside the copper layer on this metal level;
On copper layer in the 3rd perforate and in the 3rd perforate, form this scolder;
Forming after this scolder, remove this resistance layer and under copper layer; And
Merge this scolder and under copper layer.
9. the method for making of semiconductor substrate according to claim 8, wherein, forms this scolder to electroplate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010577093.6A CN102487049B (en) | 2010-12-02 | 2010-12-02 | Semiconductor substrate and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010577093.6A CN102487049B (en) | 2010-12-02 | 2010-12-02 | Semiconductor substrate and preparation method thereof |
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| CN102487049A CN102487049A (en) | 2012-06-06 |
| CN102487049B true CN102487049B (en) | 2014-10-15 |
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| CN201010577093.6A Active CN102487049B (en) | 2010-12-02 | 2010-12-02 | Semiconductor substrate and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103508412B (en) * | 2013-09-11 | 2015-11-25 | 上海丽恒光微电子科技有限公司 | The method for packing of pressure sensor chip and pressure sensor |
| US9824989B2 (en) | 2014-01-17 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package and methods of forming thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1186009A (en) * | 1996-10-17 | 1998-07-01 | 松下电器产业株式会社 | Soft solder and electronic component using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1166481C (en) * | 2002-06-28 | 2004-09-15 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
| JP4327656B2 (en) * | 2004-05-20 | 2009-09-09 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| US8039960B2 (en) * | 2007-09-21 | 2011-10-18 | Stats Chippac, Ltd. | Solder bump with inner core pillar in semiconductor package |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1186009A (en) * | 1996-10-17 | 1998-07-01 | 松下电器产业株式会社 | Soft solder and electronic component using the same |
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| CN102487049A (en) | 2012-06-06 |
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