1336516 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板表面結構及其製法，尤指 一種特別適用於覆晶封裝之封裝基板表面結構及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniaturizati〇n)的封裝要求，提供 10多數主被動元件及線路連接之電路板，亦逐漸由雙層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (mtedayer connection)擴大電路板上可利用的佈線面積而 配合尚電子岔度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 15生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠、以及植球等封裝製程，又一般半導體封裝是將 半導體晶片背面黏貼於封裝基板頂面進行打線接合（灰心 bonding) ’或者將半導體晶片之主動面以覆晶接合（FHp chip) 20方式與封裝基板接合，再於基板之背面植以錫球以供與另 一電路板進行電性連接。 上述覆晶接合封裝方式中，當半導體封裝基板表面結 構線寬及線距縮短時，因接點G 〇 i n t)強度亦隨著接點尺寸而 1336516 縮小’所以接點強度不足以承受晶片與基板間的剪應力 (shear stress)，而產生接點斷裂的現象將更加顯著。 習知的封裝基板表面結構及製法，請參考圖1。如圖i 所示’其包括一封裝基板11，其表面上具有一線路層14, 5該線路層14具有複數連接墊141。該封裝基板上覆蓋一防焊 層15，該防谭層15具有複數開孔150以顯露出該些連接墊 141。於该防焊層15表面先後形成一導電層丨^及一阻層（未 圖示）’於β玄阻層利用曝光顯影方式形成大於該些防焊層i 5 開孔150之複數阻層開孔，再藉由該導電層丨6以電鍍方式在 10該些阻層開孔内形成複數T型金屬柱17,該些金屬柱17的材 料可為銅、錫或鎳/金等等。接著，以電鍍形成焊接材料後 移除該阻層及其下之導電層，或者於移除該阻層及其下之 導電層後再於該些金屬柱17表面經由印刷形成焊接材料， 後、.’二迴焊形成複數預焊料凸塊丨9 (presold^ 。最後以 15該些預焊料凸塊19與一晶片進行接合。 上述製程所得之封裝基板表面結構雖可提供與晶片接 s以達到電性連接的目的，然而，因該T型金屬柱17與預焊 料凸塊19之界面17〇係為平面式的接觸，—旦受應力形成裂 紋則該裂紋極易延著該τ型金屬柱17與預焊料凸塊19之界 20面傳播，另外，此種結構中該導電層16處因結構強度較弱 亦容易受應力而發生裂紋，前述兩者皆會使整體之電性連 接結構產生劣化，亦即接點斷裂的現象。在半導體封裝基 板表面結構線寬及線距之縮短之趨勢下，丁型金屬柱Η與預 焊料凸塊19或連接塾141與了型金屬柱17的接觸面積勢變 6 山 6516 j此時叉應力產生接點斷裂的現象更加顯荖. 性連接結構失效。 更力..肩者，會造成電 【發明内容】 鑒於上述缺點，本發明之主要目的係在提供一 ^的表面結構’藉由改變該電性連接結構之幾何形狀，、 卩1紋傳播’強化基板電性連接結構的可 月匕改善覆晶封裂時’因連接晶片與基板的焊料凸塊^口: 應力而發生接點斷裂的現象。 又剪 15 201336516 IX. Description of the Invention: [Technical Field] The present invention relates to a surface structure of a package substrate and a method for fabricating the same, and more particularly to a surface structure of a package substrate which is particularly suitable for flip chip packaging and a method for fabricating the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization requirements of semiconductor packages, 10 circuit boards with a large number of active and passive components and line connections are also gradually evolved from double-layer boards into multi-layer boards. In a limited space, the mtedayer connection is used to expand the available wiring area on the board to meet the requirements of the integrated circuit. In the general semiconductor device process, the wafer carrier manufacturer 15 first produces a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. Then, the wafer carrier boards are transferred to a semiconductor package manufacturer for packaging processes such as crystallization, wire bonding, encapsulation, and ball implantation. In general, the semiconductor package is adhered to the top surface of the package substrate for wire bonding (grease bonding) 'Or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding (FH chip) 20, and then solder balls are implanted on the back surface of the substrate for electrical connection with another circuit board. In the above flip chip bonding package method, when the line width and the line pitch of the surface of the semiconductor package substrate are shortened, the strength of the contact G 〇int) is also reduced by 1336516 with the contact size. Therefore, the contact strength is insufficient to withstand the wafer and the substrate. The shear stress between the joints will be more pronounced. Please refer to Figure 1 for the surface structure and manufacturing method of the conventional package substrate. As shown in FIG. i, it includes a package substrate 11 having a wiring layer 14 on its surface, and the wiring layer 14 has a plurality of connection pads 141. The package substrate is covered with a solder resist layer 15 having a plurality of openings 150 to expose the connection pads 141. Forming a conductive layer 及 and a resist layer (not shown) on the surface of the solder resist layer 15 to form a plurality of resistive layers greater than the opening 150 of the solder resist layer i 5 by exposure development The holes, and the conductive layer 丨6 are electroplated to form a plurality of T-shaped metal pillars 17 in the openings of the barrier layers. The material of the metal pillars 17 may be copper, tin or nickel/gold or the like. Then, after forming the solder material by electroplating, the resist layer and the underlying conductive layer are removed, or after removing the resist layer and the underlying conductive layer, the solder material is formed on the surface of the metal pillars 17 by printing, 'Two reflow forming a plurality of pre-solder bumps 丨 9 (presold ^. Finally, 15 pre-solder bumps 19 are bonded to a wafer. The surface structure of the package substrate obtained by the above process can be provided to the wafer to achieve The purpose of the electrical connection, however, because the interface 17 of the T-shaped metal pillar 17 and the pre-solder bump 19 is in a planar contact, the crack is highly prone to the τ-shaped metal pillar when the crack is formed by stress. 17 and the surface of the pre-solder bump 19 spread 20, in addition, in this structure, the conductive layer 16 is susceptible to stress and crack due to weak structural strength, both of which will result in the overall electrical connection structure. Deterioration, that is, the phenomenon of joint breakage. In the tendency of the line width and the line pitch of the surface of the semiconductor package substrate, the contact between the butt-shaped metal pillars and the pre-solder bumps 19 or the joints 141 and the metal pillars 17 Area change 6 mountain 6516 j At this time, the phenomenon of joint breakage caused by the fork stress is more obvious. The joint structure fails. More force: shoulder, it will cause electricity. [Inventive content] In view of the above disadvantages, the main object of the present invention is to provide a surface The structure 'by changing the geometry of the electrical connection structure, the 卩1 pattern propagation' can enhance the electrical connection structure of the substrate to improve the flip chip cracking when the solder bump is connected to the wafer and the substrate: stress The phenomenon of joint breakage occurs. Cut 15 20
製本^之另—目的係在提供一種封裝基板表面結構的 狀、二2焊料凸塊形成能抑制裂紋傳播之幾何形 :曰加、.1。合強度，此製法復因其減少製程步驟，其所 、、4無須於金屬柱與連接塾間配置導電層，這兩者皆处 減少其結構處發生斷裂，而使產品良率上升。 I ，達成上述目的，本發明提供_種封裝基板表面結 路屏：：括一基板’其表面上具有一線路層’其中該線 一曰/、複數連接塾，並於該基板S面及該線路層間具有 電曰 防焊層’其係覆蓋該基板上，並對應該些連 接塾具有複數開孔’·以及一金屬柱，其係配置於該些料 層開孔及對應之該連接墊上，該金屬柱延伸出該開孔外、 南於該防焊層表面並形成簟狀頭部，且該蕈狀頭部以下的 部份該金屬柱亦顯露出來。 上述之結構中’該些防焊層開孔之尺寸係小於或等於 該些連接墊。 7 1336516 本發明更提供-種封裝基板表面結構之製法，其步驟 包括·提供一基板，盆* T-- B , — /、表面具有一導電層，該導電層上覆 盍有一第一阻層’且該第-阻層形成有開口區以顯露部份 該導電層，並於該開口區内所顯露之該導電層上電锻形成 5有一線路層，該線路層具有複數連接墊；形成-第二靜 於該基板表面，且該第二阻層形成有複數開孔以顯露該此 連接塾；以電鑛方式於該些開孔各形成一金屬柱，該全屬 柱係高於該第二阻層表面，且延伸出該開孔外並形成輩狀 頭部；移除該基板表面之該第二阻層、該第一阻層及被該 10第-阻層覆蓋之該導電層；形成一防焊層於該基板表面； 以及移除部份該防焊層厚度至顯露出該金屬柱之孽狀頭 部，及顯露出該蕈狀頭部以下的部份該金屬柱，以完成本 發明之封裝基板表面結構。 i述之f法巾開狀尺寸係小於或等於 15 該些連接墊。 ' 本發明中，此種在表面具有簟狀之金屬柱的封裝基 板，乃改變金屬柱與預焊料凸塊所構成之電性連接結構二 幾何形狀，從防焊層所顯露出該金屬柱之蕈狀頭部，可抑 制直線裂紋的發生，且該葦狀頭部及其以下的部份該金屬 20柱，提供與預焊料凸塊間更大的接合表面積，及省除電性 連接墊與金屬柱間結構較弱的導電層，而在可靠度測試 日ΤΓ，接點之機械強度、抗疲勞（fatigue)性質於 .可以有效抑制接點斷裂，因此本發明可提高基板電二 ^^0516 結構的可靠度 面結構。 適用於縮短線寬及線距 之覆晶封裝基板表 【實施方式】 : 乂下係#由特定的具體實施例說明本發明之實施方 熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 10 可基於不同觀點與應用，在不_本發明之精神下進行各 種修飾與變更。 6月參考圖2A〜2G，此為製作本實施例封裝基板表面結 構之製作流程示意圖。 首先，如圖2A所示，提供一基板21，該基板21表面具 有一導電層22。該導電層22之材料可選用自銅、錫、錄、 15鉻、鈦、銅/鉻合金、以及錫/鉛合金所組成群組其中之一者， 本實施例使用銅作為此導電層22之材料。 於該導電層22上，經由曝光顯影的方式，形成具有開 口區230之第一阻層23 ,再於第一阻層23之開口區23〇内， 經由電鍍方式形成一線路層24，該線路層24具有複數連接 2〇墊241。再次利用曝光顯影的方式，形成具複數開孔250之 第二阻層25。該第一阻層23及第二阻層25可為液態光阻或 乾膜此外弟一阻層25之開孔250對應於該連接墊241，且 • 本實施例中該開孔250略小於該連接墊241。 9 1336516 接著，如圖2B所示，於該開孔250内利用電鑛方式形成 一金屬柱27,該金屬柱27之材料可選用自錫、銀、銅、 金鉍銻、鋅、鎳、錘、鎂、銦以及鎵之其中 者，本a鈿例使用銅作為該金屬柱27之材料。在電鍍形 5成該金屬柱27時，當金屬柱27超出第二阻層25之表面高度 後，電鑛便會等向性㈣r〇pic)往周圍方向發展，因此該金 屬柱27可產生有蕈狀頭部270。 然後，見圖2C所示，將第二阻層25、第一阻層23及其 所覆盍之部分該導電層22移除，以顯露出該金屬柱27、該 10 連接墊241以及該基板21表面。 接著，如圖2D所示，為了保護該基板2丨上的線路層24 及連接墊241免於物理或化學性的傷害’全面性的形成一防 焊層28，一般使用綠漆或黑漆作為此防焊層28。本實施例 使用綠漆作為此防焊層28。 15 再如圖2E所示，移除部份該防焊層28，使該防焊層28 減少厚度直到顯露該金屬柱27之蕈狀頭部27〇，及該蕈狀頭 部270以下的部份該金屬柱271，以得到本發明之封裝基板 表面結構。 之後’見圖2F所示，在該金屬柱27所顯露出之蕈狀頭 20部270及其下的部份該金屬柱271表面形成一金屬接著層 29。此金屬接著層29的材料，較佳可選自錫、銀、鎳、金、 鉻/鈦合金、錄/金合金、錦/纪合金、與錄/纪/金合金所組成 • 群組其中之一者，本實施例則使用鎳/鈀合金，形成該金屬 接著層之方式係可為電鑛、物理沉積及化學沉積之其中一 丄⑽516 者”中D亥物理"L積方式係為錢鑛及蒸鐘之其中一者， 該化學沉積係為無電電鍍。 最後’為形成作為封裝基板與晶片兩者間之電性連接 點，如圖2G所示，在該金屬柱27蕈狀頭部27〇及其下的部份 5該金屬柱271表面之金屬接著層29上，經由印刷及回焊製 程，形成-預焊料凸塊3〇。該預焊料凸塊3〇之材料較佳可 、自銅錫錯、鎳、金、銀、鉍及其組成群組合 金其中之一者，本實施例使用之材料為錫。 此外’亦可於先前圖2E所述之製程完成後，直接於該 U)金屬柱27蕈狀頭部27〇及其下的部份該金屬柱271上，經由 印刷f回焊製程，形成一預焊料凸塊30，而不額外形成金 屬接著層29。因此，前述之預焊料凸塊30及金屬接著層29 可依製程需要選擇性形成之。 本1明復提供一封裝基板表面結構。如圖2e所示，此 15封裝基板表面結構包含一基板21，其表面上具有一線路層 24 ’ °玄線路層24具有複數連接墊241，該基板21表 面及該線 路^間具有—導電層22。此外，該基板21及該線路層24 上復1有防焊層28 ’該防焊層28具有複數開孔對應該些 連接墊24卜又具有一金屬柱27，其係配置於該些防焊層27 20開孔及對應之该連接塾24 j上，該金屬柱η延伸出該開孔 外同於5玄防焊層27表面並形成簟狀頭部27〇，且該蕈狀頭 部2 7 〇以下的部份該金屬柱2 71亦顯露出來。 ' 本發明所揭示在表面上具有蕈狀頭部金屬柱之封裝基 板的結構及製程’乃改變金屬柱與預焊料凸塊所構成之電 11 丄J丄ϋ 丄J丄ϋ 10 15The other is to provide a shape of the surface structure of the package substrate, and the formation of the two solder bumps can suppress the propagation of cracks: 曰, . In combination, the method is designed to reduce the number of process steps, and the 4 does not need to be provided with a conductive layer between the metal post and the connecting crucible, both of which reduce the fracture at the structure and increase the yield of the product. I, in order to achieve the above object, the present invention provides a substrate substrate surface junction screen: a substrate having a circuit layer on its surface, wherein the line has a 曰/, a plurality of connections 塾, and the substrate S surface and the Between the circuit layers, there is an electric solder resist layer 'which covers the substrate, and has a plurality of openings · and a metal post, which are disposed on the opening of the material layer and the corresponding connection pad, The metal post extends outside the opening, south of the surface of the solder resist layer and forms a dome-shaped head, and the metal pillar is also exposed in a portion below the braided head. In the above structure, the size of the solder mask opening is less than or equal to the connecting pads. 7 1336516 The present invention further provides a method for fabricating a surface structure of a package substrate, the method comprising: providing a substrate, the basin * T-- B, / /, having a conductive layer on the surface, the conductive layer being covered with a first resist layer And the first resist layer is formed with an open area to expose a portion of the conductive layer, and the conductive layer is exposed on the conductive layer in the open area to form a circuit layer having a plurality of connection pads; the circuit layer has a plurality of connection pads; a second static layer is formed on the surface of the substrate, and the second resistive layer is formed with a plurality of openings to expose the connecting ridge; and a metal pillar is formed on each of the openings by electro-mineralization, and the whole column is higher than the first a second resist layer surface extending outside the opening and forming a generation head; removing the second resist layer on the surface of the substrate, the first resist layer and the conductive layer covered by the 10th resist layer; Forming a solder mask on the surface of the substrate; and removing a portion of the solder resist layer to reveal a dome-shaped head of the metal pillar, and exposing a portion of the metal pillar below the braided head to complete The surface structure of the package substrate of the present invention. The open size of the f-measured towel is less than or equal to 15 of the connecting pads. In the present invention, the package substrate having the metal pillars having a meandering shape on the surface changes the geometrical structure of the electrical connection structure formed by the metal pillars and the pre-solder bumps, and the metal pillars are exposed from the solder resist layer. The braided head can suppress the occurrence of linear cracks, and the beak head and the lower portion of the metal 20 pillars provide a larger joint surface area with the pre-solder bumps, and the electrical connection pad and metal are omitted. The conductive layer with weaker structure between the columns, and the mechanical strength and fatigue resistance of the joint can effectively suppress the joint breakage during the reliability test day, so the invention can improve the structure of the substrate electric ^^0516 Reliability surface structure. A flip-chip package substrate suitable for shortening the line width and the line pitch. [Embodiment] The present invention is described by a specific embodiment. Those skilled in the art can easily understand the contents disclosed in the present specification. Other advantages and benefits of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Referring to Figures 2A to 2G in June, this is a schematic diagram of the fabrication process for fabricating the surface structure of the package substrate of this embodiment. First, as shown in Fig. 2A, a substrate 21 having a conductive layer 22 on its surface is provided. The material of the conductive layer 22 can be selected from the group consisting of copper, tin, Li, 15 chrome, titanium, copper/chromium alloy, and tin/lead alloy. In this embodiment, copper is used as the conductive layer 22. material. On the conductive layer 22, a first resist layer 23 having an open region 230 is formed through exposure and development, and a wiring layer 24 is formed by electroplating in the open region 23A of the first resist layer 23. Layer 24 has a plurality of connection pads 2 241. The second resist layer 25 having a plurality of openings 250 is formed by exposure development again. The first resistive layer 23 and the second resistive layer 25 may be liquid photoresist or dry film, and the opening 250 of the resist layer 25 corresponds to the connecting pad 241, and the opening 250 is slightly smaller than this in the embodiment. Connect the pad 241. 9 1336516 Next, as shown in FIG. 2B, a metal pillar 27 is formed by using the electric ore method in the opening 250. The material of the metal pillar 27 can be selected from tin, silver, copper, gold, zinc, nickel, and hammer. Among the magnesium, indium and gallium, this example uses copper as the material of the metal pillar 27. When the metal pillar 27 is plated into the metal pillar 27, when the metal pillar 27 exceeds the surface height of the second resist layer 25, the electric ore is developed in the direction of the isotropic (four) r〇pic), so that the metal pillar 27 can be produced. Braided head 270. Then, as shown in FIG. 2C, the second resist layer 25, the first resist layer 23 and a portion thereof covered by the conductive layer 22 are removed to expose the metal pillar 27, the 10 connection pad 241, and the substrate. 21 surface. Next, as shown in FIG. 2D, in order to protect the circuit layer 24 and the connection pad 241 on the substrate 2 from physical or chemical damage, a solder mask 28 is formed comprehensively, and green paint or black paint is generally used. This solder mask layer 28. This embodiment uses green paint as the solder resist layer 28. 15 as shown in FIG. 2E, a portion of the solder resist layer 28 is removed to reduce the thickness of the solder resist layer 28 until the crown portion 27 of the metal post 27 is exposed, and the portion below the braided head 270 The metal post 271 is dispensed to obtain the surface structure of the package substrate of the present invention. Thereafter, as shown in Fig. 2F, a metal back layer 29 is formed on the surface of the metal post 271 on the beak head portion 20 270 and the portion below the metal post 27. The material of the metal back layer 29 is preferably selected from the group consisting of tin, silver, nickel, gold, chromium/titanium alloy, recording/gold alloy, brocade alloy, and recording/time/gold alloy. In one embodiment, the nickel/palladium alloy is used, and the metal bonding layer can be formed into one of the electric ore, physical deposition and chemical deposition (10) 516. One of the ore and the steaming tube, the chemical deposition system is electroless plating. Finally, in order to form an electrical connection point between the package substrate and the wafer, as shown in FIG. 2G, the metal column 27 is in the shape of a head. 27〇 and the lower portion 5 of the metal post 271 on the metal backing layer 29, through the printing and reflow process, forming a pre-solder bump 3〇. The pre-solder bump 3〇 material is preferably The material used in this embodiment is tin from one of the alloys of copper tin, nickel, gold, silver, antimony and its constituent alloys. Further, 'after the process described in the previous FIG. 2E is completed, directly U) the metal post 27 has a braided head 27〇 and a portion below the metal post 271, which is printed back via f The process forms a pre-solder bump 30 without additionally forming a metal back layer 29. Therefore, the foregoing pre-solder bump 30 and metal back layer 29 can be selectively formed according to the process requirements. As shown in FIG. 2e, the surface structure of the 15 package substrate comprises a substrate 21 having a circuit layer 24' on the surface thereof. The circuit layer 24 has a plurality of connection pads 241, and the surface of the substrate 21 and the circuit have - a conductive layer 22. In addition, the substrate 21 and the circuit layer 24 have a solder resist layer 28'. The solder resist layer 28 has a plurality of openings corresponding to the connection pads 24 and has a metal post 27. The metal pillars η extend out of the opening and are the same as the surface of the 5 Xuan solder resist 27 and form a braided head 27〇, and the corresponding soldering layer 27 20 is opened and corresponding to the connecting port 24 j The metal pillar 2 71 is also exposed in the portion below the 蕈-shaped head portion. The structure and process of the package substrate having the 头部-shaped head metal column on the surface of the present invention change the metal pillar and the pre-solder. The electric power of the bumps is 11 丄J丄ϋ 丄J丄ϋ 10 15
連接墊141 Τ型金屬柱17 第一阻層23 連接墊241 金屬柱27 結構的幾何形狀，從防焊層所顯露出該金屬柱之葦 的部μΓΓ直線裂紋的發生，且該蕈狀頭部及其以下 積，H、，柱，提供與預焊料凸塊間更大的接合表面 在可〜除電性連接墊與金屬㈣結構較弱的導電層，而 於i==Μ ’㈣之機㈣度 '抗疲勞（fatlgue)性質優 可以有效抑制接點斷裂，因此本發明可提高 性連接結構的可靠度，適料縮短線寬及線距之覆 曰曰封裝基板表面結構。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1係習知封裝基板表面結構之示意圖。 圖2Α〜2G圖係本發明—較佳實施例封裝基板表面結構之 製作流程示意圖。 【主要元件符號說明】 基板11 線路層14 防焊層15 導電層16 Τ型金屬柱表面170預焊料凸塊19 基板21 導電層22 開口區230 線路層24 第二阻層25 開孔250 12 1336516 蕈狀頭部270 部份金屬柱271 金屬接著層29 預焊料凸塊30 防焊層28Connection pad 141 Τ-type metal post 17 first resistive layer 23 connection pad 241 metal post 27 structural geometry, the occurrence of a straight line crack in the ridge of the metal post from the solder resist layer, and the 蕈-shaped head And the following product, H, column, provides a larger bonding surface with the pre-solder bumps in the conductive layer of the de-energized connection pad and the metal (four) structure, and the machine of i==Μ '(4) (4) The degree of 'fatigue' is excellent in suppressing joint breakage. Therefore, the present invention can improve the reliability of the joint structure, and can shorten the line width and the line spacing of the surface structure of the package substrate. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the surface structure of a conventional package substrate. 2 to 2G are schematic views showing the manufacturing process of the surface structure of the package substrate of the present invention. [Main component symbol description] Substrate 11 Circuit layer 14 Solder mask 15 Conductive layer 16 金属-type metal post surface 170 Pre-solder bump 19 Substrate 21 Conductive layer 22 Open region 230 Circuit layer 24 Second resist layer 25 Opening 250 12 1336516 Braided head 270 part metal post 271 metal backing layer 29 pre-solder bump 30 solder resist layer 28
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