CN102355254B - Clockless State Regression Domino Logic Gates and Related Integrated Circuits and Estimation Methods - Google Patents

Abstract

A clockless state regression domino logic gate and related integrated circuit and estimation method. The clockless state regression domino logic gate is responsive to a plurality of input nodes including at least one state regression node. A domino circuit presets a preset node to a first state. When the preset node is pulled to a second state, the domino circuit is switched to a latching state and switches the state of an output node. When a reset node is pulled to the first state, the domino circuit resets back to the preset state and switches the output node back to its preset value. An evaluation circuit pulls the preset node to the second state when the input node is in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in the latched state. After an evaluation event, the reset circuit pulls the reset node to the first state if the reset condition is satisfied and the input node is no longer in the evaluation state.

Description

Without clock-state regression domino logic gate and relevant integrated circuit and evaluation method

Technical field

The present invention relates to logical circuit, and be particularly related to self-Reset Status and return dominoes formula gates (self-resetting return to state (RTS) domino logic gate), its operation need not rely on clock signal, and returns (RTS) signal for response state.

Background technology

The setting of logical circuit on integrated circuit (IC), the quick actuating logic computing of conventionally take is object, therefore, has multiple possibility layout.In many examples, clock signal is directed to the circuit of logical operation is provided is difficulty and be difficult for realizes.Comprise static state and dynamic logic gate and circuit, most logical circuit all needs according to an input clock operation.Static CMOS (Complementary Metal Oxide Semiconductor) gate is with quite low energy operation, but there is considerable input capacitance, and wherein signal is that complementary P type device and N-type device wrestled each other and obtain, and therefore, the operation of static CMOS (Complementary Metal Oxide Semiconductor) gate is quite slow.The staticizer that dominoes formula circuit (Domino) is more relative is quick, but almost always will be controlled by an input clock signal.

This technical field needs a kind of logical circuit or gate, can be under the state without clock signal in faster and effective mode, carries out logical operation.

Summary of the invention

Formed a kind of without clock-state regression domino logic gate according to one embodiment of the present invention, there is a plurality of nodes, a dominoes circuit, an estimation circuit, an enable circuit and a reset circuit.Above-mentioned node designs separately at one first state and one second state and switches.Above-mentioned each leisure of input node is set as after above-mentioned the first state, returns operation return above-mentioned the second state according to state.Dominoes circuit has a preset condition and a latch mode.When this dominoes circuit is this preset condition, this dominoes circuit is set a preset node and an activation node to above-mentioned the first state and is set this output node and one first replacement node is above-mentioned the second state.When this preset node transition is to above-mentioned the second state, this dominoes circuit switches to this latch mode, with this output node of transition to above-mentioned the first state and this activation node of transition to above-mentioned the second state.When this first replacement node transition is above-mentioned the first state, this dominoes circuit this preset condition of resetting back.When above-mentioned input node be at least one estimated state any time, this preset node of this estimation circuit transition is to this second state, on the contrary this estimation circuit does not affect the level of this default node.When this activation node is above-mentioned the second state, this second replacement node of this enable circuit transition is to above-mentioned the first state, otherwise this enable circuit does not affect the level of this second replacement node.When above-mentioned input node be not in above-mentioned at least one estimated state any time, this reset circuit is coupled in above-mentioned first and second replacement node together.When above-mentioned input node be in above-mentioned at least one estimated state any time, this reset circuit is isolated from each other above-mentioned first and second replacement node.This estimation circuit and this reset circuit can be two configuration designs each other.Described state regression technique can be realized by returning logic ' 0 ' design, for responding, returns logic ' 0 ' input signal, or, can realize by returning logic ' 1 ' design, for responding, return logic ' 1 ' input signal.

The integrated circuit of realizing according to one embodiment of the present invention, comprising one first logic and without clock-state regression domino logic gate.This first logic is supplied a plurality of states and is returned signal.Described state returns signal and switches on separately one first state and one second state.About each state, return signal, after being set as the first state, it is the second state that this first logic can return each state recurrence signal of operating and setting according to state.Without clock-state regression domino logic gate, comprise a default node, an activation node, an output node and one first and one second replacement node, switch on separately first and second state.Without clock-state regression domino logic gate, also comprise a dominoes circuit, an estimation circuit, an enable circuit and a reset circuit.

The logical operation evaluation method of realizing according to one embodiment of the present invention.Described method comprises that receiving a plurality of states returns signal.About each state, return signal, can after being set to one first state, according to state, return operation and return one second state.The method also comprises that supply has a dominoes circuit of a preset condition and a latch mode.This dominoes circuit, when this preset condition, can be set a preset node and an activation node is one first state, and sets an output node and a replacement node is one second state.When this preset node is by transition during to this second state, this dominoes circuit switches to this latch mode.When this replacement node transition is to this first state, this preset condition is returned in this dominoes circuit transition, with this output node of transition to this first state and this activation node of transition to this second state.The method also comprises that the above-mentioned state of estimation returns input signal, and wherein, when described state returns input signal in any of at least one estimated state, this preset node of transition, to this second state, makes this dominoes circuit switch to its latch mode.The method is still included in this activation node this replacement node of transition when this second state and described state return signal no longer for any of above-mentioned at least one estimated state and take and reset this dominoes circuit as this preset condition for this first state.

According to one embodiment of the present invention formed, without clock-state regression domino logic gate, there are a plurality of nodes, a dominoes circuit, an estimation circuit, an enable circuit and a reset circuit.Each node switches on one first state and one second state.At least one input node is that a state returns node, can, after being set as this first state, returning operation return this second state according to state.This dominoes circuit has a preset condition and a latch mode.When this dominoes circuit is this preset condition, this dominoes circuit set a preset node and an activation node to this first state and set an output node and one first replacement node to this second state.When this preset node is pulled to this second state, this dominoes circuit switches to this latch mode, this output node is pulled to this first state and this activation node is pulled to this second state.When this first replacement node is pulled to this first state, this dominoes circuit this preset condition of resetting back.When above-mentioned input node is during in any of at least one estimated state, this estimation circuit is pulled to this second state by this preset node; Otherwise this estimation circuit is not interfered the level of this preset node.When this activation node is during in this second state, this enable circuit draws high this second replacement node to this first state.When above-mentioned input node is not during in above-mentioned at least one estimated state any, this reset circuit is coupled in above-mentioned first and second replacement node together; Otherwise this reset circuit can be isolated above-mentioned first and second replacement node mutually.

Above-mentioned state regression technique can be embodied as the framework that returns logic ' 0 ', in order to respond, returns logic ' 0 ' input signal.Or above-mentioned state regression technique can be embodied as the framework that returns logic ' 1 ', in order to respond, return logic ' 1 ' input signal.Estimation circuit and reset circuit can be used for jointly carrying out logical operation or the function of any demand, and without the two configuration designs that are defined as each other.In one embodiment, the Set Status of the corresponding above-mentioned input node of estimation circuit, this reset circuit couples the input node that is less than above-mentioned input node sum.About offering the input node of this reset circuit, each is all that state returns node.

As for the integrated circuit according to one embodiment of the present invention made, comprising the first logic and without clock-state regression domino logic gate.This first logic provides at least one state to return signal, switches on one first state and one second state.About each state, return signal, this first logic can return operation according to this state it setting is back to the second state after described state returns signal sets to be the first state.Described have a preset node, an activation node, an output node and one first and one second replacement node without clock-state regression domino logic gate; Each comfortable above-mentioned first and second state of above-mentioned node switches.Describedly without clock-state regression domino logic gate, also comprise a dominoes circuit, an estimation circuit, an enable circuit and a reset circuit.

As for according to the method for formed a kind of estimation one logical operation of one embodiment of the present invention, comprising following steps.First, receive a plurality of input signals, each comfortable first state of described input signal and the second state switch.In addition, provide a dominoes circuit, operate in a preset condition and a latch mode.Under this preset condition, this dominoes circuit is set a preset node and activation node to one first state and is set an output node and replacement node to one second state.When this preset node is pulled to this second state, this dominoes circuit switches to this latch mode, and this output node of transition is to this first state and move this activation node to this second state.When this replacement node is moved this first state to, this dominoes circuit this preset condition of resetting back.Described method also comprises: estimate that above-mentioned state returns input signal, when above-mentioned state returns any one at least one estimated state of input signal, move this preset node to second state, with this dominoes circuit of transition to this latch mode.Described method also comprises: in this activation node, when this second state and above-mentioned state return input signal for any one in above-mentioned at least one estimated state, move this replacement node to this first state with this dominoes circuit of resetting.Above-mentioned input signal comprises that at least one state returns signal, returns operation return as this second state after being set as the first state according to state.

According to one embodiment of the present invention, realize one without clock-state regression domino logic gate, comprise a dominoes circuit and an input circuit.This is used for responding a plurality of input logic signals without clock-state regression domino logic gate, and wherein each input logic signal is designed to switch in first and second logic state.Dominoes circuit comprises three inverters, has one first and one second device of one first conductive form and a device with one second conductive form.The first inverter is coupled between above-mentioned input and output node.The second inverter is coupled between above-mentioned output node and an activation node.The 3rd inverter couples one first replacement node with input.The above-mentioned first device of the first conductive form has that a control end couples above-mentioned output node, one first current terminal couples about one first power supply potential node of above-mentioned the first logic state and one second current terminal and couples above-mentioned preset node.The first device of the second conducted state has one first current terminal and couples that a second source current potential, a control end about this second logic state couples this activation node and one second current terminal couples this first replacement node.This second device of the first conductive form has one first current terminal and couples output and one second current terminal that this first power supply potential node, a control end couple the 3rd inverter and couple this preset node.When above-mentioned input logic signal is an estimated state, this input circuit is moved this preset node to this second logic state.When this estimated state is left in above-mentioned input signal transition, this input circuit is temporarily moved this first replacement node to this first logic state.

In one embodiment, this input circuit comprises an estimation circuit, an enable circuit and a reset circuit.When above-mentioned input logic signal is an estimated state, this estimation circuit is moved this preset node to this second logic state.When this activation node is this second logic state, this enable circuit is moved one second replacement node to this first logic state.When this input logic signal is not this estimated state, this reset circuit couples this first replacement node to this second replacement node.In one embodiment, this first power supply potential node has one on the occasion of power supply potential, and this second source potential nodes has a reference potential, and this first conductive form is the design of semiconductor P type, and this second conductive form is the design of semiconductor N type.In another embodiment, this first power supply potential node has a reference potential, and this second source potential nodes has one on the occasion of power supply potential, and this first conducting form is the design of semiconductor N type, and this second conducting form is the design of semiconductor P type.Above-mentioned input signal can comprise that at least one state returns signal, and according to different designs, described input signal can return logic ' 1 ' or return logic ' 0 '.

An integrated circuit of realizing according to one embodiment of the present invention comprises that at least one is without clock-state regression domino logic gate and one first circuit.This first circuit is supplied at least one state and is returned signal, and according to state recurrence operation, it is set as to the second state after above-mentioned state returns signal sets to be the first state.Can above-mentioned similar fashion design without clock-state regression domino logic gate.

A kind of method of estimating a plurality of input logic signals.Described input logic signal comprises that at least one state returns input signal.The method comprises that setting a preset node is one first logic state, and this first logic state is the anti-phase of one second logic state.Described method also comprises that anti-phase this preset node is to determine the logic state of an output node, anti-phase this output node is to determine the logic state of an activation node, when this activation node is this first logic state, transition one replacement node is to this second logic state, anti-phase this replacement node is to determine a logic state of an anti-phase replacement node, when this anti-phase replacement node is this second logic state, this preset node of transition is to this first logic state, when forming an estimated state, force above-mentioned input signal this preset node to this second logic state, being supplied in transition is at least one state recurrence signal that after the first logic state, the second logic state is returned in transition, and be that this second logic state and above-mentioned input signal force this replacement node for this first logic state when recurrence operates this estimated state of escape according to state at this activation node.In addition,, when replacement node is forced this first logic state, this second logic state is returned in the transition of anti-phase replacement node, then, this preset node of transition is this first logic state, then comes, and the above-mentioned output node of transition returns this second logic state, then, this activation node of transition is got back to this first logic state, and then, this replacement node of transition returns this second logic state, and then, this anti-phase replacement node of transition returns this first logic state.

Accompanying drawing explanation

Below narration will contribute to understand advantage of the present invention, feature and improve content, and the diagram of cooperation comprises:

Fig. 1 is the calcspar of a simplification, describes a chip or an integrated circuit, comprising what realize according to one embodiment of the present invention, one without clock status, returns dominoes circuit;

Fig. 2 is a calcspar, diagram according to one embodiment of the present invention, realize one without clock-state regression domino logic gate, can be used to realize Fig. 1 and return one or more without clock-state regression domino logic gate in dominoes circuit without clock status;

Fig. 3 is a block schematic diagram, and what diagram realized without a kind of recurrence logic ' 0 ' execution mode of clock-state regression domino logic gate according to Fig. 2 one returns logic ' 0 ' domino logic gate without clock;

Fig. 4 is the schematic diagram of recurrence logic ' 0 ' dominoes circuit, and diagram Fig. 3 returns a kind of execution mode of logic ' 0 ' dominoes circuit;

Fig. 5 is a sequential chart, and diagram Fig. 3 returns the operation of logic ' 0 ' domino logic gate without clock, wherein adopts a kind of execution mode of recurrence logic ' 0 ' the dominoes circuit of Fig. 4;

Fig. 6 is a block schematic diagram, and diagram one returns logic ' 0 ' domino logic gate without clock, in order to realize a logic sum gate, M input signal I1...IM is carried out to logic OR computing;

Fig. 7 is a simplification calcspar, a string repeatedly gate design of diagram, wherein have three be coupled in together without clock status, return gate, in order to realize a logical operation;

Fig. 8 is a block schematic diagram, diagram according to another embodiment of the present invention, realize one without clock-state regression domino logic gate, in order to realize diversified logical operation;

Fig. 9 is a block schematic diagram, and diagram one returns logic ' 0 ' domino logic gate without clock, in order to realize a logic and operation, returns logic ' 0 ' input signal I1...IM carry out logic and operation to M;

Figure 10 is a block schematic diagram, and another returns logic ' 0 ' domino logic gate without clock diagram, and in order to realize a logical AND gate, to M persistent state, ' 0 ' input signal I1...IM makes logic and operation, comprising the reset circuit of a simplification;

Figure 11 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate without clock, and its a kind of recurrence logic ' 1 ' execution mode without clock-state regression domino logic gate according to Fig. 2 is realized;

Figure 12 is for returning logic ' 1 ' dominoes circuit one schematic diagrames, and diagram Figure 11 returns a kind of execution mode of logic ' 1 ' dominoes circuit;

Figure 13 is a sequential chart, in order to illustrate that Figure 11 returns the operation of logic ' 1 ' domino logic gate without clock, wherein adopts Figure 12 to return a kind of execution mode of logic ' 1 ' dominoes circuit;

Figure 14 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate without clock, wherein realizes a logic sum gate, returns logic ' 1 ' input signal I1...IM do logic OR computing to M;

Figure 15 is a block schematic diagram without clock recurrence logic ' 1 ' domino logic gate 1500, made according to another kind of execution mode, in order to carry out a diversified logical operation;

Figure 16 is a block schematic diagram without clock recurrence logic ' 1 ' domino logic gate, in order to realize a logical AND gate, returns logic ' 1 ' input signal I1...IM make logic and operation to M; And

Figure 17 returns a block schematic diagram of logic ' 1 ' domino logic gate for another without clock, in order to realize a logical AND gate, M recurrence logic ' 1 ' entered to signal I1...IM and carry out logic and operation, comprising the reset circuit that has a simplification.

[main element symbol description]

101～integrated circuit; 103～state returns logic;

104～non-state returns logic;

105～without clock status, return dominoes circuit;

107～logical circuit;

200～without clock-state regression domino logic gate;

201～state regression estimation circuit; 202～preset node;

203～state returns reset circuit; 204～state returns activation node;

205～state returns dominoes circuit; 206～replacement node;

207～state returns enable circuit; 208～output node;

210～the second replacement nodes;

300～without clock, return logic ' 0 ' domino logic gate;

301～recurrence logic ' 0 ' estimation circuit; 302～precharged node;

303～recurrence logic ' 0 ' reset circuit;

304～recurrence logic ' 0 ' activation node;

305～recurrence logic ' 0 ' dominoes circuit; 306～replacement node;

308～output node; 310～the second replacement nodes;

400～recurrence logic ' 0 ' dominoes circuit; 401～inverter;

402～half holding circuits; 403,405～inverter;

The reactions of the second status signal RESET of the two configuration designs of 501～sign;

600～without clock, return logic ' 0 ' domino logic gate;

601～recurrence logic ' 0 ' estimation circuit;

603～recurrence logic ' 0 ' reset circuit;

The design of 700～associating gate;

701,703,705～without clock-state regression domino logic gate;

800～without clock, return logic ' 0 ' domino logic gate;

801～recurrence logic ' 0 ' estimation circuit; 802～via node;

803～recurrence logic ' 0 ' reset circuit;

900～without clock, return logic ' 0 ' domino logic gate;

901～recurrence logic ' 0 ' estimation circuit;

903～recurrence logic ' 0 ' reset circuit;

1000～without clock, return logic ' 0 ' domino logic gate;

1003～recurrence logic ' 0 ' reset circuit;

1100～without clock, return logic ' 1 ' domino logic gate;

1101～recurrence logic ' 1 ' estimation circuit; 1102～pre-clear node;

1103～recurrence logic ' 1 ' reset circuit;

1104～recurrence logic ' 1 ' activation node;

1105～recurrence logic ' 1 ' dominoes circuit; 1106～replacement node;

1108～output node; 1110～the second replacement nodes;

1200～recurrence logic ' 1 ' dominoes circuit; 1201～inverter;

1202～half holding circuits; 1203,1205～inverter;

1400～without clock, return logic ' 1 ' domino logic gate;

1401～recurrence logic ' 1 ' estimation circuit;

1403～recurrence logic ' 1 ' reset circuit;

1500～without clock, return logic ' 1 ' domino logic gate;

1501～recurrence logic ' 1 ' estimation circuit; 1502～via node;

1503～recurrence logic ' 1 ' reset circuit;

1600～without clock, return logic ' 1 ' domino logic gate;

1601～recurrence logic ' 1 ' estimation circuit;

1603～recurrence logic ' 1 ' reset circuit;

1700～without clock, return logic ' 1 ' domino logic gate;

1703～recurrence logic ' 1 ' reset circuit;

CLK～clock signal;

EVAL～the first status signal;

I1...I6～input signal;

I1 (RT0) ... IM (RT0), IX (RT0)～recurrence logic ' 0 ' input signal;

I1 (RT1) ... IM (RT1), IX (RT1)～recurrence logic ' 1 ' input signal;

IN～input signal;

IN (NON-RTS)～non-state returns input signal;

IN (RTS)～state returns input signal;

N1, N2, NA...NM～N lane device;

O1 (RST), O2 (RST)～output signal;

OUT～output;

OUT (RT0)～recurrence logic ' 0 ' output signal;

OUT (RT1)～recurrence logic ' 1 ' output signal;

OUT (RTS)～state returns output signal;

P1, P2, P3, PA...PM～P lane device;

PCHG～preliminary filling input/output terminal/signal;

PCLR～pre-clear input/output terminal/signal;

PSET～preset input/output terminal;

RESET～the second status signal;

RST～reset signal; RSTB～anti-phase reset signal;

RT0E～recurrence logic ' 0 ' enable signal;

RT1E～recurrence logic ' 1 ' enable signal;

RTSE～state returns enable signal;

T0...T14～time point;

VDD～confession electric potential;

VSRC1, VSRC2～power supply potential; VSS～reference potential.

Embodiment

Below illustrate help those skilled in the art are able to the disclosed summary of the invention of this specification to make and apply to application-specific and condition.Those skilled in the art may develop various deformation according to following disclosed execution mode, and the disclosed skill of specification also may realize with other execution modes.Therefore, scope of the present invention is not intended to be limited to shown below or described specific embodiment, in fact, should explain with the widest scope of disclosed skill and feature.Inventor found industry at a high speed, efficient and need not rely on the demand of the logical operation of clock signal.Therefore, inventor develops state that need not clock signal and returns domino logic gate, and Fig. 1～Figure 17 discussion is below provided.

Fig. 1 is the calcspar of a simplification, a diagram one chip (or integrated circuit, IC) 101, comprising what realize according to one embodiment of the present invention, one without clock status, return dominoes circuit (clockless return to state domino circuit) 105.Integrated circuit 101 can be any form, and can comprise any amount of electronic circuit that the art has developed.In one embodiment, chip 101 is a processor, similar devices such as a microcontroller (microcontroller) or microprocessor (microprocessor), and in addition, the integrated circuit of any type or chip all may be applied for it.One clock signal clk is arranged on this integrated circuit 101, returns logical one 03 receive by a state.This state returns logical one 03 one or more state of output and returns input signal IN (RTS) to coupling this plurality of input nodes without clock status recurrence dominoes circuit 105 corresponding inputs.This clock signal clk is also pulled strings to non-state recurrence logic (NON-RTS logic) 104.This non-state returns one or more non-state of logical one 04 output and returns signal IN (NON-RTS) to coupling this plurality of inputs without clock status recurrence dominoes circuit 105 corresponding inputs.Below more describe in detail.Along with return the design difference of dominoes circuit 105 without clock status, the content of input signal IN (combination of IN (RTS) and IN (NON-RTS)) can be different.(for example, two configuration design/dual configurations) in some applications, each input signal IN is that state returns signal RTS (being designed to example with logic sum gate).In addition, other application in (for example, non-two configuration design/non-dual configuration), having one at least for state returns signal RTS in input signal IN, is state recurrence signal RTS or non-state recurrence NON-RTS signal as for remaining each signal in input signal IN.Conventionally, be under following situation, to need development to return signal with above-mentioned state is provided.Above-mentionedly without clock status, return the one or more states of dominoes circuit 105 output and return output signal OUT (RTS) to the correlated inputs end of another logical circuit 107, and clock signal clk is also connected to the input end of clock of logical circuit 107.State returns logical one 03 and comprises the combination of any static state or dynamic circuit, and also comprises the combination of any latching (latch) or buffer circuit, to return operation according to state, provides input signal IN (RTS).Logical one 07 comprises combination and/or any latching or the combination of buffer of any static state or dominoes circuit (have pin position footed or without pin position footless), to receive or to latch or temporary described output signal OUT (RTS).

What described state returned input and output signal IN and OUT representative is that signal can be got back to a predetermined state or one first state after being switched to one second state.In binary system logic, it is not to get back to logic ' 0 ' RT0 that state returns, and its logic of propositions state is logic ' 0 '), get back to exactly logic ' 1 ' (RT1, its logic of propositions state is logic ' 1 ').Without clock status, return dominoes circuit 105 and comprise that one or more is without clock-state regression domino logic gate.Describedly without clock-state regression domino logic gate, go here and there each other repeatedly (cascade), or be coupled in together according to any serial or parallel connection mode.All having an opportunity to be gone here and there repeatedly or be cascaded without clock-state regression domino logic gate of multiple quantity, is only limited to time conditions, and whether effectively described time conditions is defined in corresponding output signal.Each can receive any amount of state without clock-state regression domino logic gate and return input signal and export at least one state and return and output signal to other circuit-comprise that other are without clock-state regression domino logic gate or logical circuit 107 or other similar circuit.

Fig. 2 is a calcspar, diagram according to a kind of execution mode of the application, realize one without clock-state regression domino logic gate 200, in order to realize this, without clock status, return one or more without clock-state regression domino logic gate in dominoes circuit 105.One or more signal provision in input signal IN are given on corresponding input node, and to input to the corresponding input of a state regression estimation circuit 201, and at least one above-mentioned input signal IN can offer a state recurrence reset circuit 203.Although in figure, indicate by same input signal IN supplying to circuit 201 with 203 both, in some embodiments-below by discuss in detail-what be supplied to this state recurrence reset circuit 203 can be only a subclass of above-mentioned input signal IN.In addition, input signal IN can be state and returns signal (RTS) and maybe can comprise that one or more non-state returns signal (non-RTS).Without clock-state regression domino logic gate 200, also comprise that a state returns dominoes circuit 205; This state returns dominoes circuit 205 and couples a pair of power supply potential VSRC1 and VSRC2.Each is provided power supply potential VSRC1 and VSRC2 by a power circuit (without showing in the drawings), and supplies power supply potential to a plurality of electronic circuits on integrated circuit 101 with suitable current potential unification, and institute's employing technology can be the art common technique.The current potential that each power supply potential is supplied and corresponding potential region between power supply potential VSRC1 and VSRC2 and circuit pattern and particular technology or technique are relevant, for example, can be 5 volts, 3.3 volts or 2.1 volts etc.Conventionally, one of power supply potential VSRC1 and VSRC2 are that (for example, VSS), and another is one for electric potential VDD to a reference potential, can the art common technique realize.State regression estimation circuit 201, state return reset circuit 203 can form an input circuit jointly with state recurrence enable circuit 207, corresponding input signal IN action.

State regression estimation circuit 201 couples power supply potential VSRC2, and also couples a preset node 202 to couple a preset input/output terminal PSET of this state recurrence dominoes circuit 205.This state recurrence dominoes circuit 205 has an output and supplies a state recurrence output signal OUT (RTS) in an output node 208, and there is a replacement input/output terminal RST and produce a reset signal (being designated as equally RST) in a replacement node 206, and also there is a state and return enable signal output RTSE and supply a state and return enable signal (being designated as equally RTSE) and return activation node 204 in a state of correspondence.Without clock-state regression domino logic gate 200, comprise that a state returns enable circuit 207 and couples power supply potential VSRC1.This state returns enable circuit 207 to be had an input and couples node 204 and return enable signal RTSE to receive this state, and has another end points and couple one second replacement node 210.This state returns reset circuit 203 and is coupled between above-mentioned replacement node 210 and 206.

Each signal node (for example, IN, OUT, PSET, RST, RTSE etc.) has one first logic state and one second logic state; This first logic state is relevant to power supply potential VSRC2, and this second logic state is relevant to power supply potential VSRC1.State regression estimation circuit 201 has an initial preset state, and now each input signal IN is above-mentioned the first logic state, identical with its persistent state (return state).When together transition of above-mentioned input signal IN, while forming in one or more estimated state any, this state regression estimation circuit 201 enters an estimated state, produces an estimation event.The described estimation event of one or more estimated state of described input signal IN-produce-relevant by this state regression estimation circuit 201 logical design separately.For example, if this state regression estimation circuit 201 is designed to a logic sum gate, when an estimation event is appointed the transition that one or more the first state to the second state occurs in described input signal IN, occur.In another kind of execution mode, if this state regression estimation circuit 201 is to be embodied as a logical AND gate, an estimation event only can be occurred during to this second logic state by this first logic state transition at each input signal IN.This state returns dominoes circuit 205 and conventionally has two states, comprises a preset condition (" preset " state) and a latch mode (" latch " state).This preset condition is generally the initial or preset value that this state returns dominoes circuit 205.Under this preset condition, this state returns preset its preset input/output terminal PSET of dominoes circuit 205 meeting, so node 202 is this second logic state.In addition,, under this preset condition, state returns this reset signal of dominoes circuit 205 initial settings RST for this first logic state and sets this state and returns enable signal RTSE for this second logic state.This state returns reset circuit 203 and has an isolation (isolation state) and a Reset Status (reset state), by the Determines of the described input signal IN being applied thereto.When put on described input signal IN that this state returns reset circuit 203 separately in or return this first logic state, it is its Reset Status that this state returns reset circuit 203.Otherwise this state returns reset circuit 203 in its isolation.Must specify, when collective's state symbol of described input signal IN closes any of one or more estimated state, it is to be positioned at its isolation that state returns reset circuit 203.When this state returns enable signal RTSE in this second logic state, this state returns enable circuit 207 in its initial preset state; When this state returns enable signal RSTE in this first logic state, this state returns enable circuit 207 transition to enabled status.

Operation without clock-state regression domino logic gate 200 is below discussed.One estimation event occur in described input signal IN transition be in one or more estimated state any time; Now, this state regression estimation circuit 201 enters its estimated state and this state and returns reset circuit 203 and enter its isolation.In above-mentioned estimated state, this state regression estimation circuit 201 changes the signal of node 202, therefore, state returns the preset input/output terminal PSET transition of dominoes circuit 205 to this first logic state, causes this state to return dominoes circuit 205 and is switched to latch mode from its preset condition.This state returns dominoes circuit 205 and when being switched to its latch mode, switches output signal OUT to this second logic state, and switching state recurrence enable signal RTSE to the first logic state, and no longer affects this reset signal RST.State returns enable circuit 207 and enters its enabled status, couples node 210 to power supply potential VSRC1, to respond the state of the first logic state, returns enable signal RTSE.Because state returns reset circuit 203, respond input signal IN in its isolation, therefore, even if state returns enable circuit 207, be enabled, still do not affect this reset signal RST.For these reasons, this reset signal RST still maintains the first logic state.

When returning input signal IN, the state that is supplied to state to return reset circuit 203 gets back to its preset state according to state recurrence operation, state returns reset circuit 203 and enters its Reset Status, replacement node 210, together with 206 are coupled in, is pulled to this second logic state by circuit 203 and 207 by reset signal RST.The transition meeting of reset signal RST to the second logic state causes a resetting event, makes state return dominoes circuit 205 and returns its preset condition.Be described as follows, state returns the current potential that dominoes circuit 205 can change its preset input/output terminal PSET, makes node 202 get back to the second logic state.In addition, state returns dominoes circuit 205 can switch back the first logic state by output signal OUT, and switching state recurrence enable signal RTSE returns this second logic state.This state returns enable circuit 207 and can corresponding states return the transition of enable signal RTSE to the second logic state and effectively close, and state recurrence dominoes circuit 205 can retract the first logic state by reset signal RST.

Generally speaking, when input signal IN together transition in one or more estimated state any time, 201 transitions of state regression estimation circuit, to an estimated state, produce an estimation event, and this state returns reset circuit 203 and enters an isolation.Respond above-mentioned estimation event, state recurrence dominoes circuit 205, switches output signal OUT and switches this state recurrence enable signal RTSE with this state recurrence enable circuit 207 of activation to latch mode from its preset condition transition.When these states that return input signal IN or be at least supplied to this state to return reset circuit 203 when each state return input signal IN and return operation and get back to the first logic state according to state, state regression estimation circuit 201 is got back to its preset state and this state and is returned reset circuit 203 and enter its Reset Status and move this reset signal RST to this second logic state to produce a resetting event.Respond this resetting event, this state returns dominoes circuit 205 and gets back to its preset condition, makes this state return enable signal RSTE and returns this second logic state with this state recurrence enable circuit 207 of decapacitation.Once these state recurrence enable circuit 207 decapacitation, state returns the just no longer impact operation of state of reset circuit 203, until after another estimation event generation.This state returns dominoes circuit 205 and subsequently reset signal RST is retracted to the first logic state, makes this without clock-state regression domino logic gate 200, get in advance the next estimation event of meeting ready.Thus, without clock-state regression domino logic gate 200, be a self-reset circuit, need not clock signal realize a Logical Status estimation.

Below more discuss without one of clock-state regression domino logic gate 200 and return the design of logic ' 0 ' (RT0) gate and recurrence logic ' 1 ' (RT1) gate design.Described recurrence logic ' 0 ' gate design is to return logic ' 0 ' input signal for responding.Described recurrence logic ' 1 ' gate design is to return logic ' 1 ' input signal for responding.In some embodiments, it is two configurations (dual configurations) designs that state regression estimation circuit 201 and state return reset circuit 203, in order to respond same state, returns input signal IN.In such execution mode (for example, the 10th and 17 figure illustrated embodiment), state returns reset circuit 203 and is simplified, wherein, be supplied to these states recurrence input signals IN of this state regression estimation circuit 201 also can be supplied to state to return reset circuit 203, meanwhile, by state, returning reset circuit 203 with the same logical operation meeting of state regression estimation circuit 201 is implemented in this selected state and returns on input signal IN subclass.In other embodiments, the not two configuration designs of circuit 201 and 203, and in the described input signal IN of supplying to circuit 201 only a subclass be to be supplied to this state to return reset circuit 203.The described input signal IN that is supplied to this state to return reset circuit 203 is that state returns signal, and no matter remaining input signal IN is state returns (RTS) or non-state recurrence (non-RTS) signal.In described arbitrary execution mode, estimated state is true time, and Reset Status is just false.When state regression estimation Circuit display estimated state does not meet, estimated state is invalid.In estimated state, be false but state returns the replacement condition of reset circuit while setting up, described Reset Status is set up.

Fig. 3 is a calcspar, and diagram one returns logic ' 0 ' domino logic gate 300 without clock, is a kind of recurrence logic ' 0 ' execution mode without clock-state regression domino logic gate 200.Output signal OUT and at least one input signal IN are designed to return logic ' 0 ' signal, take logic ' 0 ' as logic of propositions state.Based on the art prior art, using power supply potential VSRC1 as a confession electric potential VDD, and using power supply potential VSRC2 as a reference potential VSS.This state regression estimation circuit 201, state return dominoes circuit 205 and state recurrence reset circuit 203 is realized as respectively recurrence logic ' 0 ' estimation circuit 301, recurrence logic ' 0 ' dominoes circuit 305 and return logic ' 0 ' reset circuit 303, in order to design according to returning logic ' 0 ' operation.Should be noted that, although in circuit 301 and 303 any may to isolate other circuit be recurrence logic ' 1 ' circuit (seeing with its output), but still be that what take that its input is patrolled with recurrence and the viewpoint of ' 0 ' domino logic gate 300 allomeric functions is looked is recurrence logic ' 0 ' technology.Aforementioned preset input/output terminal PSET is implemented as a preliminary filling input/output terminal PCHG.This preliminary filling input/output terminal PCHG couples a precharged node 302; This precharged node 302 is realized aforementioned preset node 202.Without clock, return logic ' 0 ' domino logic gate 300 and set recurrence logic ' 0 ' output signal OUT in an output node 308, reset signal RST is created in replacement node 306.Aforesaid state returns activation node 204 and is implemented as recurrence logic ' 0 ' activation node 304, couples the grid of P lane device P1.Described P lane device P1 realizes aforesaid state and returns enable circuit 207.It is that VDD and its drain electrode couple and return logic ' 0 ' reset circuit 303 via one second replacement node 310 that the source electrode of P lane device P1 couples power supply electricity.Return logic ' 0 ' reset circuit 303 and also couple replacement node 306.

Fig. 4 diagram one returns logic ' 0 ' dominoes circuit 400, for returning a kind of execution mode of logic ' 0 ' dominoes circuit 305.Precharged node 302 couples the input of an inverter 401, and couples the drain electrode of P lane device P2 and P3.The output of inverter 401 couples output node 308 described recurrence logic ' 0 ' output signal OUT (RT0) is provided, and it is supplied to the grid of P lane device P3 and the input of another inverter 403.The output of inverter 403 couples node 304 and with supply shape, returns the grid of logic ' 0 ' enable signal RT0E to N lane device N1.The source electrode of N lane device N1 couples reference potential VSS, and its drain electrode couples replacement node 306 with supply reset signal RST.Reset signal RST is supplied to the input of an inverter 405.The output of inverter 405 is supplied an anti-phase reset signal RSTB.Anti-phase reset signal RSTB is supplied to the grid of P lane device P2, and its source electrode couples for electric potential VDD.Inverter 401 together forms half with P lane device P3 and maintains (half-keeper) circuit 402, to maintain the level of preliminary filling input/output terminal PCHG until return logic ' 0 ' estimation circuit 301 it dragged down.The initial preliminary filling of preliminary filling input/output terminal PCHG is high level, and therefore, it is low level that inverter 401 makes output signal OUT, with conducting P lane device P3.P lane device P3 is pulled to preliminary filling input/output terminal PCHG for electric potential VDD, to maintain the high level logic state of preliminary filling input/output terminal PCHG.Because output signal OUT is initially low level, inverter 403 orders return logic ' 0 ' enable signal RT0E conducting N lane device N1, to drag down the level of reset signal RST.The inverter 405 thereby anti-phase reset signal RSTB of high level can be provided, makes not conducting of P lane device P2.

With reference to figure 3 and Fig. 4, respond in input signal IN that single or multiple transition is one or more estimated state wherein a kind of time the estimation event that produces, returning logic ' 0 ' estimation circuit 301 can drag down preliminary filling input/output terminal PCHG level, causes and returns logic ' 0 ' dominoes circuit 400 transitions to its latch mode.Therefore, inverter 401 is drawn high the level of output signal OUT, makes not conducting of P lane device P3.Inverter 403 can drag down the level that returns logic ' 0 ' enable signal RT0E, makes the P1 conducting of P lane device and makes not conducting of N lane device N1.The conducting meeting of P lane device P1 is couple to for electric potential VDD node 310.The not conducting meeting of N lane device N1 makes reset signal RST no longer be restricted to low level.The estimated state of input signal IN can make to return logic ' 0 ' reset circuit 303 transitions to its isolation, makes node 306 isolation nodes 310.Thus, replacement node 306 can temporarily be isolated, therefore reset signal RST can deliberately not driven as any state.Due to without any other device effects, reset signal RST still maintains low level.In another embodiment, separately there is a N lane device N2 (indicating with dotted line) supply in Fig. 4 circuit, form second half holding circuit with inverter 405, to maintain the low level state of reset signal RST.N lane device N2 has a grid and receives anti-phase reset signal RSTB, and a drain electrode couples node 306, and one source pole couples reference potential VSS.Because anti-phase reset signal RSTB is initially high level, it is still low level that N lane device N2 makes node 306 under the state of not conducting of N lane device N1.N lane device N2 is for guaranteeing or guaranteeing that reset signal RST is still low level under aforesaid state.When input signal IN is in estimated state, return logic ' 0 ' reset circuit 303 and maintain its isolation.

When being supplied to each recurrence logic ' 0 ' input signal IN of this recurrence logic ' 0 ' reset circuit 303 to revert to its preset state, return logic ' 0 ' reset circuit 303 transitions to its Reset Status, produce a resetting event, wherein, P lane device P1 and recurrence logic ' 0 ' reset circuit 303 together draw high reset signal RST into high level.Note that if described circuit has N lane device N2, returning logic ' 0 ' reset circuit 303 needs design to resist N lane device N2 to draw high the level of reset signal RST.Inverter 405 thereby can drag down the level of anti-phase reset signal RSTB, makes P lane device P2 conducting.The P lane device P2 of conducting can be pulled up to its preset state by the current potential of preliminary filling input/output terminal PCHG.Please note, when being supplied to each recurrence logic ' 0 ' input signal IN of this recurrence logic ' 0 ' reset circuit 303 to get back to preset state, input signal IN is no longer in an estimated state, therefore return the level that logic ' 0 ' estimation circuit 301 no longer drags down default input/output terminal PCHG.Thus, P lane device P2 draws high back its precharging state by the level of preliminary filling input/output terminal PCHG.When the level of preliminary filling input/output terminal PCHG is high level, it is low level again that inverter 401 makes output signal OUT, and with conducting P lane device P3, maintaining preliminary filling input/output terminal PCHG is high level.Inverter 403 will return logic ' 0 ' enable signal RT0E and draw high as high level is with conducting N lane device N1 and make not conducting of P lane device P1.Due to not conducting of P lane device P1, return logic ' 0 ' reset circuit and isolate for electric potential VDD, and no longer draw high reset signal RST.In addition, the N lane device N1 of conducting can move reset signal RST to low level, and it is high level that inverter 405 can draw high anti-phase reset signal RSTB, to make not conducting of P lane device P2 (and in having the example of supply N lane device N2, also comprise and make N lane device N2 conducting).Although not conducting of P lane device P2, it is high level that half holding circuit 402 can maintain preliminary filling input/output terminal PCHG.Thus, return logic ' 0 ' dominoes circuit 400 its preset condition of resetting back, be ready to meet next estimation event.

Fig. 5 returns the operation of logic ' 0 ' domino logic gate 300 without clock with sequential chart diagram, wherein according to a kind of execution mode, will return logic ' 0 ' dominoes circuit 400 and return logic ' 0 ' dominoes circuit 305 for realizing.The first status signal EVAL shows an estimated state of this recurrence logic ' 0 ' estimation circuit 301, and the establishment of this estimated state represents the generation of an estimation event.The first status signal EVAL is high level and when this estimated state is false, is low level when this estimated state is set up.The quantity of the estimated state of input signal IN is decided by return the logic function design of logic ' 0 ' dominoes circuit 305.For example, if return logic ' 0 ' dominoes circuit 305, be designed to a logic OR function, in these input signals IN any or a plurality ofly can distinguish a corresponding estimated state for the situation of high level.If return logic ' 0 ' dominoes circuit 305, be that design realizes a logical AND function, input signal IN only has an estimated state; Under this estimated state, each input signal IN is high level.The second status signal RESET shows a Reset Status that returns logic ' 0 ' reset circuit 303; When this Reset Status is set up, this second status signal RESET is high level; When this Reset Status is false, this second status signal RESET is low level.The state that described Reset Status is decided by return the design of logic ' 0 ' reset circuit 303 and is supplied to these input signals IN that returns logic ' 0 ' reset circuit 303.Whenever input signal IN is any of a kind of or multiple estimated state, Reset Status is false and is returned logic ' 0 ' reset circuit 303 in its isolation.When being supplied to each that return logic ' 0 ' reset circuit 303 to return logic ' 0 ' input signal IN to get back to logic ' 0 ', return logic ' 0 ' reset circuit 303 in its Reset Status.Described resetting event only betides recurrence logic ' 0 ' enable signal RT0E and makes the low level of P lane device P1 conducting and return logic ' 0 ' reset circuit 303 when its Reset Status.Estimation and reset circuit design are to each other relied in minority application.No matter be two configurations or non-two configuration design, when all input signal IN return logic ' 0 ', Reset Status is set up, and estimated state is false.Under two configurations and non-two configuration design, when estimated state is set up, the neither establishment of Reset Status.Under non-two configuration design, only a subclass of input signal IN is to be supplied to this recurrence logic ' 0 ' reset circuit 303, and Reset Status may be also false when estimated state is false, and may change into after being false and still maintain and be false in estimated state.

Fig. 5 comprises the sequential chart of signal EVAL, RESET, PCHG, OUT, RT0E, RST and RSTB.Shown in the transition of signal to postpone be only signal effect, be not intended to for the particular design bounded delay time.At initial time T0, the first status signal EVAL is low level, represents that input signal IN is not in estimated state.The second status signal RESET is junk at sequential T0.Note that input signal IN (at least these are for returning the signal of logic ' 0 '), behind an estimation interval and before the interval effect of next estimation, returns as logic ' 0 ' according to returning logic ' 0 ' operation.Yet each input signal may have different time delays.When input signal IN is all set as preset state, the first status signal EVAL is that low level and the second status signal RESET are high level.If some or be a plurality ofly converted to high level but still do not meet the condition (once estimating before interval upper) of estimated state in input signal, the second status signal RESET may between bifurcation, convert one or repeatedly and simultaneously the first status signal EVAL maintain low level.Therefore, the second status signal RESET as shown in the figure, is not particular state, in addition, because state returns enable circuit 207 (being realized by P lane device P1 in returning logic ' 0 ' example), do not act on, described any bifurcation early than estimation event changes unimportant.Signal PCHG, OUT, RT0E, RST and RSTB are initially set respectively logic ' 1 ', ' 0 ', ' 1 ', ' 0 ' and ' 1 ' in time T 0.

The time point T1 continuing, input signal IN together enters an estimated state, so the first status signal EVAL draws high and the second status signal RESET drags down.Respond the first status signal EVAL of high level, return logic ' 0 ' estimation circuit 301 and drag down preliminary filling input/output terminal PCHG current potential by the connecting time point T2 after short delay, to cause an estimation event.Because the second status signal RESET is low level, return logic ' 0 ' reset circuit 303 in its isolation.Response is pulled to low level preliminary filling input/output signal PCHG, and the connecting time point T3 of inverter 401 after short delay draws high the level of output signal OUT.Along with drawing high of output signal OUT, the connecting time point T4 of inverter 403 after short delay drags down the level of this recurrence logic ' 0 ' enable signal RT0E, with conducting P lane device P1 and not conducting N lane device N1.Because returning logic ' 0 ' reset circuit 303 is not conducting, reset signal RST is not affected by any device, and maintains low level (or maintaining low level by N lane device N2).The state that returns logic ' 0 ' domino logic gate 300 without clock remains unchanged and the first status signal EVAL is high level.At the time point T5 continuing, in input signal IN, one or more signal changes its state, causes estimated state to be false, corresponding it, the first status signal EVAL transition is low level.If be supplied to return logic ' 0 ' reset circuit 303 input signal each also get back to logic ' 0 ', the second status signal RESET draws high as dotted line 501 at time point T5.If the embodiment of the two configuration designs of right and wrong, the first status signal EVAL transition to low level, and the second status signal RESET transition to there being a delay between high level.Must be noted that estimated state is false and returns logic ' 0 ' estimation circuit 301 and after time point T5, no longer drags down preliminary filling input/output signal PCHG because the first status signal EVAL is low level.Preliminary filling input/output signal PCHG maintains low level, until follow-up, by P lane device P2, is pulled up to high level.Note that it is low level that another half holding circuit (not in graphic) can be used to maintain preliminary filling input/output signal PCHG in above-mentioned condition.

At time point T5 or the time point T6 that continues, being supplied to the input signal IN transition that returns logic ' 0 ' reset circuit 303 is zero, and to start the Reset Status of this recurrence logic ' 0 ' reset circuit 303, making the second status signal RESET is high level.Described recurrence logic ' 0 ' replacement current potential 303 associating P lane device P1, the time point T7 after short delay draws high the current potential of reset signal RST, to start a resetting event.The time point T8 of inverter 405 after short delay drags down to respond it by anti-phase reset signal RSTB.Anti-phase reset signal RSTB transition is low level, and with conducting P lane device P2, the time point T9 after a short delay draws high back preset state by preliminary filling input/output signal PCGH.When preliminary filling input/output signal PCHG is high level, the time point T10 of inverter 401 after short delay is set as low level again by output signal OUT.Transition is that low level output signal OUT can conducting P lane device P3, to make half holding circuit 402 maintain this preliminary filling input/output signal PCHG be high level until next estimation interval will under draw.The time point T11 of inverter 403 after short delay will return logic ' 0 ' enable signal RT0E and move high level to.The high level state that returns logic ' 0 ' enable signal RT0E can make the N1 conducting of N lane device and make not conducting of P lane device P1.Because not conducting of P lane device P1, returns logic ' 0 ' reset circuit 303 and no longer draws high reset signal RST.The conducting meeting of N lane device N1 makes the time point T12 of reset signal RST after short delay retract low level.Inverter 405 can draw high anti-phase reset signal RSTB to high level by the time point T13 after short delay, and therefore, P lane device P2 no longer draws high preliminary filling input/output signal PCHG.Now, by half holding circuit 402, maintaining preliminary filling input and output PCHG is high level.At time point T13 time point T14 after a while, signal recovers its preset state, return logic ' 0 ' estimation circuit 301 and P lane device P1 all in its preset state, return logic ' 0 ' dominoes circuit 305 and get back to its preset condition, in addition, suppose that in input signal IN, each signal is low level, return logic ' 0 ' reset circuit 303 in its Reset Status.Generally speaking, an estimated state of input signal IN causes an estimation event, and causing output signal OUT is high level, and the resetting event that continues of activation.The Reset Status of input signal IN causes returning logic ' 0 ' reset circuit 303 and causes a resetting event, and gets back to its initial condition without clock recurrence logic ' 0 ' domino logic gate 300, prepares to meet next estimation interval.

As shown in the figure, the second status signal RESET is that high level is until time point T11.During time point T11, returning logic ' 0 ' enable signal RT0E transition is that high level returns logic ' 0 ' domino logic gate without clock and gets back to its initial condition to determine this, and so far, the second status signal RESET is meaningless.Note that reset signal RST is when time point T7 moves high level to, even if Reset Status is false and is dragged down the second status signal RESET, reset signal RST still maintains high level, and reason is that N lane device N1 is still not conducting, cannot affect reset signal RST.Therefore, although should being maintained, sets up until ' 0 ' the enable signal RT0E transition of recurrence logic is high level Reset Status, input signal can drag down the level of the second status signal RESET and not exert an influence after time point T7 with before time point T11, therefore, can maintain suitable circuit operation.Once returning logic ' 0 ' enable signal RT0E is high level, not conducting of P lane device P1, and the meaningless transition of any input signal IN after time point T11 all without acting on.The situation of non-above-mentioned meaningless transition may cause an estimated state in addition.The state that note that returns signal RTS may not there is not meaningless transition.Yet some input signal, may return signal and may have meaningless transition for non-state.The input signal IN that is supplied to recurrence logic ' 0 ' estimation circuit 301 is that the estimated state that is selected to avoid potential occurs.

Fig. 6 is a block schematic diagram, and diagram one returns logic ' 0 ' domino logic gate 600 without clock, in order to realize a logic sum gate, M input signal I1...IM that returns logic ' 0 ' is done to logic OR computing, and wherein, M is greater than 1 positive integer.In such execution mode, input signal I1...IM returns logic ' 0 ' signal.Without clock, return logic ' 0 ' domino logic gate 600 and comprise recurrence logic ' 0 ' dominoes circuit 305.These recurrence logic ' 0 ' dominoes circuit 305 couple recurrence logic ' 0 ' estimation circuit 601 (returning logic ' 0 ' estimation circuit 301 in order to realize), and couple recurrence logic ' 0 ' reset circuit 603 (returning logic ' 0 ' reset circuit 303 in order to realize).Return logic ' 0 ' estimation circuit 601 and comprise M N lane device NA...NM, with drain electrode, couple node 302 separately, and with source electrode, couple reference potential VSS separately.N lane device NA...NM has a grid separately, as shown in the figure the corresponding input signal I1...IM that receives.Similarly, return logic ' 0 reset circuit 603 and comprise M P lane device PA...PM, be serially connected with between the second replacement node 310 and replacement node 306.As shown in the figure, wherein the drain electrode of first P lane device PA and P lane device P1 is coupled in node 310, couples the source electrode of next P lane device as for the drain electrode of P lane device PA.According to this serial connection rule, wherein last P lane device PM couples node 306 with its drain electrode.P lane device PA...PM separately as shown in the figure with grid receive input signal I1...IM one of them.Although only draw in a plurality of N lane device NA...NM two device NA and NM, a plurality of P lane device PA...PM two in diagram, install two signal I1 and the IM in PA and PM, a plurality of input signal I1...IM, it must be appreciated, any amount of described device and signal may be all its execution mode (for example, being supplied to the input signal I2... etc. of the grid of N lane device NB and P lane device PB).

Without clock, return a kind of execution mode that logic ' 0 ' domino logic gate 600 is two configuration designs, wherein return logic ' 0 ' reset circuit 603 for returning two configuration designs of logic ' 0 estimation circuit 601.Under two configuration designs, being supplied to and returning logic ' 0 ' estimation circuit 601 is all input signal I1...IM with the signal that returns logic ' 0 ' reset circuit 603.The operation that returns logic ' 0 ' domino logic gate 600 without clock meets the sequential chart shown in Fig. 5 conventionally.Under such state, when input signal I1...IM is logic ' 0 ' according to returning logic ' 0 ' operation, the first status signal EVAL is that low level and the second status signal RESET are high level.In input signal I1...IM, any is high level, and estimated state is set up, and Reset Status is false; Therefore, the first status signal EVAL is that high level state and the second status signal RESET are low level state.Because circuit 601 and 603 is two configuration designs, along with the transition of input signal IN is switched, the first status signal EVAL and the second status signal RESET can and then switch and be maintained each other anti-phase.Along with any transition in input signal IN is logic ' 1 ', preliminary filling input/output signal PCHG transition is low level, output signal OUT transition after short delay is high level, and ' 0 ' the enable signal RT0E transition after another section of short delay of recurrence logic is that low level is with activation one resetting event.When input signal I1...IM each when returning logic ' 0 ' operation and get back to logic ' 0 ', return logic ' 0 ' reset circuit 603 and cause this resetting event, making reset signal RST transition is high level, anti-phase reset signal RSTB transition is low level, and preliminary filling input/output signal PCHG draws high and gets back to as previously mentioned low level for high level and output signal OUT.

In some design, the limited amount that returns interior the be connected in series P lane device of logic ' 0 ' reset circuit 603 is specific quantity, to guarantee proper handling.For example, in one embodiment, the maximum quantity that allows to be serially connected with for the P lane device of 306 of electric potential VDD and replacement nodes is 4, the quantity of input signal thereby be restricted to 3 (M is 3).For the input signal to a large amount of carries out logic OR computing, can without ' 0 ' domino logic gate 600 combinations of clock recurrence logic or string, stack togather a plurality of, by a large amount of gates, any amount of input signal is carried out to logic OR computing, below describe in detail.

Fig. 7 is a simplification calcspar, and what three of diagrams formed with 705 without clock-state regression domino logic gate 701,703 one combines gate design 700, in order to realize a logical operation.Associating gate design 700 as shown is state and returns pattern, and can be applicable to any recurrence logic ' 0 ' or return logic ' 1 ' application.In one embodiment, six input signal I1...I6 produce a state and return output signal OUT after logical operation.In input signal I1...I3 at least one or upper to being all that state returns signal totally, and in input signal I4...I6 at least one or upper to being all that state returns signal totally.Associating gate design 700 comprise two three inputs without clock-state regression domino logic gate 701 and 703 and another dual input state return domino logic gate 705.State returns domino logic gate 701 and receives input signal I1...I3 and supply a state recurrence output signal O1 (RTS), returns an input signal of domino logic gate 705 as state.Similarly, state returns domino logic gate 703 and receives input signal I4...I6 and supply a state recurrence output signal O2 (RTS), returns another input signal of domino logic gate 705 as state.State returns domino logic gate 705 and returns defeated signal OUT (RTS) at its output supply status.Thus, a plurality of without clock-state regression domino logic gate can be combined or string stack togather, to deal with a large amount of input signals, complete a certain logic computing.In addition, still there are other designs can complete same computing.For example, with three dual input gates, realize first order structure, receive separately two signals in six input signals, and produce separately an output signal, using and combine the input signal as three input logic gates.Or described technology also can be used for realizing the logical operation of the input signal of other quantity, the above-mentioned input signal for several 6 is only that explanation is used.

Gate 701,703 in described associating gate design 700 respectively can for example, according to different logical operation demand-with 705, logical AND (AND), logic OR (OR), logical AND non-(NAND), logic NOT or (NOR), logic XOR (XOR) ... wait or the set of any described logical operation-coordinate suitable or available input signal realization.For example, about logic XOR-XOR (A, B) of signal A and signal B-a logic XOR gate, state return input signal A and B with and inversion signal A ' and B ' (label " ' " be represented as inversion signal) need be supplied.Gate 701,703 in associating gate design 700 can be carried out different computings from 705.Although in figure, only show three gates, must statement, the technology series, parallel that any amount of gate all can be known based on the art person or otherwise combine.For example, gate 701,703 and 705 can be embodied as a logic sum gate according to returning logic ' 0 ' dominoes logical circuits 600 without clock separately.In such execution mode, gate 701 is designed to a logic sum gate, and input signal I1...I3 is done to logic OR computing, to supply output signal O1; Gate 703 is designed to a logic sum gate, and input signal I4...I6 is done to logic OR computing, to supply output signal O2; And gate 705 is designed to a logic sum gate, signal O1 and O2 are done to logic OR computing, to produce output signal OUT.Thus, a large amount of without clock return logic ' 0 ' domino logic gate can be combined or string stack togather, deal with the logical operation of a large amount of input signals, for example, realize a logic OR computing.

Fig. 8 is a calcspar, and diagram one returns logic ' 0 ' domino logic gate 800 without clock, wherein according to another embodiment of the present invention, realizes the logical operation mixing.Without clock, return logic ' 0 ' domino logic gate 800 and comprise above-mentioned recurrence logic ' 0 ' dominoes circuit 305.These recurrence logic ' 0 ' dominoes circuit 305 couple recurrence logic ' 0 ' estimation circuit 801 (in order to realize this recurrence logic ' 0 ' estimation circuit 301) and and return logic ' 0 ' reset circuit 803 (in order to realize this recurrence logic ' 0 ' reset circuit 303).Return logic ' 0 ' estimation circuit 801 and comprise three N lane device NA, NB and NC, with drain electrode, couple node 302 separately, and with source electrode, couple a via node 802 separately.Return logic ' 0 ' estimation circuit 801 and also comprise two N lane device ND and NE, with drain electrode, couple node 802 separately, and with source electrode, couple reference potential VSS separately.N lane device NA...NE receives five input signal I1...I5 with grid respectively.In this embodiment, return logic ' 0 ' estimation circuit 801 and carry out a logical operation, make OUT=(I1|I2|I3) & (I4|I5), wherein, what symbol " | " represented is logic OR computing, and symbol " & " representative is logic and operation.One estimated state betides in input signal I1...I3 any when having at least one to be high level in high level and input signal I4 and I5.Return logic ' 0 ' reset circuit 803 and comprise two P lane device PA and PB, be serially connected with between the drain electrode and replacement node 306 of P lane device P1, and be coupled to node 310 with the drain electrode of P lane device P1.Special instruction, P lane device PA couples the drain electrode of P lane device P1 with source electrode, and with drain electrode, couples the source electrode of P lane device PB, and P lane device PB couples this replacement node 306 with drain electrode.Input signal I4 is supplied to the grid of P lane device PA to use, and input signal I5 is supplied to the grid of P lane device PB to use.In this embodiment, Reset Status only occurs when input signal I4 and I5 are all low level.Input signal I4 and I5 are for returning logic ' 0 ' signal; As for input signal I1...I3, can be and return logic ' 0 ' signal but be decided to be and return logic ' 0 ' signal without one.Although state returns signal and sets for expection, in some design, in conjunction with non-state, returning signal and state recurrence signal may be quite useful design.Described non-state returns signal may need to meet some with respect to the time conditions of these states recurrence signals.For example, in one embodiment, it may be that corresponding states returns signal and sets or maintain that non-state returns signal.

The operation that returns logic ' 0 ' domino logic gate 800 without clock generally meets the sequential chart shown in Fig. 5.In such embodiments, estimated state input signal I1...I3 eventually at least one for high level and input signal I4 and I5, at least one is set up during for high level, described estimated state is in time point T1 initiation estimation event.With reference to previously narration, respond described estimation event, preliminary filling input/output signal PCHG transition is low level, and then, output signal OUT transition is high level, then comes, and returning logic ' 0 ' enable signal RT0E transition is low level; Described transition is interval one short delay respectively.In the interval that described estimated state is set up, the first status signal EVAL maintains high level.Reset Status is only set up when input signal I4 and I5 are all set as low level.This second status signal RESET will maintain low level owing to having any to be high level in input signal I4 and I5, and therefore, the second status signal RESET maintains low level when the first status signal EVAL is high level.When the first status signal EVAL is when time point T5 transition is low level, if input signal I4 and I5 are low level simultaneously, it is high level that the second status signal RESET just understands transition.At time point T5, if input signal I4 and I5 all transition be low level, the second status signal RESET can transition be high level, but the second status signal RESET also likely maintains the low level time more of a specified duration.For example, if input signal I1...I3 all transition be low level and input signal I4 and I5 any be maintained high level, the second status signal RESET when the first status signal EVAL transition is low level still not transition to high level.Signal I4 to be entered and I5 (are for example low level according to returning logic ' 0 ' operation, with reference to figure 5 time point T6) the second status signal RESET transition be high level and return logic ' 0 ' reset circuit 803 and enter its Reset Status, to cause resetting event.As previous institute narrating content, respond described resetting event, reset signal RST transition is high level, anti-phase reset signal RSTB transition is low level, high level is returned in preliminary filling input/output signal PCHG transition, and output signal OUT transition returns low level, and above-mentioned transition is interval one short delay separately.

Without clock, returning logic ' 0 ' domino logic gate 800 is one non-pair of arrangement embodiments, wherein returns two configuration designs that logic ' 0 ' reset circuit 803 not returns logic ' 0 ' estimation circuit 801.In this embodiment, in input signal I1...I5, only there are subclass-input signal I4 and I5-to be supplied to this recurrence logic ' 0 ' reset circuit 803.Yet, due to estimated state only set up input signal I4 and I5 at least one during for high level, therefore, when returning logic ' 0 ' estimation circuit 801 and being its estimated state, return logic ' 0 ' reset circuit 803 inevitable in its isolation, can guarantee suitable operation.Particularly, when described estimation event starts, return logic ' 0 ' reset circuit 803 in its isolation, and these recurrence logic ' 0 ' dominoes circuit 305 transitions are its latch mode conducting P lane device P1.Reset signal RST is not subject to any device to determine current potential under described estimation condition.As input signal I4 and I5, according to returning logic ' 0 ', to operate equal transition be low level, returns logic ' 0 ' estimation circuit 801 and depart from its estimated state and return logic ' 0 ' circuit 803 and enter its Reset Status and cause a resetting event.Described resetting event makes these recurrence logic ' 0 ' dominoes circuit 305 transitions return its preset condition, makes not conducting of P lane device P1, and then drags down the level of reset signal RST, to prepare to meet next estimation event.

The associating gate structure that can be used for similar associating gate design 700 without the logical operation of clock recurrence logic ' 0 ' domino logic gate 800.For example, gate 701 can be realized by three input logics or door, receives input signal I1...I3, to supply an output signal O1.Gate 703 can be realized by a dual input logic sum gate, to receive two input signal I4 and I5 to supply an output signal O2.Gate 705 can be realized by a dual input logical AND gate, so that signal O1 and O2 are made to logic and operation.Thus, co-ordinative construction will realize logical operation (I1|I2|I3) & (I4|I5).In another kind of framework, also can provide the 3rd P lane device (not showing in the drawings) to be serially connected between node 310 and 306.Three P lane devices of serial connection are for receiving respectively input signal I1, I2 and I3.Resulting operation is equivalent, even if, with respect to the state (I4 and I5) of two input signals, the state of three input signals (I1, I2 and I3) may make to return logic ' 0 ' dominoes circuit 305 and return the spent time of preset condition slightly for a long time by latch mode transition.

Fig. 9 is a block schematic diagram, and diagram one returns logic ' 0 ' domino logic gate 900 without clock, wherein realizes a logical AND gate, returns logic ' 0 ' input signal I1...IM carry out logic and operation to M.In such logical AND embodiment, each is to return logic ' 0 ' signal for input signal I1...IM.Without clock, return logic ' 0 ' domino logic gate 900 and comprise described recurrence logic ' 0 ' dominoes circuit 305, couple and return logic ' 0 ' estimation circuit 901 (realizing described recurrence logic ' 0 ' estimation circuit 301) and recurrence logic ' 0 ' reset circuit 903 (realizing described recurrence logic ' 0 ' estimation circuit 303).Return logic ' 0 ' estimation circuit 901 and comprise M N lane device NA...NM, be serially connected with between preliminary filling Inport And Outport Node 302 and reference potential VSS.As shown in the figure, the drain electrode of N lane device NA couples node 302, and its source electrode couples the drain electrode of next N lane device in serial, and follows this rule until afterbody N lane device NM, and the source electrode of N lane device NM is coupled to reference potential VSS.As shown in the figure, N lane device NA...NM provides grid to receive input signal I1...IM separately.Accordingly, return logic ' 0 ' reset circuit 903 and comprise that M P lane device PA...PM is parallel between node 310 and replacement node 306.Particularly, the source electrode of P lane device PA...PM couples node 310, and drain electrode couples replacement node 306.

Without clock, return the embodiment that logic ' 0 ' domino logic gate 900 is another kind of two configuration designs.The operation that returns logic ' 0 ' domino logic gate 900 without clock is generally to meet the disclosed sequential chart of Fig. 5.In such embodiments, estimated state is to set up when all input signal I1...IM are high level, and now, the total conducting of N lane device NA...NM, together moves preliminary filling input/output terminal PCHG to reference potential VSS.When in input signal I1...IM, any is low level, Reset Status is set up.In this execution mode, returning logic ' 0 ' estimation is two configuration designs with reset circuit 901 and 903 each other.According to various application, described gate can be designed to receive the input signal of multiple quantity.Yet about return the discussion of logic ' 0 ' domino logic gate 600 without clock, in order to ensure operation correctness, the quantity that is serially connected in the N lane device in recurrence logic ' 0 ' estimation circuit 901 can be limited in specific quantity as previously.

Associating gate design 700 as discussed previously, returns logic ' 0 ' domino logic gate 900 without clock and can adopt repeatedly technology of string, realizes the logic and operation of any amount of input signal with multiple logic and door.Gate 701,703 and 705 each can be embodied as a logical AND gate with reference to return logic ' 0 ' domino logic gate 900 without clock.In one embodiment, gate 701 is designed to a logical AND gate, in order to input signal I1...I3 is made to logic and operation, to produce signal O1; Gate 703 is designed to a logical AND gate, and to input signal, I4...I6 does logic and operation, to produce signal O2; Gate 705 is designed to a logical AND gate, and signal O1 and O2 are made to logic and operation, to produce output signal OUT.Thus, a plurality of without clock return logic ' 0 ' domino logic gate can be combined or string stack togather, for example, to realize certain logic computing-, the processing of logic and operation-to number of input signals.

Figure 10 is a calcspar, and another returns logic ' 0 ' domino logic gate 1000 without clock diagram, for realizing a logical AND gate, returns logic ' 0 ' input signal I1...IM and makes logic and operation, and comprise the reset circuit 1003 of a simplification to M.Without clock, return logic ' 0 ' domino logic gate 1000 haply with similar without clock recurrence logic ' 0 ' domino logic gate 900, wherein same element adopts same numbering.Relatively two circuit, return logic ' 0 ' reset circuit 903 and change by recurrence logic ' 0 ' reset circuit 1003 realizations.In general the operation that returns logic ' 0 ' domino logic gate 1000 without clock also meets the disclosed sequential chart of Fig. 5.Return logic ' 0 ' reset circuit 1003 and only comprise a P lane device PA, the drain electrode that couples P lane device P1 with source electrode is in node 310, and couples replacement node 306 with drain electrode.In input signal I1...IM, any, be denoted as signal IX in figure, can be supplied to the grid of P lane device PA.

Compare with return logic ' 0 ' domino logic gate 900 without clock, it is identical without clock, returning the performed computing of logic ' 0 ' domino logic gate 1000, but is to be designed to non-pair of configuration structure.The operation that returns logic ' 0 ' domino logic gate 1000 without clock is substantially similar without clock recurrence logic ' 0 ' domino logic gate 900, and difference is in its Reset Status only to be set up when input signal IX is low level.When input signal I1...IM-comprises signal IX-all transition is high level, Reset Status is false, and estimation event occurs.When signal IX transition is logic ' 0 ', described estimated state is false and described Reset Status is set up, and a resetting event is initiated, and makes this without clock, return logic ' 0 ' dominoes circuit 305 and gets back to its preset condition.The advantage that returns logic ' 0 ' domino logic gate 1000 without clock is recurrence logic ' 0 ' reset circuit of simplifying, and wherein only with a P lane device, realizes; Yet, if signal IX returns zero level in the mode slow compared with other input signals, have certain speed loss and occur.The advantage that returns logic ' 0 ' domino logic gate 900 without clock may speed reaction speed, and reason is, after estimation event, when resetting event can in input signal, any transition be zero level, speed immediately occurs; Yet, can need ' 0 ' the reset circuit design of more complicated recurrence logic.If one of described input signal IN must can be chosen as signal IX for the fastest recurrence logic ' 0 ' signal, to solve the reaction speed problem that returns logic ' 0 ' domino logic gate 1000 without clock.

Sequential chart with reference to figure 5, that looks back employing recurrence logic ' 0 ' dominoes circuit 400 returns logic ' 0 ' domino logic gate 300 without clock, wherein, selected a plurality of or all input signals (depending on its particular design) are when returning logic ' 0 ' and be operating as (or transition to) logic ' 0 ', and without clock, returning logic ' 0 ' domino logic gate 300 is its initial preset state.When input signal makes estimated state, set up, Reset Status is for being false, and an estimation event occurs.Under the state of setting up in estimated state, Reset Status is maintained is false.When recurrence logic ' 0 ' input signal that is supplied to reset circuit reverts to its logic of propositions ' 0 ' state, described estimated state transition is for being false, and described Reset Status is set up thereafter.Reset is finally to occur according to returning logic ' 0 ' operation.About return logic ' 0 ' domino logic gate 600 without clock, at input signal I1...IM, each occurs when all transition is logic ' 0 ' resetting event.About return logic ' 0 ' domino logic gate 800 without clock, generation when resetting event is logic ' 0 ' in a subclass of input signal I1...I5-be input signal I4 and I5-transition.About return logic ' 0 ' domino logic gate 900 without clock, resetting event occurs when wherein any transition is logic ' 0 ' at input signal I1...IM.About return logic ' 0 ' domino logic gate 1000 without clock, resetting event in input signal selected one-be that signal IX-transition occurs while being logic ' 0 '.

Figure 11 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate 1100 without clock, according to a kind of recurrence logic ' 1 ' execution mode without clock-state regression domino logic gate 200, realizes.One or more input signal is designed to return logic ' 1 ' signal with the output signal producing, and the logic of propositions state having is logic ' 1 '.Power supply potential VSRC1 is designed to reference potential VSS, and power supply potential VSRC2 is designed to for electric potential VDD, contrary with the design that returns logic ' 0 ' domino logic gate 300 without clock.State regression estimation circuit 201, state return dominoes circuit 205 and state recurrence reset circuit 203 with recurrence logic ' 1 ' estimation circuit 1101,, is returned logic ' 1 ' dominoes circuit 1105 respectively and recurrence logic ' 1 ' reset circuit 1103 is realized, and it returns ' 1 ' operational design according to a state.Although note that circuit 1101 and 1103 may be regarded as returning logic ' 0 ' circuit separately because of the operation of its output signal, be still according to its input signal and recurrence logic ' 1 ' domino logic gate 1100 mass actions it is considered as returning logic ' 1 ' circuit.The aforesaid preset end PSET that inputs out changes by a pre-clear input/output terminal PCLR who couples a pre-clear node 1102 and replaces.The output that returns logic ' 1 ' domino logic gate 1100 without clock is set recurrence logic ' 1 ' output signal OUT at an output node 1108, and produces reset signal RST at a replacement node 1106.State returns activation node 204 and is realized by recurrence logic ' 1 ' activation node 1104, couples the grid of N lane device N1, to realize state, returns enable circuit 207.N lane device N1 couples reference potential VSS and couples the second replacement node 1110 with source electrode with source electrode, and recurrence logic ' 1 ' reset circuit 1103 is coupled between replacement node 1110 and 1106.

Figure 12 is a block schematic diagram, and diagram one returns logic ' 1 ' dominoes circuit 1200, for returning a kind of execution mode of logic ' 1 ' dominoes circuit 1105.Return logic ' 1 ' dominoes circuit 1200 for returning the anti-phase design of logic ' 0 ' dominoes circuit 300, wherein with reference potential VSS, replace the confession electric potential VDD in circuit 300, for electric potential VDD, replace the reference potential VSS in circuit 300, with P lane device, replace the N lane device in circuit 300, with N lane device, replace the P lane device in circuit 300, and the mode of operation that makes each node is that (logic ' 0 ' state replaces to logic ' 1 ' state for the rp state of circuit 300 interior corresponding node, and logic ' 1 ' state replaces with logic ' 0 ' state).In addition, the P passage in each inverter and N lane device and power supply potential design are all the anti-phase designs of circuit 300; In figure because performed be similarly anti-phase computing, so the identical symbol of it employing is represented.Pre-clear node 1102 couples the input of inverter 1201, and couples the drain electrode of N lane device N2 and N3.The output of inverter 1201 couples output node 1108 and returns logic ' 1 ' output signal with supply, and also couples the grid of N lane device N3 and the input of inverter 1203.The output of inverter 1203 is coupled to node 1104 and returns logic ' 1 ' enable signal RT1E with supply, to put on the grid of P lane device P1.P lane device P1 couples for electric potential VDD and with drain electrode and couples replacement node 1106 with supply reset signal RST with source electrode.Reset signal RST is supplied to the input of inverter 1205, and the output of inverter 1205 is supplied an anti-phase reset signal RSTB.Reversed-phase output signal RSTB is supplied to the grid of N lane device N2, and the source electrode of this N lane device N2 couples reference potential VSS.Inverter 1201 together forms half holding circuit 1202 with N lane device N3, maintains pre-clear input/output terminal PCLR current potential and be low level until return logic ' 1 ' estimation circuit 1101 current potential of this pre-clear input/output terminal PCLR is drawn high.P lane device P2 (corresponding N lane device N2 returning in logic ' 0 ' dominoes circuit 300) as shown in figure dotted line receives anti-phase reset signal RSTB with its grid, and couples node 1106 with drain electrode, and couples for electric potential VDD with source electrode.Pre-clear input/output terminal PCLR is initial is low level clearly in advance, therefore inverter 1201 is set output signal OUT, is high level, makes N lane device N3 conducting.Therefore N lane device N3 maintains pre-clear input/output terminal PCLR is low level.Because the initial condition of output signal OUT is high level, inverter 1203 can be set and return logic ' 1 ' enable signal RT1E be low level, makes P lane device P1 conducting, and the P lane device P1 of conducting will draw high reset signal RST.The initial state that therefore inverter 1205 drags down anti-phase reset signal RSTB and N lane device N2 is not conducting.

With reference to Figure 11 and Figure 12, the estimation event occurring while responding one or more input signal IN transition for any of one or more estimated state, return the level that logic ' 1 ' estimation circuit 1101 draws high pre-clear input/output terminal PCLR, cause and return logic ' 1 ' dominoes circuit 1200 transitions for its latch mode.Particularly, inverter 1201 can drag down output signal OUT and make not conducting of N lane device N3.Inverter 1203 draws high the level that returns logic ' 1 ' enable signal RT1E, makes N lane device N1 conducting, and makes not conducting of P lane device P1.The N lane device N1 of conducting can couple node 1110 to reference potential VSS.It is high level that the P lane device P1 of not conducting will no longer limit reset signal RST.The estimated state of input signal IN can cause returning logic ' 1 ' reset circuit 1103 transitions for its isolation, and node 1106 and 1110 is isolated from each other.Thus, replacement node 1106 is temporarily isolated, and reset signal RST is no longer limited in particular state.Yet owing to there is no other devices to attempt to change the state of reset signal RST, reset signal RST is maintained high level.When input signal IN is in an estimated state, return logic ' 1 ' reset circuit 1103 and maintain its isolation.

When being supplied to each reply of input signal IN of this recurrence logic ' 1 ' reset circuit 1103, it is its preset state, return logic ' 1 ' reset circuit 1103 transitions to its Reset Status, cause a resetting event, wherein, N lane device N1 and return logic ' 1 ' reset circuit 1103 and combine and move reset signal RST to low level.Inverter 1205 can be moved anti-phase reset signal RSTB to high level with conducting N lane device N2 thereupon.The N lane device N2 of conducting can be pulled down to preset value by the current potential of pre-clear input/output terminal PCLR.Please note, when being supplied to each input signal IN of this recurrence logic ' 1 ' reset circuit 1103 to revert to preset state, these input signals IN will be no longer estimated state, therefore, return logic ' 1 ' estimation circuit 1101 and no longer pre-clear input/output terminal PCLR will be pulled in to high level.Thus, N lane device N2 is able to again pre-clear input/output terminal PCLR be dragged down into pre-clear state.If pre-clear input/output terminal PCLR transition is high level, it is high level again that inverter 1201 can be set output signal OUT, makes N lane device N3 conducting, and maintaining pre-clear input/output terminal PCLR is low level.Inverter 1103 can drag down recurrence logic ' 1 ' enable signal RT1E, with conducting P lane device P1 and make not conducting of N lane device N1.Due to not conducting of N lane device N1, return logic ' 1 ' reset circuit 1103 and reference potential VSS isolation, no longer the level of reset signal RST is dragged down.In addition, the conducting meeting of P lane device P1 draws high high level by reset signal RST, and inverter 1105 can be moved anti-phase reset signal RSTB to low level, makes not conducting of N lane device N2.Although not conducting of N lane device N2, it is low level that half holding circuit 1202 can maintain pre-clear input/output terminal PCLR current potential.Thus, return logic ' 1 ' dominoes circuit 1200 its preset condition of resetting back, to prepare to meet estimation event next time.

Figure 13 describes the operation that returns logic ' 1 ' domino logic gate 1100 without clock with a sequential chart, what wherein return that logic ' 1 ' dominoes circuit 1105 adopt is a kind of execution mode that returns logic ' 1 ' dominoes circuit 1200.The sequential chart of Figure 13 is fundamentally similar with the sequential chart of Fig. 5, except the difference of minority signal name and the level adjustment (it is anti-phase) of circuit signal.Special instruction, compared to Fig. 5, Figure 13 replaces preliminary filling input/output signal PCHG with pre-clear input/output signal PCLR, to return logic ' 1 ' output signal OUT (RT1), replace recurrence logic ' 0 ' output signal OUT (RT0), and return logic ' 0 ' enable signal RT0E to return logic ' 1 ' enable signal RT1E replacement.Signal PCLR, OUT (RT1), RT1E, RST and the RSTB of Figure 13 is respectively the anti-phase of Fig. 5 signal PCHR, OUT (RT0), RT0E, RST and RSTB.In addition, the transition time has short delay substantially equally.Compare with Fig. 5, Figure 13 also comprises the waveform of the first status signal EVAL and the second status signal RESET, and response class seemingly.In this embodiment, the first status signal EVAL is used for indicating the estimated state that returns logic ' 1 ' estimation circuit 1101, is high level, and is low level when estimated state is set up when estimated state is false.The second status signal RESET is used for indicating the Reset Status that returns logic ' 1 ' reset circuit 1103, is high level, and when Reset Status is false, is low level when Reset Status is set up.Described Reset Status can cause a resetting event, occurs over just after an estimation event when this recurrence logic ' 1 ' enable signal RT1E is high level.

Figure 13 presents described signal EVAL, RESET, PCRL, OUT (RT1), RT1E, RST and RSTB with sequential chart.It is only signal purposes that the transition existing between each signal postpones, and not accurately shows actual state.With reference to initial time point T0, the initial condition of the first status signal EVAL is low level, shows that input signal IN is not in estimated state.In addition,, based on Fig. 5 institute content of the discussions, the second status signal RESET is meaningless in time point T0.At time point T0, signal PCLR, OUT (RT1), RT1E, RST and RSTB are initially set respectively logic ' 0 ', ' 1 ', ' 0 ', ' 1 ' and ' 0 '.

At the time point T1 continuing, input signal IN together enters estimated state, and causing the first status signal EVAL transition is high level, and the second status signal RESET transition is low level.Respond the high level state of the first status signal EVAL, return the time point T2 of logic ' 1 ' estimation circuit 1101 after a short delay and draw high pre-clear input/output terminal PCLR current potential, cause an estimation event.Because the second status signal RESET is low level, return logic ' 1 ' reset circuit 1103 in its isolation.Respond the signal transition of pre-clear input/output terminal PCLR to the action of high level, the connecting time point T3 of inverter 1201 after a short delay drags down the level of output signal OUT.Low level output signal OUT is drawn in response, and the connecting time point T4 of inverter 1203 after a short delay draws high the level that returns logic ' 1 ' enable signal RT1E, with conducting N lane device N1, and makes not conducting of P lane device P1.Owing to returning logic ' 1 ' reset circuit 1103, do not act on, reset signal RST is not affected by any device and maintains high level (or in having the execution mode of design P lane device P2, P2 maintains high level by P lane device).The state that returns logic ' 1 ' dominoes circuit 1200 without clock is constant for holding when the first status signal EVAL is high level.At the time point T5 continuing, one or more input signal IN change state, cause described estimated state to be false, and the corresponding transition of the first status signal EVAL are low level.If be supplied to return logic ' 1 ' reset circuit 1103 input signal IN each all reply as logic ' 1 ', the second status signal RESET is high level as the dotted line 501 time point T5 transition that is shown in.Yet about non-two configuration designs, the first status signal EVAL transition is that low level and the second status signal RESET transition are to have a delay between high level.Note that described estimated state is false because the first status signal EVAL is low level, therefore return the current potential that logic ' 1 ' estimation circuit 1101 no longer draws high pre-clear input/output terminal PCLR after time point T5.The current potential of pre-clear input/output terminal PCLR can maintain high level until N lane device N2 effect drags down its level.

At time point T5 or the time point T6 that continues, being supplied to the input signal IN transition that returns logic ' 1 ' reset circuit 1103 is high level, and to start to return the Reset Status of logic ' 1 ' reset circuit 1103, making the second status signal RESET transition is high level.Return logic ' 1 ' the reset circuit 1103 time point T7s of associating N lane device N1 after a short delay level of reset signal RST is dragged down, with an initial resetting event.Inverter 1205 is responded aforesaid operations, and the time point T8 after a short delay draws high the level of anti-phase reset signal RSTB.Transition is the anti-phase reset signal RSTB meeting conducting N lane device N2 of high level, and the time point T9 after a short delay drags down the level of pre-clear input/output terminal PCLR.When the level reduction of pre-clear input/output terminal PCLR, it is high level that the time point T10 of inverter 1201 after a short delay sets output signal OUT.Transition is that the output signal OUT of high level can make N lane device N3 conducting, and the current potential that causes half holding circuit 1202 to be maintained pre-clear input/output terminal PCLR is low level until its level is drawn high in estimation interval after a while.The time point T11 of inverter 1203 after a short delay drags down the level that returns logic ' 1 ' enable signal RT1E.Recurrence logic ' 1 ' the enable signal RT1E of low level state makes P lane device P1 conducting, and makes not conducting of N lane device N1.Due to not conducting of N lane device N1, return the level that logic ' 1 ' reset circuit 1103 no longer drags down reset signal RST.The time point T12 of the P lane device P1 of conducting after a short delay retracts high level by reset signal RST.The time point T13 of inverter 1205 after short delay drags down the level of anti-phase reset signal RSTB, makes N lane device N2 no longer drag down the level of pre-clear input/output terminal PCLR.Now, to be responsible for maintaining level of this pre-clear input/output terminal PCLR be low level to half holding circuit 1202.At the time point T14 following after time point T13, described signal is got back to initial preset state.Therefore, return logic ' 1 ' estimation circuit 1101 and N lane device N1 all in its preset state, return logic ' 1 ' dominoes circuit 1105 and return its preset condition, in addition, suppose that each is high level into signal IN, return logic ' 1 ' reset circuit 1103 in its Reset Status.Generally speaking, the estimated state of input signal IN can cause an estimation event, and causing output signal OUT transition is low level, and the resetting event that continues of activation.The Reset Status of input signal IN can cause and return logic ' 1 ' reset circuit 1103 initiation one resetting event, and makes to return logic ' 1 ' domino logic gate 1100 its initial conditions of recurrence without clock, to meet next estimation interval.

Content of the discussions as Fig. 5, the second status signal RESET is high level until time point T11-returns logic ' 1 ' enable signal RTE1 transition is low level-to guarantee that returning logic ' 1 ' gate without clock returns its initial condition, thereafter, the second status signal RESET as shown is meaningless.Please note, reset signal RST, when time point T7 is pulled to low level, drags down the second status signal RESET into low level if Reset Status is false, and reset signal RST still maintains low level, reason is that P lane device P1 is still not conducting, the unable reset signal RST that affects.Therefore, although should maintaining, sets up until ' 1 ' the enable signal RT1E transition of recurrence logic is low level Reset Status, if but input signal moves in this way after time point T7 and time point T11 drags down the second status signal RESET before, still can not affect correct circuit operation.Once returning logic ' 1 ' enable signal RT1E is low level, P lane device P1 conducting, and any insignificant transition of input signal IN can not affect integrated circuit state after time point T11.

Figure 14 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate 1400 without clock, for realizing a logic OR computing, M input signal I1...IM is done to logic OR computing.Without clock, return logic ' 1 ' domino logic gate 1400 and comprise recurrence logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples recurrence logic ' 1 ' estimation circuit 1401 (being used for realizing aforementioned recurrence logic ' 1 ' estimation circuit 1101) and and returns logic ' 1 ' reset circuit 1403 (being used for realizing aforementioned recurrence logic ' 1 ' reset circuit 1103).Return logic ' 1 ' estimation circuit 1401 and comprise M P lane device PA...PM, with drain electrode, couple node 1102 separately, and with source electrode, couple for electric potential VDD separately.P lane device PA...PM provide a grid separately, with receive input signal I1...IM one of them.In similar fashion, return logic ' 1 ' reset circuit 1403 and comprise M N lane device NA...NM, be serially connected with between node 1110 and replacement node 1106.As shown in the figure, the N lane device NA of the first order couples the node 1110 in the drain electrode of N lane device N1 with source electrode, and with drain electrode, couples the source electrode of next stage N lane device; Follow described rule until the N lane device NM of afterbody.The drain electrode of afterbody N lane device NM couples node 1106.N lane device NA...NM provide a grid separately, with mode as shown in the figure receive input signal I1...IM one of them.Although only indicate wherein two device (NA of described N lane device in figure, NM), wherein two device (PA of P lane device, PM) and only show input signal I1 and IM, in fact, according to disclosed rule, omit the part of drawing and can comprise any amount of described device and coherent signal (for example, being supplied to the input signal I2 of the grid of N passage and P lane device NB and PB).

Without clock, returning logic ' 1 ' domino logic gate 1400 is a kind of two configuration design, wherein, returns logic ' 1 ' reset circuit 1403 for returning two configuration designs of logic ' 1 ' estimation circuit 1401.In addition,, in two configurations design, being supplied to what return logic ' 1 ' estimation circuit 1401 and recurrence logic ' 1 ' reset circuit 1403 is all identical input signal I1...IM.The operation that returns logic ' 1 ' domino logic gate 1400 without clock meets the sequential shown in Figure 13 conventionally.In this embodiment, when input signal I1...IM is according to the operation that returns logic ' 1 ' during all in logic ' 1 ', the first status signal EVAL is low level, and the second status signal RESET is high level.When in input signal I1...IM, any transition is low level, estimated state is set up, and Reset Status is false, therefore the first status signal EVAL is that high level and the second status signal RESET are low level.Because circuit 1401 and 1403 is two configuration designs, along with the transition of input signal IN is switched, the state of the first status signal EVAL and the second status signal RESET and then switches, and is maintained the anti-phase of the other side.Respond the estimation event that in input signal IN, the low level transition of any causes, pre-clear input/output terminal PCLR transition is high level, and output signal OUT transition after short delay is low level, and ' 1 ' the enable signal RT1E transition after another section of short delay of recurrence logic is that high level is with activation one resetting event.When input signal I1...IM returns logic ' 1 ' according to returning logic ' 1 ' operation transition totally, return logic ' 1 ' reset circuit 1403 and cause a resetting event, making reset signal RST transition is low level, anti-phase reset signal RSTB transition is high level, the level of pre-clear input/output terminal PCLR retracts low level, and output signal OUT draws high back high level as aforementioned content.

In some design, the quantity that is serially connected in the N lane device in recurrence logic ' 1 ' reset circuit 1403 may need to be limited in below specified quantitative, to guarantee circuit normal operation.For example, in one embodiment, the transformation that is serially connected in the N lane device of 1106 of reference potential VSS and replacement nodes is 4, and therefore, the quantity of input signal can be restricted to 3 (being that M is 3).With reference to figure 7, gate 701,703 and 705 can return logic ' 1 ' logic sum gate by one respectively and realize, and what each gate adopted is to return logic ' 1 ' domino logic gate 1400 technology without clock.In this embodiment, gate 701 is designed to a logic sum gate, to returning logic ' 1 ' input signal I1...I3, carries out logic OR computing, to supply, returns logic ' 1 ' signal O1.Gate 703 is designed to recurrence logic ' 1 ' logic sum gate, carries out logic OR computing, to supply recurrence logic ' 1 ' signal O2 to returning logic ' 1 ' input signal I4...I6.Gate 705 is designed to recurrence logic ' 1 ' logic sum gate, and signal O1 and O2 are carried out to logic OR computing, to be supplied as the output signal OUT that returns logic ' 1 ' signal.Thus, a plurality of without clock return logic ' 1 ' domino logic gate can be combined or string stack togather with recurrence logic ' 1 ' input signal to a large amount of and carry out specific logical operation, for example, logic OR computing.

Figure 15 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate 1500 without clock, wherein according to another execution mode, realizes diversified logical operation.Without clock, return logic ' 1 ' domino logic gate 1500 and comprise recurrence logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples and returns logic ' 1 ' estimation circuit 1501 (returning logic ' 1 ' estimation circuit 1101 in order to realize) and recurrence logic ' 1 ' reset circuit 1503 (returning logic ' 1 ' reset circuit 1103 in order to realize).The design that returns logic ' 1 ' domino logic gate 1500 without clock is substantially identical without clock recurrence logic ' 0 ' domino logic gate 800, and difference is the anti-phase design of specially doing returning logic ' 1 '.It is described, compared to gate 800, gate 1500 replaces reference potential VSS for electric potential VDD, with reference potential VSS, replace for electric potential VDD, with N lane device, replace P lane device, with P lane device, replace N lane device, make input signal I4 and I5 adopt and return logic ' 1 ' mode of operation but not recurrence logic ' 0 ' mode of operation, by the anti-phase design of signal condition, and make input signal I1...I3 for returning logic ' 1 ' or non-recurrence logic ' 1 ' signal.Aforementioned nodes 302,304,306,308 and 310 replaces with similar node 1102,1104,1106,1108 and 1110 respectively, in the mode of similar 11...14 figure, realizes similar computing.The operation that returns logic ' 1 ' domino logic gate 1500 without clock generally meets the disclosed sequential chart of Figure 13.Without clock, return logic ' 1 ' domino logic gate 1500 and carry out a logical operation OUT=～((～I1|～I2|～I3) & (～I4|～I5)), wherein, what symbol "～" represented is logical inversion.

Similar to clock recurrence logic ' 0 ' domino logic gate 800, without clock, return another execution mode that logic ' 1 ' domino logic gate 1500 is non-two configuration designs, wherein, return two configuration designs that logic ' 1 ' reset circuit 1503 not returns logic ' 1 ' estimation circuit 1501.In input signal I1...I5, only there are one subclass-input signal I4 and I5-to be supplied to and return logic ' 1 ' reset circuit 1503.While setting up due to estimated state input signal I4 and I5 one of them must be low level, therefore return logic ' 1 ' reset circuit 1503, be its isolation.As long as returning logic ' 1 ' estimation circuit 1501 is estimated state, returning logic ' 1 ' reset circuit 1503 must the aforementioned manner normal running to guarantee to return logic ' 0 ' domino logic gate 800 without clock with similar in its isolation.In addition, without clock, returning logic ' 1 ' domino logic gate 1500 can adopt the technology that is similar to associating gate design 700 to realize a string repeatedly gate.In one embodiment, the 3rd N lane device (do not show in the drawings) makes an addition to string between node 1110 and 1106 and changes in device, makes three strings N lane device reception input signal I1, I2 and I3 repeatedly.What above-mentioned correction realized is equivalent logical operation, but, about this, return logic ' 1 ' dominoes circuit 1105 and return the spent time of preset condition from latch mode transition, the situation of three input signals (I1...I3) can be consuming time compared with the situation of two input signals (I4 and I5).

Figure 16 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate 1600 without clock, is a logical AND gate, returns logic ' 1 ' input signal I1...IM carry out logic and operation to M.Without clock, return logic ' 1 ' domino logic gate 1600 and comprise recurrence logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples recurrence logic ' 1 ' estimation circuit 1601 (for realizing aforementioned recurrence logic ' 1 ' estimation circuit 1101) and and returns logic ' 1 ' reset circuit 1603 (for realizing aforementioned recurrence logic ' 1 ' reset circuit 1103).The design that returns logic ' 1 ' domino logic gate 1600 without clock is substantially similar without clock recurrence logic ' 0 ' domino logic gate 900, and difference is that domino logic gate 1600 is distortion of having done according to returning logic ' 1 ' operation.Be noted that, compare with domino logic gate 900, domino logic gate 1600 replaces reference potential VSS for electric potential VDD, and replace for electric potential VDD with reference potential VSS, with N lane device, replace P lane device, with P lane device, replace N lane device, make input signal I1...I5 adopt and return logic ' 1 ' design but not ' 0 ' design of recurrence logic, make output signal OUT for returning logic ' 1 ' design but not return logic ' 0 ' design, and to make signal condition be anti-phase design.Node 302,304,306,308 and 310 can be replaced by similar node 1102,1104,1106,1108 and 1110 respectively, the equal computing of being discussed to be implemented in 11...14 figure.

Without clock, return another execution mode that logic ' 1 ' domino logic gate 1600 is two configuration designs.The operation that returns logic ' 1 ' domino logic gate 1600 without clock generally meets sequential chart shown in Figure 13.In this embodiment, estimated state is only set as low level at input signal I1...IM totally and sets up, and makes the total conducting of P lane device PA...PM, makes a concerted effort the level of pre-clear input/output terminal PCLR to move to for electric potential VDD.When Reset Status can in input signal I1...IM, any be for high level, set up.In such execution mode, returning logic ' 1 ' estimation and reset circuit 1601 and 1603 is two configuration designs each other.According to various demands, designed circuit can be accepted the input signal of requirement.With reference to returning the previous discussion of logic ' 1 ' domino logic gate 1400 without clock, similarly, the quantity that is serially connected in the P lane device in recurrence logic ' 1 ' estimation circuit 1601 may need to be limited in specific quantity, to guarantee circuit normal running.Consult Fig. 7, gate 701,703 and 705 can adopt recurrence logic ' 1 ' logical AND gate realization that returns logic ' 1 ' domino logic gate 1600 technology without clock separately.Thus, can by several without clock return logic ' 1 ' domino logic gate in conjunction with or string stack togather, with the input signal to a large amount of, carry out the logic and operation of specific logical operation-for example.

Figure 17 is a block schematic diagram, and diagram one returns logic ' 1 ' domino logic gate 1700 without clock, is a logical AND gate, and M input signal I1...IM carried out to logic and operation, wherein adopts the reset circuit 1703 of simplifying.Without clock, return logic ' 1 ' domino logic gate 1700 substantially similar without clock recurrence logic ' 1 ' domino logic gate 1600, wherein, same element adopts same numbering, and return logic ' 1 ' reset circuit 1603, changes by returning logic ' 1 ' reset circuit 1703 replacements.Without clock, return logic ' 1 ' domino logic gate 1700 and generally meet sequential chart shown in Figure 13.Return logic ' 1 ' reset circuit 1703 and only have a N lane device NA, the drain electrode that couples N lane device N1 with source electrode is in node 1110, and couples replacement node 1106 with drain electrode.Input signal I1...IM wherein any-be generally denoted as IX-will be supplied to the grid of N lane device NA.

Without clock, return the computing of logic ' 1 ' domino logic gate 1700 and return logic ' 0 ' domino logic gate 1600 equivalences without clock, difference is that domino logic gate 1700 is non-two configuration design execution modes.The operation that returns logic ' 1 ' domino logic gate 1700 without clock is substantially similar without clock recurrence logic ' 1 ' domino logic gate 1600, and it is only that high level is just set up at input signal IX that difference is in Reset Status.When input signal I1...IM-comprise input signal IX-each all transition be low level, Reset Status is false, and estimation event occurs.When input signal IX transition is logic ' 0 ', estimated state is false, and Reset Status establishment, causes a resetting event and makes to return logic ' 1 ' dominoes circuit 1105 its preset condition of recurrence without clock.The advantage that returns logic ' 1 ' domino logic gate 1700 without clock is that it returns logic ' 1 ' reset circuit and simplifies, only there is a N lane device to be contained in wherein, yet, slow compared with other input signals if the speed of logic ' 1 ' is returned in input signal IX transition, have reaction speed problem.The advantage that returns logic ' 1 ' domino logic gate 1600 without clock is possible there is reaction speed faster, after reason is estimation event, once having any transition in input signal is logic ' 1 ', can cause resetting event, cost is that the design meeting of recurrence logic ' 1 ' reset circuit is more complicated.The speed issue of domino logic gate 1700 can be avoided by following mode: making in input signal IN, can the quickest transition be that the input signal of logic ' 1 ' is described input signal IX.

Review returns logic ' 1 ' domino logic gate 1100 without clock, order wherein adopts recurrence logic ' 1 ' the dominoes circuit 1200 according to Figure 13 sequential chart operation, without clock return logic ' 1 ' domino logic gate 1100 input signal when returning logic ' 1 ' operation in (or transition to) logic ' 1 ' in (or transition to) initial preset state.When input signal makes estimated state, set up, Reset Status is false and an estimation event is initiated.When estimated state is set up, Reset Status maintains is false.After estimated state is set up, if while being supplied to the input signal transition of reset circuit to return its logic of propositions ' 1 ' state, Reset Status is set up.Reset and finally according to returning logic ' 1 ' operation, occur.Take that without clock, to return logic ' 1 ' domino logic gate 1400 be example, resetting event betides the equal transition of each input signal I1...IM while returning logic ' 1 '.Take that without clock, to return logic ' 1 ' domino logic gate 1500 be example, resetting event betides one subclass-input signal I4 of input signal I1...I5 and I5-transition while being logic ' 1 '.Take that without clock, to return logic ' 1 ' domino logic gate 1600 be example, resetting event betides in input signal I1...IM any transition while returning logic ' 1 '.Take that without clock, to return logic ' 1 ' domino logic gate 1700 be example, resetting event betides this signal of selecting in input signal-be referred to as input signal IX-transition while being logic ' 1 '.

Although several preferred implementations of the present invention are below described in detail in detail as possible, still may have other execution modes or distortion to exist.For example, foregoing circuit can anyly comprise that other suitable scheme of logic device or circuit and so on realize.Any amount of computing of the logical circuit of introducing can be realized by similar techniques in software or firmware or integrating device.Described circuit can comprise anti-phase device, to carry out positive or inverted logic or other technology that signal can be reversed.The circuit computing that disclosed technology adopts can be numeral, binary bit byte or character, and those skilled in the art know, about numeral or the binary circuit application of any bit quantity.Those skilled in the art perhaps can be take the disclosed concept of foregoing and embodiment as basis, design or adjust all the other structures, under the prerequisite without prejudice to spirit of the present invention, according to the defined scope of following claims, realize the effect identical with the present invention.

Claims (40)

1. without a clock-state regression domino logic gate, comprising:

A plurality of nodes, be designed to separately switch at one first state and one second state, comprising a plurality of input nodes, a preset node, an output node, an activation node and one first and one second replacement node, wherein, above-mentioned a plurality of input node comprises that a state returns node separately, after being set as above-mentioned the first state, according to state, returning operation and return above-mentioned the second state;

One dominoes circuit, there is a preset condition and a latch mode, when this dominoes circuit is during in this preset condition, this dominoes circuit is set this preset node and this activation node to above-mentioned the first state, and set this output node and the first replacement node to above-mentioned the second state, when this preset node is by transition during to this second state, this dominoes circuit switches to this latch mode, make this output node transition to above-mentioned the first state and this activation node of transition to above-mentioned the second state, when this first replacement node by transition when above-mentioned the first state, this dominoes circuit this preset condition of resetting back,

One estimation circuit, at described input node during in any of at least one estimated state, this preset node of transition is to above-mentioned the second state, and when this input node is not above-mentioned estimated state, do not interfere the level of this preset node;

One enable circuit, this activation node during in this second state this second replacement node of transition to above-mentioned the first state, otherwise, do not interfere the level of this second replacement node; And

One replacement current potential, when input signal is not any of above-mentioned at least one estimated state, couple this first replacement node and this second replacement node, and in this input signal, be above-mentioned at least one estimated state any time this first replacement node is isolated to this second replacement node.

2. as claimed in claim 1 without clock-state regression domino logic gate, wherein estimation circuit and reset circuit are two configuration designs each other.

3. as claimed in claim 1 without clock-state regression domino logic gate, wherein estimation circuit is carried out logic OR computing to above-mentioned a plurality of input nodes.

4. as claimed in claim 1 without clock-state regression domino logic gate, wherein this estimation circuit is carried out logic and operation to above-mentioned a plurality of input nodes.

5. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' nodes, wherein, above-mentioned a plurality of input node is designed to switch at logic ' 0 ' state and logic ' 1 ' state separately, and above-mentioned each leisure of a plurality of input signal be set to logic ' 1 ' after transition return logic ' 0 ';

This preset node comprises a precharged node, and this dominoes circuit comprises recurrence logic ' 0 ' dominoes circuit;

When this dominoes circuit is this preset condition, this dominoes circuit set this precharged node and this activation node to logic ' 1 ' and set this output node and this first replacement node to logic ' 0 ', when this dominoes circuit is this latch mode, this this output node of dominoes circuit transition is that logic ' 1 ' and this activation node of transition are logic ' 0 ', when this first replacement node transition is to logic during ' 1, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes be above-mentioned at least one estimated state any one time, this this precharged node of estimation circuit transition is to logic ' 0 ', when above-mentioned a plurality of input nodes are not any one of above-mentioned at least one estimated state, this estimation circuit does not affect this preset node; And

When this activation node is logic ' 0, this second replacement node of this enable circuit transition is to logic ' 1 ', otherwise this enable circuit does not affect this second replacement node.

6. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' nodes, has separately logic ' 1 ' state and logic ' 0 ' state, and wherein, above-mentioned a plurality of each leisures of input node are set as returning as logic ' 1 ' after logic ' 0 ';

This preset node comprises a pre-clear node, and this dominoes circuit comprises recurrence logic ' 1 ' dominoes circuit;

When this dominoes circuit is during in this preset condition, this dominoes circuit set this pre-clear node and this activation node to logic ' 0 ' and set this output node and this first replacement node to logic ' 1 ', when this dominoes circuit is during in this latch mode, this this output node of dominoes circuit transition is to logic ' 0 ' and this activation node of transition to logic ' 1 ', when this first replacement node transition is logic ' 0 ', this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes form any of above-mentioned at least one estimated state, this pre-clear node of this estimation circuit transition is to logic ' 1 ', and when above-mentioned a plurality of input nodes do not form any of above-mentioned at least one estimated state, this estimation circuit does not affect this preset node; And

When this activation node is logic ' 1 ', this second replacement node of this enable circuit transition is to logic ' 0 ', otherwise this enable circuit does not affect this second replacement node.

7. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

Default node comprises a precharged node;

This estimation circuit comprises a plurality of N lane devices, couples this precharged node, with source electrode, couples a reference potential and couple input node corresponding in above-mentioned a plurality of input node with grid separately with drain electrode;

This enable circuit comprises one the one P lane device, with source electrode, couples for electric potential, couples this second replacement node, and couple this activation node with grid to drain; And

Reset circuit comprises a plurality of the 2nd P lane devices, is serially connected with between this first and second replacement node, couples input node corresponding in above-mentioned a plurality of input node separately with grid.

8. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

This preset node comprises a precharged node;

This estimation circuit comprises a plurality of N lane devices, is serially connected with between this precharged node and reference potential, couples input node corresponding in above-mentioned a plurality of input node separately with grid;

This enable circuit comprises one the one P lane device, with source electrode, couples power supply potential, couples this second replacement node to drain, and couples this activation node with grid; And

Reset circuit comprises a plurality of the 2nd P lane devices, couples this second replacement node, couples this first replacement node to drain and couples input node corresponding in above-mentioned a plurality of input node with grid separately with source electrode.

9. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

This preset node comprises a precharged node;

This estimation circuit comprises a plurality of N lane devices, is serially connected with between this precharged node and reference potential, couples input node corresponding in above-mentioned a plurality of input node separately with grid;

This activation node comprises one the one P lane device, with source electrode, couples for electric potential, couples this second replacement node, and couple this activation node with grid to drain; And

Reset circuit comprises one the 2nd P lane device, with source electrode, couples this second replacement node, couples this first replacement node to drain, and couples one of them input node of above-mentioned a plurality of input node with grid.

10. as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

This preset node comprises a pre-clear node;

This estimation circuit comprises a plurality of P lane devices, couples this pre-clear node, with source electrode, couples for electric potential and with grid and couple input node corresponding in above-mentioned a plurality of input node separately with drain electrode;

This enable circuit comprises one the one N lane device, with source electrode, couples reference potential, couples this second replacement node to drain, and couples this activation node with grid; And

Reset circuit comprises a plurality of the 2nd N lane devices, is serially connected with between this first and second replacement node, couples input node corresponding in above-mentioned a plurality of input node separately with grid.

11. is as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

Default node comprises a pre-clear node;

This estimation circuit comprises a plurality of P lane devices, is serially connected with this pre-clear node and between electric potential, couples input node corresponding in above-mentioned a plurality of input node separately with grid;

This enable circuit comprises one the one N lane device, with source electrode, couples reference potential, couples this second replacement node to drain, and couples this activation node with grid; And

Reset circuit comprises a plurality of the 2nd N lane devices, couples this second replacement node separately with source electrode, couples this first replacement node to drain, and couples input node corresponding in above-mentioned a plurality of input node with grid.

12. is as claimed in claim 1 without clock-state regression domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

Default node comprises a pre-clear node;

This estimation circuit comprises a plurality of P lane devices, is serially connected with this pre-clear node and between electric potential, couples input node corresponding in above-mentioned a plurality of input node separately with grid;

This enable circuit comprises one the one N lane device, with source electrode, couples reference potential, couples this second replacement node to drain, and couples this activation node with grid; And

This replacement current potential comprises one the 2nd N lane device, with source electrode, couples this second replacement node, couples this first replacement node to drain, and with grid, couples one of them input node of above-mentioned a plurality of input nodes.

13. 1 kinds of integrated circuits, comprising:

One first logic, supply a plurality of states and return signal, each above-mentioned state returns Design of Signal and switches at one first state and one second state, above-mentioned a plurality of state returns signal, and each can, after being set as above-mentioned the first state, returning operation according to state and be set as above-mentioned the second state by this first logic;

One without clock-state regression domino logic gate, receive above-mentioned a plurality of state and return signal, and this comprises without clock-state regression domino logic gate:

One preset node, an activation node, an output node and one first and one second replacement node, be designed to switch at above-mentioned first and second state separately;

One dominoes circuit, there is a preset condition and a latch mode, wherein, when this dominoes circuit is during in this preset condition, this dominoes circuit is set this preset node and this activation node to above-mentioned the first state, and set this output node and the first replacement node to above-mentioned the second state, when this preset node is by transition during to this second state, this dominoes circuit switches to this latch mode, make this output node transition to above-mentioned the first state, and this activation node of transition is to above-mentioned the second state, when this first replacement node transition is when above-mentioned the first state, this dominoes circuit this preset condition of resetting back,

One estimation circuit, above-mentioned a plurality of states return signals be at least one estimated state any time, this preset node of transition is to above-mentioned the second state, and in above-mentioned a plurality of states return signals be not in above-mentioned at least one estimated state any time, do not affect this preset node;

One enable circuit, when this activation node is above-mentioned the second state, this second replacement node of transition is above-mentioned the first state extremely, otherwise, do not affect this second replacement node; And

One reset circuit, when above-mentioned a plurality of states recurrence signals are not any of above-mentioned at least one estimated state, couple this first replacement node to this second replacement node, and when above-mentioned a plurality of states return any that signal is above-mentioned at least one estimated state, this first replacement node is isolated to this second replacement node.

14. integrated circuits as claimed in claim 13, wherein this first logic is supplied a plurality of recurrence logic ' 0 ' signals, above-mentioned the first state is that logic ' 1 ' and above-mentioned the second state are logic ' 0 ', and this comprises that without clock-state regression domino logic gate one returns logic ' 0 ' domino logic gate without clock.

15. integrated circuits as claimed in claim 13, wherein this first logic is supplied a plurality of persistent state ' 1 ' signals, above-mentioned the first state is that logic ' 0 ' and above-mentioned the second state are logic ' 1 ', and this comprises that without clock-state regression domino logic gate one returns logic ' 1 ' domino logic gate without clock.

16. integrated circuits as claimed in claim 13, wherein this comprises that without clock-state regression domino logic gate string stacks a plurality of without clock-state regression domino logic gate of meter.

The method of 17. 1 kinds of estimation one logical operations, comprising:

Receive a plurality of states and return input signal, described state returns input signal and is designed to separately according to state, return operation recurrence one second state after setting one first state for;

Supply has a dominoes circuit of a preset condition and a latch mode, when this dominoes circuit is this preset condition, this dominoes circuit sets a preset node and an activation node is above-mentioned the first state, and setting an output node and a replacement node is above-mentioned the second state, this preset node by transition when above-mentioned the second state, this dominoes circuit switches to this this output node of latch mode transition to above-mentioned the first state and this activation node of transition to above-mentioned the second state, when this replacement node transition is when above-mentioned the first state, this dominoes circuit this preset condition of resetting back,

Estimate that above-mentioned a plurality of state returns input signal, wherein in above-mentioned a plurality of states return input signals be at least one estimated state any time transition this preset node above-mentioned the second state extremely, to switch this dominoes circuit to this latch mode; And

Enable signal be above-mentioned the second state and above-mentioned a plurality of state return input signal in above-mentioned a plurality of estimated state any time, this replacement node of transition is to this first state, with this dominoes circuit of resetting to this preset condition.

18. methods as claimed in claim 17, wherein, with this activation node of transition, the step to this second state comprises for this latch mode while presetting node transition to above-mentioned the second state, to switch this dominoes circuit:

One replacement condition of this dominoes circuit of activation.

19. methods as claimed in claim 17, the step that wherein the above-mentioned a plurality of states of above-mentioned estimation return input signals comprise carry out a logic OR computing when returning in above-mentioned a plurality of states in input signals that at least one transition is to above-mentioned the first state this preset node of transition to above-mentioned the second state, and wherein the method for this dominoes circuit of above-mentioned replacement be included in this activation node when this second state and above-mentioned a plurality of state return input signal and are above-mentioned the second state this replacement node of transition to this first state.

20. methods as claimed in claim 17, the step that wherein the above-mentioned a plurality of states of above-mentioned estimation return input signals comprise carry out a logic and operation with this preset node of transition when above-mentioned a plurality of states return the total transition of input signal to above-mentioned the first state to above-mentioned the second state, and wherein the step of this dominoes circuit of above-mentioned replacement to be included in this activation node be that above-mentioned the second state and above-mentioned a plurality of state return in input signal when at least one input signal returns above-mentioned the second state this replacement node of transition to this first state.

21. 1 kinds return gate without clock status, comprising:

A plurality of nodes, switch on separately one first state and one second state, comprising a plurality of input nodes, a preset node, an output node, an activation node and one first and one second replacement node, in above-mentioned a plurality of input node, at least one comprises that a state returns node, returns operation transition return above-mentioned the second state after setting above-mentioned the first state for according to state;

One dominoes circuit, there is a preset condition and a latch mode, when this dominoes circuit is this preset condition, this dominoes circuit sets this preset node and this activation node is above-mentioned the first state, and setting this output node and the first replacement node is above-mentioned the second state, when this preset node transition is above-mentioned the second state, this dominoes circuit is switched to this latch mode, take this output node of transition as above-mentioned the first state, and this activation node of transition is above-mentioned the first state, when above-mentioned the first state is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back,

One estimation circuit, at above-mentioned a plurality of input nodes, be at least one estimated state any time, this preset node of transition is above-mentioned the second state, and when above-mentioned a plurality of input nodes are not any of above-mentioned at least one estimated state, does not affect this preset node;

One enable circuit, when this activation node is above-mentioned the second state, this second replacement node of transition is above-mentioned the first state, and does not affect this second replacement node when this activation node is not above-mentioned the second state; And

One reset circuit, above-mentioned a plurality of input nodes for above-mentioned at least one estimated state any time couple this first replacement node to this second replacement node, and in above-mentioned a plurality of input nodes be above-mentioned at least one estimated state any time this first replacement node is isolated to this second replacement node.

22. is as claimed in claim 21 without clock status recurrence gate, and wherein this estimation circuit and this reset circuit are non-two configuration design each other.

23. is as claimed in claim 21 without clock status recurrence gate, wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes, this subclass comprises at least one, but non-total above-mentioned input node, the input node that belongs to this subclass comprises that a state returns node separately, above-mentioned at least one estimated state each only in this subclass of above-mentioned a plurality of input nodes, at least one occurs when above-mentioned the second state transition, and this dominoes circuit this preset condition of only resetting back when this subclass of above-mentioned a plurality of input nodes is above-mentioned the second state totally.

24. is as claimed in claim 21 without clock status recurrence gate, wherein:

Above-mentioned a plurality of input node comprises that at least one returns logic ' 0 ' node, each is designed to above-mentioned at least one recurrence logic ' 0 ' node switch at logic ' 0 ' state and logic ' 1 ' state, and above-mentioned at least one each leisure of recurrence logic ' 0 ' node is set as logic, and logic ' 0 ' is returned in the rear transition in ' 1;

This preset node comprises a precharged node, and this dominoes circuit comprises recurrence logic ' 0 ' dominoes circuit;

When this dominoes circuit is this preset condition, this dominoes circuit set this precharged node and this activation node to logic ' 1 ' and set this output node and this first replacement node to logic ' 0 ', when this dominoes circuit is this latch mode, this this output node of dominoes circuit transition to logic ' 1 ' and this activation node of transition is logic ' 0 ', and, when logic ' 1 ' is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any time, this this precharged node of estimation circuit transition is to logic ' 0 ', when above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any time, this estimation circuit does not affect this preset node; And

When this activation node is logic ' 0 ', this second replacement node of this enable circuit transition is to logic ' 1 ', and when this activation node is not logic ' 0 ', this enable circuit does not affect this second replacement node.

25. is as claimed in claim 24 without clock status recurrence gate, wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes, this subclass comprises at least one but non-total above-mentioned input node, each comprises recurrence logic ' 0 ' node input node in this subclass of above-mentioned a plurality of input nodes, above-mentioned at least one estimated state each when occurring over just at least one input node in above-mentioned a plurality of this subclass of input node and switching to logic ' 1 ' by logic ' 0 ', and this dominoes circuit this preset condition of resetting back when only all input nodes in this subclass of above-mentioned a plurality of input nodes are logic ' 0 '.

26. is as claimed in claim 21 without clock status recurrence gate, wherein:

Above-mentioned a plurality of input node comprises that at least one returns logic ' 1 ' node, each is designed to above-mentioned at least one recurrence logic ' 1 ' node switch between logic ' 1 ' state and logic ' 0 ' state, and each returns logic ' 1 ' above-mentioned at least one recurrence logic ' 1 ' node after being set as logic ' 0 ';

This preset node comprises a pre-clear node, and this dominoes circuit comprises recurrence logic ' 1 ' dominoes circuit;

When this dominoes circuit is this preset condition, this dominoes circuit is set this pre-clear node and this activation node to be logic ' 0 ' and to set this output node and this first replacement node is logic ' 1 ', when dominoes circuit is this latch mode, this this output node of dominoes circuit transition is that logic ' 0 ' and this activation node of transition are logic ' 1 ', when logic ' 0 ' is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any time, this pre-clear node of this estimation circuit transition is logic ' 1 ', and when above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any time, this estimation circuit does not affect this preset node; And

When this activation node is logic ' 1 ', this second replacement node of this enable circuit transition is logic ' 0 ', and when this activation node is not logic ' 1 ', this enable circuit does not affect this second replacement node.

27. is as claimed in claim 26 without clock status recurrence gate, wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes, this subclass comprises at least one but non-whole above-mentioned input node, each comprises recurrence logic ' 1 ' node input node in this subclass of above-mentioned a plurality of input nodes, each only betides above-mentioned at least one estimated state and in this subclass of above-mentioned a plurality of input nodes, has an input node at least when logic ' 1 ' transition is logic ' 0 ', and this dominoes circuit this preset condition of resetting back when only total input node is logic ' 0 ' in this subclass of above-mentioned a plurality of input nodes.

28. is as claimed in claim 21 without clock status recurrence gate, wherein:

In above-mentioned a plurality of input node, at least one comprises recurrence logic ' 0 ' input node;

This preset node comprises a pre-clear node; And

This dominoes circuit comprises:

One first inverter, has an input and couples precharged node and have an output and couple this output node;

One the one P lane device, has a grid and couples this output node, has one source pole and couples one for electric potential, and have a drain electrode and couple this precharged node;

One second inverter, has an input and couples this output node, and has an output and couple this activation node;

One the one N lane device, has one source pole and couples a reference potential, and a grid couples this activation node, and a drain electrode couples this replacement node;

One the 3rd inverter, has an input and couples this replacement node, and have an output; And

One the 2nd P lane device, has one source pole and couples this confession electric potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this precharged node.

29. is as claimed in claim 28 without clock status recurrence gate, and wherein this estimation circuit comprises a plurality of the 2nd N lane devices, and this reset circuit comprises at least one the 3rd P lane device.

30. is as claimed in claim 21 without clock status recurrence gate, wherein:

In above-mentioned a plurality of input node, at least one comprises recurrence logic ' 1 ' input node;

This preset node comprises a pre-clear node; And

This dominoes circuit comprises:

One the 5th inverter, has an input and couples this pre-clear node, and has an output and couple this output node;

One the one N lane device, has a grid and couples this output node, has one source pole and couples a reference potential, and have a drain electrode and couple this pre-clear node;

One second inverter, has an input and couples this output node, and has an output and couple this activation node;

One the one P lane device, has one source pole and couples one for electric potential, and a grid couples this activation node, and a drain electrode couples this replacement node;

One the 3rd inverter, has an input and couples this replacement node, and have an output; And

One the 2nd N lane device, has one source pole and couples this reference potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this pre-clear node.

31. is as claimed in claim 30 without clock status recurrence gate, and wherein this estimation circuit comprises a plurality of the 2nd P lane devices, and this reset circuit comprises at least one the 3rd N lane device.

32. 1 kinds of integrated circuits, comprising:

One first logic, supply at least one state and return signal, wherein above-mentioned at least one state returns Design of Signal and switches at one first state and one second state, and this first logic can return and operate in above-mentioned at least one state to return signal sets be it setting to be returned to above-mentioned the first state after above-mentioned the first state according to state; And

One without clock-state regression domino logic gate, has a plurality of input nodes and receives above-mentioned at least one state recurrence signal, and this comprises without clock-state regression domino logic gate:

One preset node, an activation node, an output node and first and second replacement node, design separately at above-mentioned first and second state and switch;

One dominoes circuit, there is a preset condition and a latch mode, wherein, when this dominoes circuit is this preset condition, this dominoes circuit sets this preset node and this activation node is above-mentioned the first state, and setting this output node and the first replacement node is above-mentioned the second state, when this preset node transition is this second state, this dominoes circuit switches to this latch mode, with this output node of transition to above-mentioned the first state, and this activation node of transition is to above-mentioned the second state, when this first state is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back,

One estimation circuit, above-mentioned a plurality of input nodes be at least one estimated state any time, this preset node of transition is to above-mentioned the second state, and in above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any time, do not affect this preset node;

One enable circuit, when this activation node is this second state, this second replacement node of transition, to this first state, and does not affect this second replacement node when this second state in this activation node; And

One reset circuit, above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any time, couple this first replacement node to this second replacement node, and in above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any time, this first replacement node is isolated to this second replacement node.

33. integrated circuits as claimed in claim 32, wherein this estimation circuit and this reset circuit are non-two configuration design each other.

34. integrated circuits as claimed in claim 32, wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes, this subclass comprises at least one but non-whole above-mentioned input node, each is state recurrence node for input node in this subclass of above-mentioned a plurality of input nodes, each occurs over just at least one input node in this subclass of above-mentioned a plurality of input nodes when above-mentioned the second state transition above-mentioned a plurality of estimated state, and this preset condition of resetting back when the input node of this dominoes circuit in this subclass of above-mentioned a plurality of input nodes is above-mentioned the second state totally.

35. integrated circuits as claimed in claim 34, wherein this first logic is supplied at least one and is returned logic ' 0 ' signal, above-mentioned the first state is that logic ' 1 ' and above-mentioned the second state are logic ' 0 ', this comprises that without clock-state regression domino logic gate one returns logic ' 0 ' domino logic gate without clock, and the input node in this subclass of above-mentioned a plurality of input nodes comprises recurrence logic ' 0 ' node separately.

36. integrated circuits as claimed in claim 34, wherein this first logic is supplied at least one and is returned logic ' 1 ' signal, wherein, above-mentioned the first state is that logic ' 0 ' and above-mentioned the second state are logic ' 1 ', this comprises that without clock-state regression domino logic gate one returns logic ' 1 ' domino logic gate without clock, and the input node in this subclass of above-mentioned a plurality of input nodes comprises recurrence logic ' 1 ' node separately.

The method of 37. 1 kinds of estimation one logical operations, comprising:

Receive a plurality of input signals, design separately at one first state and one second state and switch, wherein, above-mentioned a plurality of input signal comprises that at least one state returns signal, and above-mentioned at least one state returns signal can return according to state above-mentioned the second state of resetting back that operates after being set as above-mentioned the first state;

Supply has a dominoes circuit of a preset condition and a latch mode, when this dominoes circuit is this preset condition, this dominoes circuit is set a preset node and activation node to one first state, and set an output node and replacement node to one second state, when this preset node transition is during to this second state, this dominoes circuit switches to this latch mode, with this output node of transition to this first state and this activation node of transition to this second state, when this first state is put in this replacement node transition, this dominoes circuit this preset condition of resetting back,

Estimate above-mentioned a plurality of input signal, wherein, above-mentioned a plurality of input signals be at least one estimated state any time, this preset node of transition, to this second state, makes this dominoes circuit switch to this latch mode; And

This activation node be this second state and above-mentioned a plurality of input signal in above-mentioned at least one estimated state any time, this replacement node of transition is to this first state, with this dominoes circuit of resetting to this preset condition.

38. methods as claimed in claim 37, when wherein above-mentioned replacement step is included in this activation node and returns signal above-mentioned the second state is returned in transition after switching to above-mentioned the first state separately for this second state and above-mentioned at least one state, this replacement node of transition is to above-mentioned the first state.

39. methods as claimed in claim 37, wherein:

Above-mentioned estimation steps is included in above-mentioned at least one state and returns while having a transition to above-mentioned the first state at least in signal this preset node of transition to above-mentioned the second state; And

Above-mentioned replacement step be included in this activation node be above-mentioned the second state and above-mentioned at least one state when returning the equal transition of signal and returning above-mentioned the second state this replacement node of transition to above-mentioned the first state.

40. methods as claimed in claim 37, wherein:

When above-mentioned estimation steps is included in above-mentioned at least one state and returns the total transition of signal and return above-mentioned the first state, this preset node of transition is to this second state; And

Above-mentioned replacement step is included in this activation node while returning above-mentioned the second state for this second state and above-mentioned at least one state return the total transition of signal this replacement node of transition is to above-mentioned the first state.

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