CN102299076A - Method for manufacturing semiconductor device - Google Patents
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- CN102299076A CN102299076A CN2010102180689A CN201010218068A CN102299076A CN 102299076 A CN102299076 A CN 102299076A CN 2010102180689 A CN2010102180689 A CN 2010102180689A CN 201010218068 A CN201010218068 A CN 201010218068A CN 102299076 A CN102299076 A CN 102299076A
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Abstract
The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a front end device layer; forming gates on the front end device layer; carrying out ion implantation to form a common source and drains; forming a clearance wall layer; forming a protective layer on the clearance wall layer and ensuring the thickness of the protective layer on the common source to be greater than the thickness of other parts of the protective layer; etching the protective layer; and etching the clearance wall layer to form clearance walls, wherein the common source is arranged in the front end device layer and between the adjacent gates. The semiconductor device formed by the method improves the consistency of the critical dimensions of clearance wall etching, reduces the difficulty in etching the clearance walls and enlarges the process window.
Description
Technical field
The present invention relates to manufacture of semiconductor, relate in particular to a kind of manufacture method of semiconductor device.
Background technology
Along with the development of very lagre scale integrated circuit (VLSIC) technology, semiconductor technology has now entered the sub-micro epoch.The development of technology makes will comprise that processor, memory, analog circuit, interface logic even radio circuit are integrated on the large-scale chip, form so-called SoC (SOC (system on a chip)).As the in-line memory of SoC important component part, proportion shared in SoC increases gradually.The semiconductor memory that is used to store data is divided into volatile memory and nonvolatile memory (NVM), and volatile memory is not preserved its data when power interruptions, even and nonvolatile memory still can the retention tab internal information after power supply is closed.In a lot of equipment, comprise the NVM medium, be used for after device powers down, storing data and restart the back use in order to equipment such as in-line memory.The NVM medium comprises EPROM (EPROM), Electrically Erasable Read Only Memory (EEPROM), flash memory (FLASH) etc.
Wherein flash memory is important a kind of in the NVM product, all needs the supporting use of flash memory in normally used USB flash disk, mobile phone, the digital camera.Flash memory has the numerous species type, divides from structure to mainly contain AND, NAND, NOR, DiNOR etc.Wherein the NOR flash memory is a most general present flash memory, and all the internal memory with commonly used is close on storage format and read-write mode for it, supports random read-write, has higher speed, makes it be fit to very much stored program and related data like this.With reference to figure 1, be the schematic diagram of the memory cell 100 of traditional NOR flash memory.Wherein each memory cell 100 of NOR flash memory generally includes two folded grid 110 and 120 as can be seen, each folded grid comprises by polysilicon (poly) to be made being used for the floating boom FG (Floating Gate) 101 of store electrons, and is used for the control gate CG (Control Gate) 102 of control data access.Floating boom 101 is positioned at control gate 102 belows, and is in " floating " state usually, is not connected with any circuit.According in the polysilicon that constitutes floating boom 101 whether electron storage being arranged, represent that this unit canned data is " 0 " or " 1 ".And control gate 102 is connected with word line (Word Line) 103 usually.Memory cell 100 comprises two word lines 103, is separately positioned on the both sides of memory cell 100.Divide the word line 103 that is arranged to wipe (over-erase) in order to the mistake that prevents memory cell 100.In addition, between two folded grid 110 and 120, memory cell 100 also comprises erase gate (Erase Gate) 104.By applying suitable voltage, the electronic energy in the floating boom 101 flows to erase gate 104 by the passage between floating boom 101 and the erase gate 104, thereby memory cell 100 is carried out erase operation.On the sidewall of grid, also be formed with the clearance wall structure.These structures are that those skilled in the art is known, therefore all do not indicate in Fig. 1.Simultaneously, for some other structure of memory cell 100, also can do an explanation below in conjunction with other accompanying drawings.In the manufacturing process of these memories, can adopt the structure of common source.The manufacturing step that has the memory of this structure below in conjunction with Brief Description Of Drawings.
At first, on front end device layer 201, form oxide layer 202, form first polysilicon layer 203, dielectric layer 204 and second polysilicon layer 205 subsequently thereon and the formation sandwich construction with reference to figure 2A.On second polysilicon 205, also be formed with the hard mask layer (not shown).
With reference to figure 2B, carry out the etching of control gate then, to form control gate 205A and 205B.Then proceed to Fig. 2 C, carry out the etching of floating boom, to form floating boom 203A and 203B.Etching to floating boom can etch into oxide layer 202, and oxide layer 202 is not carried out etching; Also can etch away this oxide layer 202.Fig. 2 C shows the situation that etches away this oxide layer 202.Shown in Fig. 2 D, carry out ion implantation technology then, to form common source 207 and drain electrode 206A, 206B.
Then shown in Fig. 2 E, on the sidewall of grid 210A and 210B, form the clearance wall insulating barrier.Shown in Fig. 2 F, on the sidewall of clearance wall insulating barrier, form clearance wall 208A, 208A ' and 208B, 208B ' at last.
In the formation technology of this traditional clearance wall, when carrying out the clearance wall etching, may damage the structure of closing on.For example: the front end device layer of metal silicide layer, grid and bottom etc.Especially be easy to damage the structure on common source between two grids or title common source district.When this situation took place, electronics can more easily enter into floating gate layer, thereby caused the floating boom data to keep mistake.Secondly also can influence the sheet resistor in the fair Acceptance Tests of wafer.And can influence the consistency of the critical size of clearance wall etching.
Therefore, need a kind of manufacture method of preferable semiconductor device in the prior art,, especially do not damage the structure on the common source in the process of clearance wall etching, not damage other structures.
Summary of the invention
The invention discloses a kind of manufacture method of semiconductor device, this method comprises: the front end device layer is provided; On described front end device layer, form grid; Carry out ion and inject to form common source and drain electrode, this common source is arranged in this front end device layer, and is between the adjacent grid; On the total that abovementioned steps forms, form the gap parietal layer; On the parietal layer of gap, form protective layer, and make the thickness of the thickness of protective layer on common source greater than other parts of protective layer; Protective layer is carried out etching, with after described etching, reserve part protective layer above common source; With the gap parietal layer is carried out to form clearance wall.
Further, deposit the dielectric and second polysilicon layer between first polysilicon layer, crystal silicon layer on this front end device layer.
Preferably, the thickness of this protective layer is between the 300-1000 dust, preferably between the 400-600 dust.
Preferably, this protective layer can be an oxide layer, perhaps is made up of Si oxide, or is made up of silicon nitride.
Preferably, the deposition of this protective layer adopts TEOS as source gas, perhaps adopts SiH
4As source gas.
Further, said method also comprises: before forming this gap parietal layer, also be formed with the clearance wall insulating barrier on the sidewall of grid.
Further, the etching of this protective layer is undertaken by wet etching or dry etching.
Semiconductor device by method of the present invention forms has improved the consistency of the critical size of clearance wall etching, and has reduced the difficulty of clearance wall etching, has increased process window.
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the present invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the schematic diagram of the memory cell of traditional flash memory;
Fig. 2 A to Fig. 2 F is the profile of the related device architecture of each step in the manufacture method of traditional a kind of semiconductor device;
Fig. 3 A to Fig. 3 H is the profile according to the related device architecture of each step in the method for the described manufacturing semiconductor device of an embodiment of the invention;
Fig. 4 is the flow chart according to the manufacture method of the semiconductor device of an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
Fig. 3 A to Fig. 3 H is the profile according to the related device architecture of each step in the method for the described manufacturing semiconductor device of an embodiment of the invention.As shown in Figure 3A, provide a front end device layer 301.This front end device layer 301 can be a Semiconductor substrate, also can be to be suitable for implementing other devices of the present invention thereon.On this front end device layer 301, be formed with layer of oxide layer 302 and be used as insulating barrier.This oxide layer 302 is also referred to as grid oxic horizon.This oxide layer 302 can adopt for example thermal oxidation method formation, and its thickness can be for example below 100 dusts.Preferably, this oxide layer 302 can be the 10-20 dust.The material of this oxide layer 302 can have multiple choices, for example silica, germanium oxide etc.Need to prove that this oxide layer 302 can be included in this front end device layer 301.Deposit first polysilicon layer 303 then on oxide layer 302, thickness is approximately the 300-500 dust.The deposition of this first polysilicon layer 303 can adopt chemical vapor deposition (CVD) method or thermal oxidation method to form, and perhaps adopts other methods that are fit to form.This first polysilicon layer 303 is used to form floating boom above-mentioned, so this first polysilicon layer 303 is also referred to as floating gate layer.After this on first polysilicon layer 303, form interpoly dielectric.In the example of embodiment of the present invention, this interpoly dielectric can be oxide layer-nitride layer-oxide layer (ONO layer) 304, but is understandable that, this interpoly dielectric also can be other structure.In this execution mode of the present invention, describe in conjunction with ONO layer 304.The material of this ONO layer 304 can be chosen as silica-silicon-nitride and silicon oxide, and thickness can be approximately the 135-165 dust.Need to prove,, for convenience, in specification and accompanying drawing, all represent with ONO layer 304 though this ONO layer is a three-decker.Then, deposition second polysilicon layer 305 on ONO layer 304, thickness is approximately the 600-800 dust.This second polysilicon layer 305 is used to form control gate above-mentioned.This second polysilicon layer 305 can adopt chemical vapor deposition (CVD) method or thermal oxidation method to form equally, perhaps adopts additive method to form.This can also nitride layer-oxide layer above second polysilicon layer 305-nitride layer (NON layer) (not shown), the material of this NON layer can be selected silicon-nitride and silicon oxide-silicon nitride, thickness can be the 1300-1600 dust.This NON layer is as hard mask layer, and this hard mask layer also can be made of other structures certainly, the NON layer that is not limited to mention among the present invention.Except structure above-mentioned, on the NON layer, also can deposit one deck bottom antireflective coating (darc layer) in the photoetching process, be used for reducing or eliminate the influence of reverberation at exposure process.On darc layer, also apply the photoresist layer that one deck has pattern.The formation of darc layer and photoresist layer and effect all are that those skilled in the art understand, and do not repeat them here.
Next, shown in Fig. 3 B, at first second polysilicon layer 305 is carried out etching to form control gate 305A and 305B.Be understandable that etching and the etching to first polysilicon layer 303 cited below to second polysilicon layer 305 can adopt the several different methods in this area to finish.Such as adopting wet etching method or dry etching method to carry out etching, can use gases such as solution such as sulfuric acid or carbon tetrafluoride to carry out etching accordingly.In the optional example of above-mentioned embodiments of the present invention, the etching of second polysilicon layer 305 is finished by removing part second polysilicon layer 305 and part of O NO layer 304 successively, form above-mentioned control gate 305A and 305B with this.In this process, but also using plasma etching technics, and the directivity of etching can realize by the bias power and the cathode bias power of control plasma source.The selection of lithographic method does not limit the scope of the invention.Behind over etching, partly form two folded grid 310A and 310B, these two folded grid 310A and 310B comprise control gate 305A and 305B, part of O NO layer 304A and 304B respectively.What certainly can understand is, folded grid 310A has identical structure with 310B, and here it being distinguished only is convenience in order to describe.In addition, folded grid 310A that partly forms herein and 310B refer to the grid part that etching is finished.In addition, mode when carrying out the control gate etching, can only etch into till the ONO layer 304 as an alternative, promptly ONO layer 304 is not carried out substantial etching, and again ONO layer 304 is carried out etching in the etching of the floating boom that carries out subsequently.
Shown in Fig. 3 C, carry out first polysilicon layer, 303 etchings then to form floating boom 303A and 303B.Etching to first polysilicon layer 303 can stop at oxide layer 302, promptly oxide layer 302 is not carried out substantial etching; Also can be shown in Fig. 3 C like that oxide layer 302 is carried out etching, form partial oxidation layer 302A and 302B this moment.Can adopt suitable method that first polysilicon layer 303 is carried out etching equally.By etching, form floating boom 303A and 303B respectively to first polysilicon layer 303.Mode when control gate is carried out etching, if only etched into ONO layer 304, when carrying out the floating boom etching, at first will be carried out etching to this ONO layer 304 so as an alternative.
Shown in Fig. 3 D, carry out ion implantation technology then.For example, with N type dopant, for example arsenic, antimony or phosphorus etc. inject silicon layers, and perhaps with P type dopant, for example boron etc. injects silicon layer, with this form semiconductor device common source 307 and drain electrode 306A, 306B.This common source 307 is between two grid 310A and 310B, and in front end device layer 301. Drain electrode 306A and 306B lay respectively at the opposite side of grid 310A and 310B.After the doping of finishing common source and drain electrode, can anneal or activate the Technology for Heating Processing of dopant silicon chip usually, this step is known in this area, does not repeat them here.
Shown in Fig. 3 E, on silicon chip, deposit gap parietal layer 308 then.That is to say and on the structure shown in Fig. 3 D, form gap parietal layer 308.This gap parietal layer 308 is used to form the clearance wall of mentioning later.Gap parietal layer 308 for example can be a silicide, for example can be Si
3N
4, SiO
2Or silicon nitride etc.The deposition of gap parietal layer 308 can adopt the CVD method to form or thermal oxidation method forms, and can certainly adopt additive method to form.The thickness of this gap parietal layer 308 is greatly between the 500-2000 dust.In addition, between grid 310A and 310B and gap parietal layer 308 above-mentioned clearance wall insulating barrier can be arranged, this clearance wall insulating barrier can be made of silica.These are to know in this area, therefore do not repeat them here and no longer illustrate.This clearance wall insulating barrier and the clearance wall that forms below also are collectively referred to as side wall in the art.
Then shown in Fig. 3 F, on gap parietal layer 308, form protective layer 309.Be different from the prior art and after forming gap parietal layer 308, immediately gap parietal layer 308 carried out etching, in an embodiment of the invention, after gap parietal layer 308 forms, need on this gap parietal layer 308, to form earlier protective layer 309.The material of this protective layer 309 for example can be Si oxide, silicon nitride or the like.Preferably, this protective layer 309 is for selecting to form oxide layer, to be used as the etching protective layer.The generation type of this protective layer 309 can use chemical vapour deposition technique to form, for example plasma-enhanced chemical vapor deposition PECVD method (PE CVD), high-density plasma vapour deposition process etc.Also can adopt thermal oxidation method to form.Preferably, adopt TEOS (tetraethoxysilane) to deposit as source gas.Also can be with SiH
4Gas is as the SILPE Base technology of reacting gas.The thickness of this protective layer 309 is at the 300-1000 dust, and is preferable at the 400-600 dust.Owing to the more approaching reason of distance between two grids; after protective layer 309 forms; protective layer 309 on the sidewall between two grids can partly link together, and therefore the thickness of the protective layer 309 on common source 307 is greater than the thickness of other parts.Perhaps also can control, so that at the thickness of the protective layer on source electrode 309 thickness greater than other parts of protective layer 309 to the thickness of protective layer 309.
Shown in Fig. 3 G, this protective layer 309 is carried out etching then.For example can adopt isotropism or anisotropic dry etching or wet etching, remove with protective layer 309 with segment thickness.Because this protective layer 309 at the thickness on the common source between the grid 307 greater than the thickness on other parts, so when carrying out etching, the protective layer 309 that is positioned on other parts is removed easily basically fully.And still have remaining protective layer 309 ' this moment above the common source between the grid 307, with in follow-up protection clearance wall when carrying out the clearance wall etching.
Then shown in Fig. 3 H, the etching of carrying out clearance wall is to form clearance wall 308A, 308A ' and 308B, 308B '.Etching to clearance wall can adopt dry etching or wet etching to carry out.The etching agent proportioning of selecting for use is preferably for gap parietal layer 308 for protective layer 309, has the proportioning of higher etching selection ratio for gap parietal layer 308.For example, when protective layer 309 is a Si oxide, and gap parietal layer 308 is when being silicon nitride, and the etching agent proportioning can be for having high selectivity to silicon nitride; And when protective layer 309 is silicon nitride, and gap parietal layer 308 is when being Si oxide, the etching agent proportioning can be to having high selectivity with Si oxide.Like this, remaining protective layer 309 ' still can play the effect of protective layer.After the clearance wall etching was finished, clearance wall 308A ' and 308B between two grids sealed, rather than open in prior art, therefore can avoid electronics to enter into floating gate layer, thereby caused the floating boom data to keep mistake.And can not influence the sheet resistor in the fair Acceptance Tests of wafer, and keep the consistency of the critical size of clearance wall etching.
After clearance wall forms, again by a series of step formation memory cell as shown in Figure 1.These steps are known by those skilled in the art, do not repeat them here.
Though above-mentioned in conjunction with folded grid an embodiment of the invention are described, the present invention is equally applicable to the situation of non-folded grid.
Fig. 4 is the flow chart according to the manufacture method 400 of the semiconductor device of embodiment of the present invention.In step 402, provide the front end device layer.This front end device layer can be a Semiconductor substrate, also can be that other are suitable for implementing other devices of the present invention thereon.In step 404, on the front end device layer, form grid structure.In step 406, carry out ion and inject to form common source and drain electrode, this common source is arranged in the front end device layer, and is between the adjacent grid.In step 408, on the total that step 406 forms, form the gap parietal layer.In step 410, on the parietal layer of gap, form protective layer.In step 412, protective layer is carried out etching.Etching to protective layer makes after the protective layer etching, reserve part protective layer above common source.In step 414, carry out the clearance wall etching to form clearance wall.Above-mentioned steps is described in detail in the explanation in conjunction with Fig. 3 A-3H in the above, does not repeat them here.
The semiconductor device of Zhi Zaoing according to the embodiment of the present invention; because after forming the gap parietal layer; carry out the deposition and the etching of protective layer earlier; and then carry out the etching of clearance wall; seal when therefore the clearance wall that forms is above common source; can prevent that like this electronics in the subsequent step from entering into grid, prevent to cause grid to preserve data failure.
The semiconductor device that comprises according to above-mentioned execution mode manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
In addition, need to prove that accompanying drawing of the present invention only is a schematic diagram, it is an execution mode for a better understanding of the present invention, and the proportionate relationship shown in it is for not being interpreted as limitation of the present invention.And though the present invention is described in conjunction with the memory cell of NOR flash memory, embodiments of the present invention are applicable to that too other have the memory of same or similar structure.
The present invention is illustrated by above-mentioned execution mode, but should be understood that, above-mentioned execution mode just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described execution mode scope.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-mentioned execution mode, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. the manufacture method of a semiconductor device, described method comprises:
A) provide the front end device layer;
B) on described front end device layer, form grid;
C) carry out ion and inject to form common source and drain electrode, described common source is arranged in described front end device layer, and is between the adjacent described grid;
D) on the total that described step c) forms, form the gap parietal layer;
E) on the parietal layer of described gap, form protective layer, and make the thickness of the thickness of described protective layer on described common source greater than other parts of described protective layer;
F) described protective layer is carried out etching, with after described etching, reserve part protective layer above described common source; With
G) described gap parietal layer is carried out etching to form clearance wall.
2. the manufacture method of semiconductor device according to claim 1 is characterized in that, deposits first polysilicon layer, interpoly dielectric and second polysilicon layer on the described front end device layer.
3. the manufacture method of semiconductor device according to claim 1 is characterized in that, the thickness of described protective layer is between the 300-1000 dust.
4. the manufacture method of semiconductor device according to claim 1 is characterized in that, the thickness of described protective layer is between the 400-600 dust.
5. the manufacture method of semiconductor device according to claim 1 is characterized in that, described protective layer is an oxide layer.
6. the manufacture method of semiconductor device according to claim 1 is characterized in that, described protective layer is made up of Si oxide.
7. the manufacture method of semiconductor device according to claim 1 is characterized in that, described protective layer is made up of silicon nitride.
8. the manufacture method of semiconductor device according to claim 1 is characterized in that, the deposition of described protective layer adopts TEOS as source gas, perhaps adopts SiH
4As source gas.
9. the manufacture method of semiconductor device according to claim 1 is characterized in that, described method also comprises: before forming described gap parietal layer, also be formed with the clearance wall insulating barrier on the sidewall of described grid.
10. the manufacture method of semiconductor device according to claim 1 is characterized in that, described etching to described protective layer is undertaken by wet etching or dry etching.
11. an integrated circuit that comprises the semiconductor device of making by method according to claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
12. an electronic equipment that comprises the semiconductor device of making by method according to claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| CN102610508A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Preparation method of floating gate |
| CN104681492A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Flash memory unit forming method |
| CN111863818A (en) * | 2020-09-22 | 2020-10-30 | 晶芯成(北京)科技有限公司 | SRAM device and forming method thereof |
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