CN102136456A

CN102136456A - Method for manufacturing grid structure of storage

Info

Publication number: CN102136456A
Application number: CN2010101024166A
Authority: CN
Inventors: 李勇; 刘艳; 周儒领
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2010-01-27
Filing date: 2010-01-27
Publication date: 2011-07-27

Abstract

The invention relates to a method for manufacturing a grid structure of a storage, which comprises the following steps of: providing a front-end device layer; depositing a first polycrystalline silicon layer on the front-end device layer; depositing a polycrystalline silicon interlayer medium body on the first polycrystalline silicon layer; depositing a second polycrystalline silicon layer on the polycrystalline silicon interlayer medium body; etching the second polycrystalline silicon layer to form a control grid, and stopping etching the second polycrystalline silicon layer on the first polycrystalline silicon layer; etching the polycrystalline silicon interlayer medium body; and etching the first polycrystalline silicon layer to form a floating grid. By the method for manufacturing the grid structure of the storage, an angle formed between the floating grid and an erasing grid can be sharper, and the erasing efficiency is improved.

Description

A kind of manufacture method of memory gate electrode structure

Technical field

The present invention relates to manufacture of semiconductor, relate in particular to the manufacture method of memory gate electrode structure.

Background technology

Along with the development of very lagre scale integrated circuit (VLSIC) technology, semiconductor technology has now entered the sub-micro epoch.The development of technology makes will comprise that processor, memory, analog circuit, interface logic even radio circuit are integrated on the large-scale chip, form so-called SoC (SOC (system on a chip)).As the in-line memory of SoC important component part, proportion shared in SoC increases gradually.The semiconductor memory that is used to store data is divided into volatile memory and nonvolatile memory (NVM), and volatile memory is not preserved its data when power interruptions, even and nonvolatile memory still can the retention tab internal information after power supply is closed.In a lot of equipment, comprise the NVM medium, be used for after device powers down, storing data and restart the back use in order to equipment such as in-line memory.The NVM medium comprises EPROM (EPROM), Electrically Erasable Read Only Memory (EEPROM), flash memory (FLASH) etc.

Wherein flash memory is important a kind of in the NVM product, all needs the supporting use of flash memory in normally used USB flash disk, mobile phone, the digital camera.Flash memory has the numerous species type, divides from structure to mainly contain AND, NAND, NOR, DiNOR etc.Wherein the NOR flash memory is a most general present flash memory, and all the internal memory with commonly used is close on storage format and read-write mode for it, supports random read-write, has higher speed, makes it be fit to very much stored program and related data like this.

Fig. 1 is the schematic diagram of the memory cell 100 of traditional NOR flash memory.Wherein each memory cell 100 of NOR flash memory generally includes two folded

grid

110 and 120 as can be seen, each folded grid comprises by polysilicon (poly) to be made being used for the floating boom FG (Floating Gate) 101 of store electrons, and is used for the control gate CG (Control Gate) 102 of control data access.Floating boom 101 is positioned at control gate 102 belows, and is in " floating " state usually, is not connected with any circuit.According in the polysilicon that constitutes floating boom 101 whether electron storage being arranged, represent that this unit canned data is " 0 " or " 1 ".And control gate 102 is connected with word line (Word Line) 103 usually.Memory cell 100 comprises two word lines 103, is separately positioned on the both sides of memory cell 100.Divide the word line 103 that is arranged to wipe (over-erase) in order to the mistake that prevents memory cell 100.In addition, between two folded

grid

110 and 120, memory cell 100 also comprises erase gate (Erase Gate) 104.By applying suitable voltage, the electronic energy in the floating boom 101 flows to erase gate 104 by the passage between floating boom 101 and the erase gate 104, thereby memory cell 100 is carried out erase operation.In addition, memory cell 100 also comprises other structures, and such as oxide layer, gap insulation layer etc., these structures are that those skilled in the art is known, does not therefore indicate among Fig. 1 one by one.Simultaneously, for some other structure of memory cell 100, also can do an explanation below in conjunction with other accompanying drawings.

Efficiency of erasing is an important indicator weighing memory cell.For wiping of memory cell 100, if the angle of the floating boom 101 between floating boom 101 and erase gate 104 (being the angle A among Fig. 1) is sharp more, efficiency of erasing is just high more so.This is that also just easy more realization is wiped because this angle is sharp more, and the internal field of formation is strong more, and the electronics on the floating boom 101 flows to erase gate 104 by the passage between floating boom 101 and the erase gate 104; Otherwise this angle is blunt more, and the efficiency of erasing of memory cell is also just low more.And sharp more angle A can reduce the possibility of electronics reverse tunnel of 101 from erase gate 104 to floating boom.But how to make sharper angle A is a bottleneck of the prior art.

Fig. 2 A to 2D shows the method for making the grid structure of memory cell in the prior art.Shown in Fig. 2 A, at first provide a front end device layer 201 with shallow trench (not shown).This front end device layer 201 can refer to substrate or have the substrate of component structure.On front end device layer 201, form layer of oxide layer 202 then and be used as insulating barrier.This oxide layer 202 can adopt for example thermal oxidation method formation, and its thickness can be for example below 100 dusts.Preferred thickness can be at the 10-20 dust.Deposit first polysilicon layer 203 then on oxide layer 202, thickness is approximately the 300-500 dust.The deposition of this first polysilicon layer can adopt the chemical vapor deposition (CVD) method or adopt other suitable methods to form.This first polysilicon layer 203 forms floating boom above-mentioned.This first polysilicon layer is also referred to as floating gate layer in this article.Form oxide layer-nitride layer-oxide layer (ONO layer) 204 then on first polysilicon layer 203, the material of this ONO layer 204 can be chosen as silica-silicon-nitride and silicon oxide, and thickness is approximately the 135-165 dust.This ONO layer 204 is as dielectric layer.Then, deposition second polysilicon layer 205 on ONO layer 204, thickness is approximately the 600-800 dust.The deposition of this second polysilicon layer 205 can adopt the chemical vapor deposition (CVD) method equally or adopt additive method.This second polysilicon layer 205 forms control gate above-mentioned.This second polysilicon layer is also referred to as control grid layer in this article.Deposit one deck nitride layer-oxide layer-nitride layer (NON layer) 206 above second polysilicon layer 205 at this, the material of this NON layer 206 can be selected silicon-nitride and silicon oxide-silicon nitride, and thickness is the 1300-1600 dust.This NON layer 206 is as hard mask layer.Except structure above-mentioned, in the photoetching process of reality, on NON layer 206, also can deposit one deck bottom antireflective coating (darc layer), be used for reducing or eliminate the influence of reverberation at exposure process.On darc layer, also apply the photoresist layer that one deck has pattern.The formation of darc layer and photoresist layer and effect all are that those skilled in the art understand, and do not repeat them here.

Next, shown in Fig. 2 B, at first carry out the etching of control gate.This etching can adopt wet etching or dry etching to carry out, correspondingly can adopt gases such as solution such as sulfuric acid or carbon tetrafluoride to carry out etching technics, etching removes part NON layer 206, part second polysilicon layer 205, part of O NO layer 204 successively, forms above-mentioned control gate with this.Behind over etching, form two folded

grid

210A and 220B, on these two folded

grid

210A and 220B, comprise

NON layer

206A and 206B,

control gate

205A and 205B and

ONO layer

204A and 204B respectively.What certainly can understand is, folded grid 210A has identical structure with 220B, and here it being distinguished only is convenience in order to describe.

From to the description of Fig. 2 B as can be seen, when forming control gate, be to be etched directly into first polysilicon layer 203, the i.e. floating gate layer in the prior art.A problem of etching generation is to cause the loss of floating gate layer like this, in general can cause the loss of about 100 dusts of floating gate layer.Because floating gate layer is very thin, the thickness of nearly 400 dusts, so because the loss of this thickness, through after the etching of control gate, floating gate layer can form the shape shown in Fig. 2 B.This shape makes that the final angle A that forms is an obtuse angle but not wedge angle.In addition, be very difficult to the control of this thickness loss, therefore also may cause the damage of substrate again.

Then shown in Fig. 2 C, on the sidewall of the first folded grid 210A and the second folded grid 220B, form clearance

wall insulating barrier

207A, 207A ', 207B and 207B ' respectively, on the sidewall of clearance

wall insulating barrier

207A, 207A ', 207B and 207B ',

form clearance wall

208A, 208A ' and 208B, 208B ' then.Clearance wall insulating barrier and clearance wall can adopt the CVD method to form or thermal oxidation method forms, and can certainly adopt additive method to form.

Shown in Fig. 2 D, carry out first polysilicon layer, 203 etchings then to form floating boom 203A and 203B.Can adopt above-mentioned method that first polysilicon layer 203 is carried out etching.To the etching stopping of first polysilicon layer 203 in oxide layer 202.Then through other steps formation memory cell as shown in Figure 1.

Shown in Fig. 2 E, be the schematic diagram at the floating boom wedge angle position of the memory cell made according to above-mentioned traditional method.Wherein only show the part of memory cell.As can be seen from the figure, the angle A between floating boom 203B and the erase gate 209 is the obtuse angle, and its angle probably is 128 degree.As mentioned above, under such angle, the efficiency of erasing of memory cell can be lower, and might cause from electronics from erase gate the possibility of 209 to floating boom 203B reverse tunnel.Therefore, need a kind of manufacture method of memory gate electrode structure in the prior art, so that the angle between floating boom and the erase gate is sharper, the efficient of wiping with raising.

Summary of the invention

Excessive and cause the lower problem of efficiency of erasing for the floating boom in the memory that solves prior art and the angle between the erase gate, the invention discloses a kind of manufacture method of memory gate electrode structure, this method comprises: the front end device layer a) is provided; B) deposition first polysilicon layer on the front end device layer; C) deposit spathic silicon inter-level dielectric body on first polysilicon layer; D) deposition second polysilicon layer on interpoly dielectric; E) second polysilicon layer is carried out etching forming control gate, and to the etching stopping of second polysilicon layer on first polysilicon layer; F) interpoly dielectric is carried out etching; G) first polysilicon layer is carried out etching to form floating boom.

Preferably, deposit hard mask layer on this second polysilicon layer.Preferably, hard mask layer is nitride layer-oxide layer-nitride layer.

Preferably, interpoly dielectric is oxide layer-nitride layer-oxide layer.

Further, this method also comprises the formation of erase gate.

Preferably, to the etching stopping of second polysilicon layer in the upper surface of interpoly dielectric.

Further, further comprising the steps of between step e) and the step f): form the clearance wall insulating barrier on the sidewall at control gate; On the sidewall of clearance wall insulating barrier, form clearance wall.

By the manufacture method of memory gate electrode structure of the present invention, can make the angle between floating boom and the erase gate sharper, improved the efficiency of erasing of memory cell.

The present invention further discloses a kind of integrated circuit that comprises by the semiconductor device of making according to above method, wherein integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.

The invention also discloses a kind of electronic equipment that comprises by the semiconductor device of making according to above method, wherein electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.

Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.

Description of drawings

Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,

Fig. 1 is the schematic diagram of the memory cell of traditional NOR flash memory;

Fig. 2 A to Fig. 2 D is the manufacture method of traditional memory gate electrode structure;

Fig. 2 E is the local enlarged diagram of the memory cell of the memory made according to the conventional method;

Fig. 3 A to Fig. 3 D is the manufacture method according to the memory gate electrode structure of the embodiment of the invention;

Fig. 3 E is the local enlarged diagram according to the memory cell of the memory of the method manufacturing of the embodiment of the invention;

Fig. 4 is the flow chart according to the manufacture method of the memory gate electrode structure of the embodiment of the invention.

Embodiment

In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.

Fig. 3 A to Fig. 3 D is the method according to the manufacturing memory cell grid structure of the embodiment of the invention.As shown in Figure 3A, provide a front end device layer 301 with shallow trench (not shown).This front end device layer 301 can be a Semiconductor substrate, also can be that other are suitable for implementing other devices of the present invention thereon.On this front end device layer 301, be formed with layer of oxide layer 302 and be used as insulating barrier.This oxide layer is also referred to as grid oxic horizon.This oxide layer 302 can adopt for example thermal oxidation method formation, and its thickness can be for example below 100 dusts.Preferably, this oxide layer 302 can be the 10-20 dust.The material of this oxide layer 302 can have multiple choices, for example silica, germanium oxide etc.Need to prove that this oxide layer 302 can be included in this front end device layer 301.Deposit first polysilicon layer 303 then on oxide layer 302, thickness is approximately the 300-500 dust.The deposition of this first polysilicon layer 303 can adopt chemical vapor deposition (CVD) method or thermal oxidation method to form, and perhaps adopts other methods that are fit to form.This first polysilicon layer 303 is used to form floating boom above-mentioned, so this first polysilicon layer 303 is also referred to as floating gate layer.After this on first polysilicon layer 303, form interpoly dielectric.In the example of the embodiment of the invention, this interpoly dielectric can be oxide layer-nitride layer-oxide layer (ONO layer) 304, but is understandable that, this interpoly dielectric also can be other structure.Describe in conjunction with ONO layer 304 in an embodiment of the present invention.The material of this ONO layer 304 can be chosen as silica-silicon-nitride and silicon oxide, and thickness can be approximately the 135-165 dust.Need to prove,, for convenience, in specification and accompanying drawing, all represent with ONO layer 304 though this ONO layer is a three-decker.Then, deposition second polysilicon layer 305 on ONO layer 304, thickness is approximately the 600-800 dust.This second polysilicon layer 305 forms control gate above-mentioned.This second polysilicon layer 305 can adopt chemical vapor deposition (CVD) method or thermal oxidation method to form equally, perhaps adopts additive method to form.Preferably, can be at this nitride layer-oxide layer-nitride layer (NON layer) 306 above second polysilicon layer 305, the material of this NON layer 306 can be selected silicon-nitride and silicon oxide-silicon nitride, and thickness can be the 1300-1600 dust.This NON layer 306 is as hard mask layer, and this hard mask layer also can be made of other structures certainly, the NON layer that is not limited to mention among the present invention.Need to prove equally,, for convenience, in specification and accompanying drawing, all represent with NON layer 306 though this NON layer is a three-decker.In addition, below the description of embodiments of the invention is all carried out in conjunction with this NON layer 306, but it is not to be used to limit the scope of the invention.Except structure above-mentioned, on NON layer 306, also can deposit one deck bottom antireflective coating (darc layer) in the photoetching process, be used for reducing or eliminate the influence of reverberation at exposure process.On darc layer, also apply the photoresist layer that one deck has pattern.The formation of darc layer and photoresist layer and effect all are that those skilled in the art understand, and do not repeat them here.

Need to prove at this, material, the thickness of each layer and the generation type of each layer of above-mentioned and following each that is about to mention layer, only be an example of embodiments of the invention, in different situations, can adopt different materials, different thickness and different generation types.These should not be construed as limiting the invention.

Next, shown in Fig. 3 B, at first second polysilicon layer 305 is carried out etching to form control gate.Be understandable that etching and the etching to first polysilicon layer 303 cited below to second polysilicon layer 305 can adopt the several different methods in this area to finish.Such as adopting wet etching method or dry etching method to carry out etching, can use gases such as solution such as sulfuric acid or carbon tetrafluoride to carry out etching accordingly.In the optional example of above-mentioned embodiments of the invention, to the etching of second polysilicon layer 305 by remove part NON layer 306 successively, part second polysilicon layer 305 is finished, and forms above-mentioned control gate with this.In this process, but also using plasma etching technics, and the directivity of etching can realize by the bias power and the cathode bias power of control plasma source.The selection of lithographic method does not limit the scope of the invention.Behind over etching, partly form two folded

grid

310A and 320B, these two folded

grid

310A and 320B comprise

part NON layer

306A and 306B,

control gate

305A and 305B respectively.What certainly can understand is, folded grid 310A has identical structure with 320B, and here it being distinguished only is convenience in order to describe.In addition, folded grid 310A that partly forms herein and 320B refer to the grid part that etching is finished.

Be etched directly in the prior art first polysilicon layer 303 different be that embodiments of the invention only etch into interpoly dielectric second polysilicon layer 305 being carried out etching when forming control gate, also are the ONO layer 304 in the present embodiment.In other words, the etching to second polysilicon layer 305 proceeds on first polysilicon layer 303.Promptly after the etching of finishing second polysilicon layer 305, at the interpoly dielectric that needs to also have on first polysilicon layer 303 of etching interpoly dielectric or part.Owing to only etch into interpoly dielectric rather than be etched directly into first polysilicon layer 303 (being floating gate layer), therefore can not cause any destruction to floating gate layer, can not produce the situation of floating gate layer thickness loss of the prior art.Can carry out good control to the shape of the floating boom of final formation like this.The present invention realizes by technology is improved, and therefore goes for other lithographic method.For embodiments of the invention, the etching of control gate is not limited to only etch into ONO layer 304.As long as etch on first polysilicon layer 303, just can guarantee that first polysilicon layer 303 is without prejudice when the control gate etching.And can protect first polysilicon layer 303 in heat treatment subsequently, this will be discussed in more detail below.

Then shown in 3C, on the sidewall of part NON layer 306A and control gate 305A and part NON layer 306B and control gate 305B, form clearance

wall insulating barrier

307A, 307A ', 307B and 307B ' respectively, on the sidewall of clearance

wall insulating barrier

307A, 307A ', 307B and 307B ', form

clearance wall

308A, 308A ' and 308B, 308B ' then.Clearance wall insulating barrier and clearance wall can adopt CVD method or other method to form.The selection of deposition process does not equally herein limit the scope of the invention yet.

Then interpoly dielectric is carried out etching, and after interpoly dielectric is carried out etching to first polysilicon layer, 303 etchings to form floating boom, shown in Fig. 3 D.Can adopt suitable method that the interpoly dielectric and first polysilicon layer 303 are carried out etching equally.Etching by to the interpoly dielectric (ONO layer 304) and first polysilicon layer 303 forms part of

O NO layer

304A and 304B and floating

boom

303A and 303B respectively.The part of O NO layer that wherein removes is corresponding to part first polysilicon layer that removes.That is, remove among Fig. 3 D the ONO layer segment and first polysilicon segment between two folded grid 310A and the 320B respectively.Owing to when carrying out the control gate etching, only etched into ONO layer 304, preferably etch into the upper surface of ONO layer 304, therefore before to first polysilicon layer, 303 etchings, first polysilicon layer 303 is without any loss, and the shape of first polysilicon layer 303 can well keep.Owing to there is not the loss of first polysilicon layer, 303 thickness, the angle of the angle A between floating boom of Xing Chenging and the erase gate 309 meets at right angles basically at last in addition.In practice, the angle of the angle A that the method by the embodiment of the invention obtains can reach 86 degree, shown in Fig. 3 E.By such wedge angle, improved the efficiency of erasing of memory cell.The influence of " smile effect " that produces when the existence of this ONO layer 304 can protect floating gate layer not to be subjected to after-baking better after further, control gate formed.This " smile effect " refers to the effect of the two ends perk that produces than thin material when being heated.This effect can further make the floating boom shape of last formation uncontrollable, therefore also need avoid.And, therefore significantly reduced the adverse effect of smile effect owing on floating boom, also have the existence of ONO layer 304, make that the final angle A that forms is sharper.

After forming floating boom, again by a series of step formation memory cell as shown in Figure 1, such as erase gate formation, word line formation etc.These steps are known by those skilled in the art, do not repeat them here.

Fig. 4 is the flow chart according to the manufacture method 400 of the grid structure of the memory cell of the embodiment of the invention.In step 402, provide the front end device layer.This front end device layer can be a Semiconductor substrate, also can be that other are suitable for implementing other devices of the present invention thereon.In step 404, deposition first polysilicon layer on the front end device layer.This first polysilicon layer is used to form floating boom above-mentioned.Such as first polysilicon layer 303.In step 406, deposit spathic silicon inter-level dielectric body on first polysilicon layer.Such as being ONO layer 304 above-mentioned.In step 408, deposition second polysilicon layer on interpoly dielectric.This second polysilicon layer is used to form control gate above-mentioned.Such as second polysilicon layer 305.Optionally, in step 409, on second polysilicon layer, deposit hard mask layer.Preferable, this hard mask layer is nitride layer-oxide layer-nitride layer.In step 410, second polysilicon layer is carried out etching to form control gate.Etching to this second polysilicon layer proceeds on first polysilicon layer.Preferably, the etching of this second polysilicon layer is proceeded to the upper surface of interpoly dielectric.But also can proceed within the interpoly dielectric.Such as the interpoly dielectric that etches away part.Optionally in step 411, on the sidewall of control gate, form the clearance wall insulating barrier, and on the sidewall of clearance wall insulating barrier, form clearance wall.In step 412, interpoly dielectric is carried out etching.Promptly the interpoly dielectric on first polysilicon layer is carried out etching.In step 414, first polysilicon layer is carried out etching to form floating boom.Each layer done detailed description above, do not repeated them here.

Table 1 shows the electrical parameter of the memory cell of the method manufacturing that utilizes the embodiment of the invention.

Parameter	Unit	Desired value	Prior art	The present invention
					Wt	Volt	0.5	0.18	0.34
lr1	Microampere	23	5.10	17.98
					Vte	Volt	Less than-4	-0.89	-4.44

Wherein Wt represents the threshold voltage of word line.On behalf of whole memory unit, lr1 read electric current after wiping, and it is clean more that the big more then expression of this value is wiped.The Vte representative is at the threshold voltage of wiping the back control gate.Above-mentioned desired value is the value of wishing the relevant parameter of acquisition, and its correspondence is wiped effect preferably.From table 1, can see, the memory cell that adopts the method for the embodiment of the invention to make owing to improved the angle at the angle between floating boom and the erase gate, thus each electrical parameter than prior art more near desired value, therefore can reach and better wipe effect.

The semiconductor device that comprises according to the grid structure of the above embodiments manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.

In addition, need to prove that accompanying drawing of the present invention only is a schematic diagram, it is embodiment for a better understanding of the present invention, and the proportionate relationship shown in it is for not being interpreted as limitation of the present invention.And though the present invention is described in conjunction with the memory cell of NOR flash memory, embodiments of the invention are applicable to that too other have the memory of same or similar structure.

By the manufacture method of grid structure of semiconductor device of the present invention, can make the floating boom of formation and the angle between the erase gate sharper, improved the efficient of wiping.

The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims

1. the manufacture method of a memory gate electrode structure, described method comprises:

A) provide the front end device layer;

B) deposition first polysilicon layer on described front end device layer;

C) deposit spathic silicon inter-level dielectric body on described first polysilicon layer;

D) deposition second polysilicon layer on described interpoly dielectric;

E) described second polysilicon layer is carried out etching forming control gate, and described etching stopping to described second polysilicon layer is on described first polysilicon layer;

F) described interpoly dielectric is carried out etching;

G) described first polysilicon layer is carried out etching to form floating boom.

2. the manufacture method of memory gate electrode structure according to claim 1 is characterized in that, deposits hard mask layer on described second polysilicon layer.

3. the manufacture method of memory gate electrode structure according to claim 2 is characterized in that, described hard mask layer is nitride layer-oxide layer-nitride layer.

4. the manufacture method of memory gate electrode structure according to claim 1 is characterized in that, described interpoly dielectric is oxide layer-nitride layer-oxide layer.

5. the manufacture method of memory gate electrode structure according to claim 1 is characterized in that, described method also comprises the formation of erase gate.

6. the manufacture method of memory gate electrode structure according to claim 1 is characterized in that, described etching stopping to described second polysilicon layer is in the upper surface of described interpoly dielectric.

7. the manufacture method of memory gate electrode structure according to claim 1 is characterized in that, and is further comprising the steps of between described step e) and described step f):

On the sidewall of described control gate, form the clearance wall insulating barrier;

On the sidewall of described clearance wall insulating barrier, form clearance wall.

8. integrated circuit that comprises the semiconductor device of making by method according to claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.

9. electronic equipment that comprises the semiconductor device of making by method according to claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.