CN102270978A - Active low-pass filter based on positive feedback inductance substitution method - Google Patents

Abstract

The invention, which belongs to the analog filter design field, relates to an active low-pass filter based on a positive feedback inductance substitution method. The active low-pass filter comprises: a capacitor cell, wherein the capacitor unit is used for integrating low pass filtering characteristics as well as a second capacitor and a fourth capacitor are used for transforming active inductance; an input cell, which is used for converting an input signal in a voltage domain; a dummy cell, which is used for balancing an output common mode level and a parasitic effect; and an active inductance cell, which is used for realizing active inductance based on positive feedback. According to the active low-pass filter based on the positive feedback inductance substitution method provided in the invention, it is realized that a higher-order active low-pass filter is designed by an inductance substitution method on the basis of a positive feedback technology, so that the filter is little influenced by process variations; an analog signal is processed by employing a current multiplexing technology and a voltage domain, so that high linearity can be obtained with low power consumption; and different passboard gains can be realized by adjusting a width proportion of MOS tubes in an input portion; Moreover, the filter provided in the invention can be realized by a few transistors; and the structure of the filter is symmetrical and simple as well as is easy to design.

Description

A kind of active low-pass filter based on positive feedback inductance method of substitution

Technical field

The present invention relates to the Design of Analog Filter field, particularly a kind of active low-pass filter based on positive feedback inductance method of substitution.

Background technology

Based on the Design of Analog Filter technology develop rapidly of CMOS technology, novel filter circuit configuration continues to bring out.D ' Amico is at list of references " Stefano D ' Amico, Matteo Conta and Andrea Baschirotto, " A4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With79-dB DR; " IEEE Journal of Solid-State Circuits, pp.2713-2719, Dec.2006 " in described based on the active filter of source follower and broken traditional active filter project organization, under low-power consumption, realized high linear characteristic and high dynamic range.Single order shown in Fig. 1 based on the source follower integrator by source follower M _P1(its mutual conductance is G _M1) and load capacitance C _LForm integrator, its transfer function is:

$H\left(s\right)=\frac{G_{m1}}{G_{m1}+\mathrm{sg}{C}_L}---\left(1\right)$

On the basis of single order based on the source follower integrator, adopt local positive feedback technological synthesis plural number limit, D ' Amico has proposed full PMOS double-two-order unit (double-two-order unit 1) and full NMOS double-two-order unit (double-two-order unit 2), as shown in Figure 2, these double-two-order units are second-order low-pass filter.Full PMOS double-two-order unit and full NMOS double-two-order unit form the quadravalence low pass filter by cascade.

In actual applications, the demand to higher order filter is more.Usually the low pass double-two-order unit is mainly used in adopting in the cascade method design high-order low-pass filter.Other double-two-order units of the relative cascade of each double-two-order unit in the higher order filter are independent, and it is very big therefore to be subjected to the process deviation influence, and cascade progression is high more, influences big more.Here it is, and there is subject matter in present active low-pass filter based on source follower.(about the cascade method and the inductance method of substitution design higher order filter relevant knowledge of active filter can be with reference to Deliyannis, T., Sun, Y., and Fidler, J., K.: ' Continuous-Time Active Filter Design ' Boca Raton, FL:CRC, 1999.)

Each limit in the higher order filter that employing inductance method of substitution is realized is interrelated, and making the higher order filter that adopts this kind method to realize be subjected to process deviation influences very little.But this method mainly is based on negative-feedback technology (but list of references Bram Nauta at present, " A CMOS Transconductance-C Filter Technique for Very High Frequencies " IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.27, NO.2.FEBRUARY 1992), each passive inductance is formed active inductance by four transconductance cell and is substituted, and each transconductance cell is formed owing to eight transistors, and one five rank filter needs 64 transistors (only considering that inductance substitutes required transistorized quantity) at least.Therefore, based on the complex circuit designs of negative feedback inductor method of substitution.

In a word, at present there are 2 deficiencies in prior art: it is very big that (1) adopts the cascade method based on double-two-order unit to realize that higher order filter is influenced by process deviation; (2) based on the inductance method of substitution complex circuit designs of negative-feedback technology.

Summary of the invention

The objective of the invention is for overcoming the weak point of prior art, propose a kind of active low-pass filter based on positive feedback inductance method of substitution, the present invention has adopted based on the inductance method of substitution of positive feedback technique and has realized being subjected to process deviation to influence very little high-order low-pass filter.Can be widely used in inductance method of substitution design active low-pass filter.

The active low-pass filter based on positive feedback inductance method of substitution that the present invention proposes is characterized in that, adopts full PMOS pipe to realize that this active low-pass filter comprises:

Capacitor cell is used for comprehensive low-frequency filter characteristics;

Input unit is used in voltage domain converted input signal;

Dummy cell is used for balance output common mode level and ghost effect;

The active inductance unit is used to realize the active inductance based on positive feedback;

Wherein, described capacitor cell is by first capacitor C ₁, second capacitor C ₂, the 3rd capacitor C ₃, the 4th capacitor C ₄With the 5th capacitor C ₅Form second capacitor C ₂With the 4th capacitor C ₄Be used for the conversion active inductance; Wherein, first capacitor C ₁Positive pole meet the anode V of first node _1p, first capacitor C ₁Negative pole meet the negative terminal V of first node _1nSecond capacitor C ₂Positive pole meet the anode V of Section Point _2p, second capacitor C ₂Negative pole meet the negative terminal V of Section Point _2nThe 3rd capacitor C ₃Positive pole meet the anode V of the 3rd node _3p, the 3rd capacitor C ₃Negative pole meet the negative terminal V of the 3rd node _3nThe 4th capacitor C ₄Positive pole meet the anode V of the 4th node _4p, the 4th capacitor C ₄Negative pole meet the negative terminal V of the 4th node _4nThe 5th capacitor C ₅Positive pole meet the anode V of output node _Op, the 5th capacitor C ₅Negative pole meet the negative terminal V of output node _On

Described input unit is by PMOS pipe M _1l, the 2nd PMOS manages M _1r, the 3rd PMOS manages M _Dl, the 4th PMOS manages M _Dr, the 5th PMOS manages M _OlWith the 6th PMOS pipe M _OrForm; The one PMOS manages M _1lGrid connect input anode V _Ip, a PMOS manages M _1lSource electrode connect the anode V of first node _1pThe 2nd PMOS manages M _1rGrid meet input negative terminal V _In, the 2nd PMOS manages M _1rSource electrode connect the negative terminal V of first node _1nThe 3rd PMOS manages M _DlGrid meet bias voltage V _b, the 3rd PMOS manages M _DlSource electrode meet the anode V of first node _1pThe 4th PMOS manages M _DrGrid meet bias voltage V _b, the 4th PMOS manages M _DrSource electrode meet the negative terminal V of first node _1nThe 5th PMOS manages M _O1Grounded drain voltage GND, the 5th PMOS manages M _O1Grounded-grid voltage GND, the 5th PMOS manages M _O1Source electrode, a PMOS manage M _1lDrain electrode and the 3rd PMOS pipe M _D1Drain electrode link together; The 6th PMOS manages M _OrGrounded drain voltage GND, the 6th PMOS manages M _OrGrounded-grid voltage GND, the 6th PMOS manages M _OrSource electrode, the 2nd PMOS manage M _1rDrain electrode and the 4th PMOS pipe M _DrDrain electrode link together;

Described dummy cell is by the 7th PMOS pipe M _11l, the 8th PMOS manages M _11r, the 9th PMOS pipe M and the tenth PMOS pipe form; The 7th PMOS manages M _11lGrid meet bias voltage V _b, the 7th PMOS manages M _11lSource electrode meet the anode V of output node _OpThe 8th PMOS manages M _11rGrid meet bias voltage V _b, the 8th PMOS manages M _11rSource electrode meet the negative terminal V of output node _OnThe 9th PMOS manages M _12lGrounded drain voltage GND, the 9th PMOS manages M _12lGrounded-grid voltage GND, the 9th PMOS manages M _12lSource electrode and the 7th PMOS pipe M _11lDrain electrode link to each other; The tenth PMOS manages M _12rGrounded drain voltage GND, the tenth PMOS manages M _12rGrounded-grid voltage GND, the tenth PMOS manages M _12rSource electrode and the 8th PMOS pipe M _11rDrain electrode link to each other;

Described active inductance unit is by the 11 PMOS pipe M _2l, the 12 PMOS manages M _2r, the 13 PMOS manages M _6l, the 14 PMOS manages M _6r, the 15 PMOS manages M _10l, the 16 PMOS manages M _10r, the 17 PMOS manages V _3l, the 18 PMOS manages V _3r, the 19 PMOS manages V _5l, the 20 PMOS manages M _5r, the 21 PMOS manages M _7l, the 22 PMOS manages M _7r, the 23 PMOS manages M _9l, the 24 PMOS manages M _9r, the 25 PMOS manages M _4l, the 26 PMOS manages M _4r, the 27 PMOS manages M _8lWith the 28 PMOS pipe M _8rForm; The 11 PMOS manages M _2lDrain electrode meet the anode V of first node _1p, the 11 PMOS manages M _2lGrid meet the negative terminal V of first node _1n, the 11 PMOS manages M _2lSource electrode meet supply voltage VDD; The 12 PMOS manages M _2rDrain electrode meet the negative terminal V of first node _1n, the 12 PMOS manages M _2rGrid meet the anode V of first node _1p, the 12 PMOS manages M _2rSource electrode meet supply voltage VDD; The 13 PMOS manages M _6lDrain electrode meet the anode V of the 3rd node _3p, the 13 PMOS manages M _6lGrid meet the negative terminal V of the 3rd node _3n, the 13 PMOS manages M _6lSource electrode meet supply voltage VDD; The 14 PMOS manages M _6rDrain electrode meet the negative terminal V of the 3rd node _3n, the 14 PMOS manages M _6rGrid meet the anode V of the 3rd node _3p, the 14 PMOS manages M _6rSource electrode meet supply voltage VDD; The 15 PMOS manages M _10lDrain electrode meet the anode V of output node _Op, the 15 PMOS manages M _10lGrid meet the negative terminal V of output node _On, the 15 PMOS manages M _10lSource electrode meet supply voltage VDD; The 16 PMOS manages M _10rDrain electrode meet the negative terminal V of output node _On, the 16 PMOS manages M _10rGrid meet the anode V of output node _Op, the 16 PMOS manages M _10rSource electrode meet supply voltage VDD; The 17 PMOS manages V _3lDrain electrode meet the anode V of Section Point _2p, the 17 PMOS manages V _3lGrid meet the negative terminal V of Section Point _2n, the 17 PMOS manages V _3lSource electrode meet the anode V of first node _1pThe 18 PMOS manages V _3rDrain electrode meet the negative terminal V of Section Point _2n, the 18 PMOS manages V _3rGrid meet the anode V of Section Point _2p, the 18 PMOS manages V _3rSource electrode meet the negative terminal V of Section Point _2nThe 19 PMOS manages V _5lDrain electrode meet the anode V of Section Point _2p, the 19 PMOS manages V _5lGrid meet the negative terminal V of Section Point _2n, the 19 PMOS manages V _5lSource electrode meet the anode V of the 3rd node _3pThe 20 PMOS manages M _5rDrain electrode meet the negative terminal V of Section Point _2n, the 20 PMOS manages M _5rGrid meet the anode V of Section Point _2p, the 20 PMOS manages M _5rSource electrode meet the negative terminal V of the 3rd node _3nThe 21 PMOS manages M _7lDrain electrode meets the anode V of the 4th node _4p, the 21 PMOS manages M _7lGrid meet the negative terminal V of the 4th node _4n, the 21 PMOS manages M _7lSource electrode meet the anode V of the 3rd node _3pThe 22 PMOS manages M _7rDrain electrode meets the negative terminal V of the 4th node _4n, the 22 PMOS manages M _7rGrid meet the anode V of the 4th node _4p, the 22 PMOS manages M _7rSource electrode meet the negative terminal V of the 3rd node _3nThe 23 PMOS manages M _9lDrain electrode meet the anode V of the 4th node _4p, the 23 PMOS manages M _9lGrid meet the negative terminal V of the 4th node _4n, the 23 PMOS manages M _9lSource electrode meet the anode V of output node _5pThe 24 PMOS manages M _9rDrain electrode meet the negative terminal V of the 4th node _4n, the 24 PMOS manages M _9rGrid meet the anode V of the 4th node _4p, the 24 PMOS manages M _9rSource electrode meet the negative terminal V of output node _5nThe 25 PMOS manages M _4lDrain and gate earthed voltage GND, the 25 PMOS manages M _4lSource electrode meet the anode V of Section Point _2pThe 26 PMOS manages M _4rDrain and gate earthed voltage GND, the 26 PMOS manages M _4rSource electrode meet the negative terminal V of Section Point _2nThe 27 PMOS manages M _8lDrain and gate earthed voltage GND, the 27 PMOS manages M _8lSource electrode meet the anode V of the 4th node _4pThe 28 PMOS manages M _8rDrain and gate earthed voltage GND, the 28 PMOS manages M _8rSource electrode meet the negative terminal V of the 4th node _4n

The another kind that the present invention proposes is characterized in that based on the active low-pass filter of positive feedback inductance method of substitution, adopts full NMOS pipe to realize that this active low-pass filter comprises:

Capacitor cell is used for comprehensive low-frequency filter characteristics;

Input unit is used in voltage domain converted input signal;

Dummy cell is used for balance output common mode level and ghost effect;

The active inductance unit is used to realize the active inductance based on positive feedback;

Wherein, described capacitor cell is by first capacitor C ₁, second capacitor C ₂, the 3rd capacitor C ₃, the 4th capacitor C ₄With the 5th capacitor C ₅Form second capacitor C ₂With the 4th capacitor C ₄Be used for the conversion active inductance; Wherein, first capacitor C ₁Positive pole meet the anode V of first node _1p, first capacitor C ₁Negative pole meet the negative terminal V of first node _1nSecond capacitor C ₂Positive pole meet the anode V of Section Point _2p, second capacitor C ₂Negative pole meet the negative terminal V of Section Point _2nThe 3rd capacitor C ₃Positive pole meet the anode V of the 3rd node _3p, the 3rd capacitor C ₃Negative pole meet the negative terminal V of the 3rd node _3nThe 4th capacitor C ₄Positive pole meet the anode V of the 4th node _4p, the 4th capacitor C ₄Negative pole meet the negative terminal V of the 4th node _4nThe 5th capacitor C ₅Positive pole meet the anode V of output node _Op, the 5th capacitor C ₅Negative pole meet the negative terminal V of output node _On

Described input unit is by NMOS pipe M _1l, the 2nd NMOS manages M _1r, the 3rd NMOS manages M _Dl, the 4th NMOS manages M _Dr, the 5th NMOS manages M _OlWith the 6th NMOS pipe M _OrForm; The one NMOS manages M _1lGrid connect input anode V _Ip, a NMOS manages M _1lSource electrode connect the anode V of first node _1pThe 2nd NMOS manages M _1rGrid meet input negative terminal V _In, the 2nd NMOS manages M _1rSource electrode connect the negative terminal V of first node _1nThe 3rd NMOS manages M _DlGrid meet bias voltage V _b, the 3rd NMOS manages M _DlSource electrode meet the anode V of first node _1pThe 4th NMOS manages M _DrGrid meet bias voltage V _b, the 4th PMOS manages M _DrSource electrode meet the negative terminal V of first node _1nThe 5th PMOS manages M _O1Drain electrode meet supply voltage VDD, the 5th NMOS manages M _O1Grid meet supply voltage VDD, the 5th NMOS manages M _O1Source electrode, a NMOS manage M _1lDrain electrode and the 3rd NMOS pipe M _D1Drain electrode link together; The 6th NMOS manages M _OrDrain electrode meet supply voltage VDD, the 6th NMOS manages M _OrGrid meet supply voltage VDD, the 6th NMOS manages M _OrSource electrode, the 2nd NMOS manage M _1rDrain electrode and the 4th NMOS pipe M _DrDrain electrode link together.

Described dummy cell is by the 7th NMOS pipe M _11l, the 8th NMOS manages M _11r, the 9th NMOS pipe M and the tenth NMOS pipe form; The 7th NMOS manages M _11lGrid meet bias voltage V _b, the 7th NMOS manages M _11lSource electrode meet the anode V of output node _OpThe 8th NMOS manages M _11rGrid meet bias voltage V _b, the 8th NMOS manages M _11rSource electrode meet the negative terminal V of output node _OnThe 9th NMOS manages M _12lDrain electrode meet supply voltage VDD, the 9th NMOS manages M _12lGrid meet supply voltage VDD, the 9th NMOS manages M _12lSource electrode and the 7th NMOS pipe M _11lDrain electrode link to each other; The tenth NMOS manages M _12rDrain electrode meet supply voltage VDD, the tenth NMOS manages M _12rGrid meet supply voltage VDD, the tenth NMOS manages M _12rSource electrode and the 8th NMOS pipe M _11rDrain electrode link to each other.

Described active inductance unit is by the 11 NMOS pipe M _2l, the 12 NMOS manages M _2r, the 13 NMOS manages M _6l, the 14 NMOS manages M _6r, the 15 NMOS manages M _10l, the 16 NMOS manages M _10r, the 17 NMOS manages V _3l, the 18 NMOS manages V _3r, the 19 NMOS manages V _5l, the 20 NMOS manages M _5r, the 21 NMOS manages M _7l, the 22 NMOS manages M _7r, the 23 NMOS manages M _9l, the 24 NMOS manages M _9r, the 25 NMOS manages M _4l, the 26 NMOS manages M _4r, the 27 NMOS manages M _8lWith the 28 NMOS pipe M _8rForm; The 11 NMOS manages M _2lDrain electrode meet the anode V of first node _1p, the 11 NMOS manages M _2lGrid meet the negative terminal V of first node _1n, the 11 NMOS manages M _2lSource ground voltage GND; The 12 NMOS manages M _2rDrain electrode meet the negative terminal V of first node _1n, the 12 NMOS manages M _2rGrid meet the anode V of first node _1p, the 12 NMOS manages M _2rSource ground voltage GND; The 13 NMOS manages M _6lDrain electrode meet the anode V of the 3rd node _3p, the 13 NMOS manages M _6lGrid meet the negative terminal V of the 3rd node _3n, the 13 NMOS manages M _6lSource ground voltage GND; The 14 NMOS manages M _6rDrain electrode meet the negative terminal V of the 3rd node _3n, the 14 NMOS manages M _6rGrid meet the anode V of the 3rd node _3p, the 14 NMOS manages M _6rSource ground voltage GND; The 15 NMOS manages M _10lDrain electrode meet the anode V of output node _Op, the 15 NMOS manages M _10lGrid meet the negative terminal V of output node _On, the 15 NMOS manages M _10lSource ground voltage GND; The 16 NMOS manages M _10rDrain electrode meet the negative terminal V of output node _On, the 16 NMOS manages M _10rGrid meet the anode V of output node _Op, the 16 NMOS manages M _10rSource ground voltage GND; The 17 NMOS manages V _3lDrain electrode meet the anode V of Section Point _2p, the 17 NMOS manages V _3lGrid meet the negative terminal V of Section Point _2n, the 17 NMOS manages V _3lSource electrode meet the anode V of first node _1pThe 18 NMOS manages V _3rDrain electrode meet the negative terminal V of Section Point _2n, the 18 NMOS manages V _3rGrid meet the anode V of Section Point _2p, the 18 NMOS manages V _3rSource electrode meet the negative terminal V of Section Point _2nThe 19 NMOS manages V _5lDrain electrode meet the anode V of Section Point _2p, the 19 NMOS manages V _5lGrid meet the negative terminal V of Section Point _2n, the 19 NMOS manages V _5lSource electrode meet the anode V of the 3rd node _3pThe 20 NMOS manages M _5rDrain electrode meet the negative terminal V of Section Point _2n, the 20 NMOS manages M _5rGrid meet the anode V of Section Point _2p, the 20 NMOS manages M _5rSource electrode meet the negative terminal V of the 3rd node _3nThe 21 NMOS manages M _7lDrain electrode meets the anode V of the 4th node _4p, the 21 NMOS manages M _7lGrid meet the negative terminal V of the 4th node _4n, the 21 NMOS manages M _7lSource electrode meet the anode V of the 3rd node _3pThe 22 NMOS manages M _7rDrain electrode meets the negative terminal V of the 4th node _4n, the 22 NMOS manages M _7rGrid meet the anode V of the 4th node _4p, the 22 NMOS manages M _7rSource electrode meet the negative terminal V of the 3rd node _3nThe 23 NMOS manages M _9lDrain electrode meet the anode V of the 4th node _4p, the 23 NMOS manages M _9lGrid meet the negative terminal V of the 4th node _4n, the 23 NMOS manages M _9lSource electrode meet the anode V of output node _OpThe 24 NMOS manages M _9rDrain electrode meet the negative terminal V of the 4th node _4n, the 24 NMOS manages M _9rGrid meet the anode V of the 4th node _4p, the 24 NMOS manages M _9rSource electrode meet the negative terminal V of output node _OnThe 25 NMOS manages M _4lDrain and gate meet supply voltage VDD, the 25 NMOS manages M _4lSource electrode meet the anode V of Section Point _2pThe 26 NMOS manages M _4rDrain and gate meet supply voltage VDD, the 26 NMOS manages M _4rSource electrode meet the negative terminal V of Section Point _2nThe 27 NMOS manages M _8lDrain and gate meet supply voltage VDD, the 27 NMOS manages M _8lSource electrode meet the anode V of the 4th node _4pThe 28 NMOS manages M _8rDrain and gate meet supply voltage VDD, the 28 BMOS manages M _8rSource electrode meet the negative terminal V of the 4th node _4n

Characteristics of the present invention and effect:

(1) the present invention is different based on the negative feedback inductor method of substitution with tradition, realizes inductance method of substitution design high-order active low-pass filter based on positive feedback technique.

(2) the present invention adopts current multiplexing technology and voltage domain Analog signals, has realized obtaining high linearity under low-power consumption.

(3) the present invention compares with the cascade method design high-order active low-pass filter based on double-two-order unit, and it is very little to have adopted the inductance method of substitution to make it influenced by process deviation.

(4) the present invention can realize that symmetrical configuration is simple by less transistor, is easy to design.

(5) the present invention also can be further according to the gain requirement of using filter, and the ratio of the width of PMOS pipe and the 3rd PMOS pipe, the 2nd PMOS pipe and the 4th PMOS pipe can realize different passband gains in the adjustment importation.

(6) the present invention also can be by rationally setting transistorized size, makes the positive mutual conductance summation (comprising parasitic mutual conductance) of first node to the five nodes greater than negative transconductance under various process corner, so just can guarantee the stability of circuit.

Description of drawings

Fig. 1 is the schematic diagram of existing single order based on the source follower integrator;

Fig. 2 is existing full PMOS double-two-order unit and full NMOS double-two-order unit form the quadravalence low pass filter by cascade a schematic diagram;

Fig. 3 is the schematic diagram of the full PMOS pipe that proposes of the present invention based on the active low-pass filter of positive feedback inductance method of substitution;

Fig. 4 is the schematic diagram of the full NMOS pipe that proposes of the present invention based on the active low-pass filter of positive feedback inductance method of substitution;

Fig. 5 is the amplitude transmission curve of the 5 rank active low-pass filters that propose of the present invention.

Embodiment

Active low-pass filter based on positive feedback inductance method of substitution of the present invention reaches embodiment in conjunction with the accompanying drawings and is described in detail as follows:

The active low-pass filter based on positive feedback inductance method of substitution that the present invention proposes as shown in Figure 3, is characterized in that, adopts full PMOS pipe to realize that this active low-pass filter comprises:

Capacitor cell 1 is used for comprehensive low-frequency filter characteristics;

Input unit 2 is used in voltage domain converted input signal;

Dummy cell 3 is used for balance output common mode level and ghost effect;

Active inductance unit 4 is used to realize the active inductance based on positive feedback; Each unit with dashed lines collimation mark respectively goes out;

Wherein, described capacitor cell 1 is by first capacitor C ₁, second capacitor C ₂, the 3rd capacitor C ₃, the 4th capacitor C ₄With the 5th capacitor C ₅Form second capacitor C ₂With the 4th capacitor C ₄Be used for the conversion active inductance; Wherein, first capacitor C ₁Positive pole meet the anode V of first node _1p, first capacitor C ₁Negative pole meet the negative terminal V of first node _1nSecond capacitor C ₂Positive pole meet the anode V of Section Point _2p, second capacitor C ₂Negative pole meet the negative terminal V of Section Point _2nThe 3rd capacitor C ₃Positive pole meet the anode V of the 3rd node _3p, the 3rd capacitor C ₃Negative pole meet the negative terminal V of the 3rd node _3nThe 4th capacitor C ₄Positive pole meet the anode V of the 4th node _4p, the 4th capacitor C ₄Negative pole meet the negative terminal V of the 4th node _4nThe 5th capacitor C ₅Positive pole meet the anode V of output node _Op, the 5th capacitor C ₅Negative pole meet the negative terminal V of output node _On

Described input unit 2 is by PMOS pipe M _1l, the 2nd PMOS manages M _1r, the 3rd PMOS manages M _Dl, the 4th PMOS manages M _Dr, the 5th PMOS manages M _OlWith the 6th PMOS pipe M _OrForm; The one PMOS manages M _1lGrid connect input anode V _Ip, a PMOS manages M _1lSource electrode connect the anode V of first node _1pThe 2nd PMOS manages M _1rGrid meet input negative terminal V _In, the 2nd PMOS manages M _1rSource electrode connect the negative terminal V of first node _1nThe 3rd PMOS manages M _DlGrid meet bias voltage V _b, the 3rd PMOS manages M _DlSource electrode meet the anode V of first node _1pThe 4th PMOS manages M _DrGrid meet bias voltage V _b, the 4th PMOS manages M _DrSource electrode meet the negative terminal V of first node _1nThe 5th PMOS manages M _O1Grounded drain voltage GND, the 5th PMOS manages M _O1Grounded-grid voltage GND, the 5th PMOS manages M _O1Source electrode, a PMOS manage M _1lDrain electrode and the 3rd PMOS pipe M _D1Drain electrode link together; The 6th PMOS manages M _OrGrounded drain voltage GND, the 6th PMOS manages M _OrGrounded-grid voltage GND, the 6th PMOS manages M _OrSource electrode, the 2nd PMOS manage M _1rDrain electrode and the 4th PMOS pipe M _DrDrain electrode link together;

Described dummy cell 3 is by the 7th PMOS pipe M _11l, the 8th PMOS manages M _11r, the 9th PMOS pipe M and the tenth PMOS pipe form; The 7th PMOS manages M _11lGrid meet bias voltage V _b, the 7th PMOS manages M _11lSource electrode meet the anode V of output node _OpThe 8th PMOS manages M _11rGrid meet bias voltage V _b, the 8th PMOS manages M _11rSource electrode meet the negative terminal V of output node _OnThe 9th PMOS manages M _12lGrounded drain voltage GND, the 9th PMOS manages M _12lGrounded-grid voltage GND, the 9th PMOS manages M _12lSource electrode and the 7th PMOS pipe M _11lDrain electrode link to each other; The tenth PMOS manages M _12rGrounded drain voltage GND, the tenth PMOS manages M _12rGrounded-grid voltage GND, the tenth PMOS manages M _12rSource electrode and the 8th PMOS pipe M _11rDrain electrode link to each other;

Described active inductance unit 4 is by the 11 PMOS pipe M _2l, the 12 PMOS manages M _2r, the 13 PMOS manages M _6l, the 14 PMOS manages M _6r, the 15 PMOS manages M _10l, the 16 PMOS manages M _10r, the 17 PMOS manages V _3l, the 18 PMOS manages V _3r, the 19 PMOS manages V _5l, the 20 PMOS manages M _5r, the 21 PMOS manages M _7l, the 22 PMOS manages M _7r, the 23 PMOS manages M _9l, the 24 PMOS manages M _9r, the 25 PMOS manages M _4l, the 26 PMOS manages M _4r, the 27 PMOS manages M _8lWith the 28 PMOS pipe M _8rForm; The 11 PMOS manages M _2lDrain electrode meet the anode V of first node _1p, the 11 PMOS manages M _2lGrid meet the negative terminal V of first node _1n, the 11 PMOS manages M _2lSource electrode meet supply voltage VDD; The 12 PMOS manages M _2rDrain electrode meet the negative terminal V of first node _1n, the 12 PMOS manages M _2rGrid meet the anode V of first node _1p, the 12 PMOS manages M _2rSource electrode meet supply voltage VDD; The 13 PMOS manages M _6lDrain electrode meet the anode V of the 3rd node _3p, the 13 PMOS manages M _6lGrid meet the negative terminal V of the 3rd node _3n, the 13 PMOS manages M _6lSource electrode meet supply voltage VDD; The 14 PMOS manages M _6rDrain electrode meet the negative terminal V of the 3rd node _3n, the 14 PMOS manages M _6rGrid meet the anode V of the 3rd node _3p, the 14 PMOS manages M _6rSource electrode meet supply voltage VDD; The 15 PMOS manages M _10lDrain electrode meet the anode V of output node _Op, the 15 PMOS manages M _10lGrid meet the negative terminal V of output node _On, the 15 PMOS manages M _10lSource electrode meet supply voltage VDD; The 16 PMOS manages M _10rDrain electrode meet the negative terminal V of output node _On, the 16 PMOS manages M _10rGrid meet the anode V of output node _Op, the 16 PMOS manages M _10rSource electrode meet supply voltage VDD; The 17 PMOS manages V _3lDrain electrode meet the anode V of Section Point _2p, the 17 PMOS manages V _3lGrid meet the negative terminal V of Section Point _2n, the 17 PMOS manages V _3lSource electrode meet the anode V of first node _1pThe 18 PMOS manages V _3rDrain electrode meet the negative terminal V of Section Point _2n, the 18 PMOS manages V _3rGrid meet the anode V of Section Point _2p, the 18 PMOS manages V _3rSource electrode meet the negative terminal V of Section Point _2nThe 19 PMOS manages V _5lDrain electrode meet the anode V of Section Point _2p, the 19 PMOS manages V _5lGrid meet the negative terminal V of Section Point _2n, the 19 PMOS manages V _5lSource electrode meet the anode V of the 3rd node _3pThe 20 PMOS manages M _5rDrain electrode meet the negative terminal V of Section Point _2n, the 20 PMOS manages M _5rGrid meet the anode V of Section Point _2p, the 20 PMOS manages M _5rSource electrode meet the negative terminal V of the 3rd node _3nThe 21 PMOS manages M _7lDrain electrode meets the anode V of the 4th node _4p, the 21 PMOS manages M _7lGrid meet the negative terminal V of the 4th node _4n, the 21 PMOS manages M _7lSource electrode meet the anode V of the 3rd node _3pThe 22 PMOS manages M _7rDrain electrode meets the negative terminal V of the 4th node _4n, the 22 PMOS manages M _7rGrid meet the anode V of the 4th node _4p, the 22 PMOS manages M _7rSource electrode meet the negative terminal V of the 3rd node _3nThe 23 PMOS manages M _9lDrain electrode meet the anode V of the 4th node _4p, the 23 PMOS manages M _9lGrid meet the negative terminal V of the 4th node _4n, the 23 PMOS manages M _9lSource electrode meet the anode V of output node _5pThe 24 PMOS manages M _9rDrain electrode meet the negative terminal V of the 4th node _4n, the 24 PMOS manages M _9rGrid meet the anode V of the 4th node _4p, the 24 PMOS manages M _9rSource electrode meet the negative terminal V of output node _5nThe 25 PMOS manages M _4lDrain and gate earthed voltage GND, the 25 PMOS manages M _4lSource electrode meet the anode V of Section Point _2pThe 26 PMOS manages M _4rDrain and gate earthed voltage GND, the 26 PMOS manages M _4rSource electrode meet the negative terminal V of Section Point _2nThe 27 PMOS manages M _8lDrain and gate earthed voltage GND, the 27 PMOS manages M _8lSource electrode meet the anode V of the 4th node _4pThe 28 PMOS manages M _8rDrain and gate earthed voltage GND, the 28 PMOS manages M _8rSource electrode meet the negative terminal V of the 4th node _4n

On the basis of said structure, the present invention can be according to the gain requirement of using filter, and the width ratio of adjustment member PMOS pipe realizes different passband gains.For example: described PMOS pipe M _1lWidth (W ₁) manage M with the 3rd PMOS _DlWidth (W _d) sum equals the 7th PMOS pipe M _11lWidth (W ₁₁); Described the 2nd PMOS pipe M _1rWidth (W ₁) manage M with the 4th PMOS _DrWidth (W _d) sum equals the 8th PMOS pipe M _11rWidth (W ₁₁); The 7th PMOS manages M _11l, the 8th PMOS manages M _11r, the 17 PMOS manages V _3l, the 18 PMOS manages V _3r, the 19 PMOS manages V _5l, the 20 PMOS manages M _5r, the 21 PMOS manages M _7l, the 22 PMOS manages M _7r, the 23 PMOS manages M _9lWith the 24 PMOS pipe M _9rWidth all equate.

The another kind that the present invention proposes as shown in Figure 4, is characterized in that based on the active low-pass filter of positive feedback inductance method of substitution, adopts full NMOS pipe to realize,, this active low-pass filter comprises:

Capacitor cell 1 is used for comprehensive low-frequency filter characteristics;

Input unit 2 is used in voltage domain converted input signal;

Dummy cell 3 is used for balance output common mode level and ghost effect;

Active inductance unit 4 is used to realize the active inductance based on positive feedback; Each unit with dashed lines collimation mark respectively goes out;

Wherein, described capacitor cell 1 is by first capacitor C ₁, second capacitor C ₂, the 3rd capacitor C ₃, the 4th capacitor C ₄With the 5th capacitor C ₅Form second capacitor C ₂With the 4th capacitor C ₄Be used for the conversion active inductance; Wherein, first capacitor C ₁Positive pole meet the anode V of first node _1p, first capacitor C ₁Negative pole meet the negative terminal V of first node _1nSecond capacitor C ₂Positive pole meet the anode V of Section Point _2p, second capacitor C ₂Negative pole meet the negative terminal V of Section Point _2nThe 3rd capacitor C ₃Positive pole meet the anode V of the 3rd node _3p, the 3rd capacitor C ₃Negative pole meet the negative terminal V of the 3rd node _3nThe 4th capacitor C ₄Positive pole meet the anode V of the 4th node _4p, the 4th capacitor C ₄Negative pole meet the negative terminal V of the 4th node _4nThe 5th capacitor C ₅Positive pole meet the anode V of output node _Op, the 5th capacitor C ₅Negative pole meet the negative terminal V of output node _On

Described input unit 2 is by NMOS pipe M _1l, the 2nd NMOS manages M _1r, the 3rd NMOS manages M _Dl, the 4th NMOS manages M _Dr, the 5th NMOS manages M _OlWith the 6th NMOS pipe M _OrForm; The one NMOS manages M _1lGrid connect input anode V _Ip, a NMOS manages M _1lSource electrode connect the anode V of first node _1pThe 2nd NMOS manages M _1rGrid meet input negative terminal V _In, the 2nd NMOS manages M _1rSource electrode connect the negative terminal V of first node _1nThe 3rd NMOS manages M _DlGrid meet bias voltage V _b, the 3rd NMOS manages M _DlSource electrode meet the anode V of first node _1pThe 4th NMOS manages M _DrGrid meet bias voltage V _b, the 4th PMOS manages M _DrSource electrode meet the negative terminal V of first node _1nThe 5th PMOS manages M _O1Drain electrode meet supply voltage VDD, the 5th NMOS manages M _O1Grid meet supply voltage VDD, the 5th NMOS manages M _O1Source electrode, a NMOS manage M _1lDrain electrode and the 3rd NMOS pipe M _D1Drain electrode link together; The 6th NMOS manages M _OrDrain electrode meet supply voltage VDD, the 6th NMOS manages M _OrGrid meet supply voltage VDD, the 6th NMOS manages M _OrSource electrode, the 2nd NMOS manage M _1rDrain electrode and the 4th NMOS pipe M _DrDrain electrode link together.

Described dummy cell 3 is by the 7th NMOS pipe M _11l, the 8th NMOS manages M _11r, the 9th NMOS pipe M and the tenth NMOS pipe form; The 7th NMOS manages M _11lGrid meet bias voltage V _b, the 7th NMOS manages M _11lSource electrode meet the anode V of output node _OpThe 8th NMOS manages M _11rGrid meet bias voltage V _b, the 8th NMOS manages M _11rSource electrode meet the negative terminal V of output node _OnThe 9th NMOS manages M _12lDrain electrode meet supply voltage VDD, the 9th NMOS manages M _12lGrid meet supply voltage VDD, the 9th NMOS manages M _12lSource electrode and the 7th NMOS pipe M _11lDrain electrode link to each other; The tenth NMOS manages M _12rDrain electrode meet supply voltage VDD, the tenth NMOS manages M _12rGrid meet supply voltage VDD, the tenth NMOS manages M _12rSource electrode and the 8th NMOS pipe M _11rDrain electrode link to each other.

Described active inductance unit 4 is by the 11 NMOS pipe M _2l, the 12 NMOS manages M _2r, the 13 NMOS manages M _6l, the 14 NMOS manages M _6r, the 15 NMOS manages M _10l, the 16 NMOS manages M _10r, the 17 NMOS manages V _3l, the 18 NMOS manages V _3r, the 19 NMOS manages V _5l, the 20 NMOS manages M _5r, the 21 NMOS manages M _7l, the 22 NMOS manages M _7r, the 23 NMOS manages M _9l, the 24 NMOS manages M _9r, the 25 NMOS manages M _4l, the 26 NMOS manages M _4r, the 27 NMOS manages M _8lWith the 28 NMOS pipe M _8rForm; The 11 NMOS manages M _2lDrain electrode meet the anode V of first node _1p, the 11 NMOS manages M _2lGrid meet the negative terminal V of first node _1n, the 11 NMOS manages M _2lSource ground voltage GND; The 12 NMOS manages M _2rDrain electrode meet the negative terminal V of first node _1n, the 12 NMOS manages M _2rGrid meet the anode V of first node _1p, the 12 NMOS manages M _2rSource ground voltage GND; The 13 NMOS manages M _6lDrain electrode meet the anode V of the 3rd node _3p, the 13 NMOS manages M _6lGrid meet the negative terminal V of the 3rd node _3n, the 13 NMOS manages M _6lSource ground voltage GND; The 14 NMOS manages M _6rDrain electrode meet the negative terminal V of the 3rd node _3n, the 14 NMOS manages M _6rGrid meet the anode V of the 3rd node _3p, the 14 NMOS manages M _6rSource ground voltage GND; The 15 NMOS manages M _10lDrain electrode meet the anode V of output node _Op, the 15 NMOS manages M _10lGrid meet the negative terminal V of output node _On, the 15 NMOS manages M _10lSource ground voltage GND; The 16 NMOS manages M _10rDrain electrode meet the negative terminal V of output node _On, the 16 NMOS manages M _10rGrid meet the anode V of output node _Op, the 16 NMOS manages M _10rSource ground voltage GND; The 17 NMOS manages V _3lDrain electrode meet the anode V of Section Point _2p, the 17 NMOS manages V _3lGrid meet the negative terminal V of Section Point _2n, the 17 NMOS manages V _3lSource electrode meet the anode V of first node _1pThe 18 NMOS manages V _3rDrain electrode meet the negative terminal V of Section Point _2n, the 18 NMOS manages V _3rGrid meet the anode V of Section Point _2p, the 18 NMOS manages V _3rSource electrode meet the negative terminal V of Section Point _2nThe 19 NMOS manages V _5lDrain electrode meet the anode V of Section Point _2p, the 19 NMOS manages V _5lGrid meet the negative terminal V of Section Point _2n, the 19 NMOS manages V _5lSource electrode meet the anode V of the 3rd node _3pThe 20 NMOS manages M _5rDrain electrode meet the negative terminal V of Section Point _2n, the 20 NMOS manages M _5rGrid meet the anode V of Section Point _2p, the 20 NMOS manages M _5rSource electrode meet the negative terminal V of the 3rd node _3nThe 21 NMOS manages M _7lDrain electrode meets the anode V of the 4th node _4p, the 21 NMOS manages M _7lGrid meet the negative terminal V of the 4th node _4n, the 21 NMOS manages M _7lSource electrode meet the anode V of the 3rd node _3pThe 22 NMOS manages M _7rDrain electrode meets the negative terminal V of the 4th node _4n, the 22 NMOS manages M _7rGrid meet the anode V of the 4th node _4p, the 22 NMOS manages M _7rSource electrode meet the negative terminal V of the 3rd node _3nThe 23 NMOS manages M _9lDrain electrode meet the anode V of the 4th node _4p, the 23 NMOS manages M _9lGrid meet the negative terminal V of the 4th node _4n, the 23 NMOS manages M _9lSource electrode meet the anode V of output node _OpThe 24 NMOS manages M _9rDrain electrode meet the negative terminal V of the 4th node _4n, the 24 NMOS manages M _9rGrid meet the anode V of the 4th node _4p, the 24 NMOS manages M _9rSource electrode meet the negative terminal V of output node _OnThe 25 NMOS manages M _4lDrain and gate meet supply voltage VDD, the 25 NMOS manages M _4lSource electrode meet the anode V of Section Point _2pThe 26 NMOS manages M _4rDrain and gate meet supply voltage VDD, the 26 NMOS manages M _4rSource electrode meet the negative terminal V of Section Point _2nThe 27 NMOS manages M _8lDrain and gate meet supply voltage VDD, the 27 NMOS manages M _8lSource electrode meet the anode V of the 4th node _4pThe 28 NMOS manages M _8rDrain and gate meet supply voltage VDD, the 28 BMOS manages M _8rSource electrode meet the negative terminal V of the 4th node _4n

On the basis of said structure, the present invention can be according to the gain requirement of using filter, and the width ratio of adjustment member NMOS pipe realizes different passband gains.For example: described NMOS pipe M _1lWidth (W ₁) manage M with the 3rd NMOS _DlWidth (W _d) sum equals the 7th NMOS pipe M _11lWidth (W ₁₁); Described the 2nd NMOS pipe M _1rWidth (W ₁) manage M with the 4th NMOS _DrWidth (W _d) sum equals the 8th NMOS pipe M _11rWidth (W ₁₁); The 7th NMOS manages M _11l, the 8th NMOS manages M _11r, the 17 NMOS manages V _3l, the 18 NMOS manages V _3r, the 19 NMOS manages V _5l, the 20 NMOS manages M _5r, the 21 NMOS manages M _7l, the 22 NMOS manages M _7r, the 23 NMOS manages M _9lWith the 24 NMOS pipe M _9rWidth all equate.

Active low-pass filter based on positive feedback inductance method of substitution of the present invention, different with tradition based on the negative feedback inductor method of substitution, realize inductance method of substitution design high-order active low-pass filter based on positive feedback technique; Can realize that symmetrical configuration is simple by less transistor, be easy to design.

The present invention also can be by rationally setting transistorized size, under various process corner, make first node to the positive mutual conductance summation (comprising parasitic mutual conductance) of output point greater than corresponding negative transconductance, so just can guarantee the stability of circuit; Adopt current multiplexing technology and voltage domain Analog signals, realized under low-power consumption, obtaining high linearity; Compare with the cascade method design high-order active low-pass filter based on double-two-order unit, it is very little to have adopted the inductance method of substitution to make it influenced by process deviation; Also can be according to the gain requirement of using to filter, the ratio of the width of PMOS pipe and the 3rd PMOS pipe, the 2nd PMOS pipe and the 4th PMOS pipe realizes different passband gains in the adjustment importation.

Below introduce the result who the active low-pass filter based on positive feedback inductance method of substitution of the present invention is carried out simulating, verifying:

Based on 5 rank passive electrical inductance-capacitance filter prototypes, adopt CMOS 90nm technology that the active low-pass filter based on positive feedback inductance method of substitution that the present invention shown in Figure 3 proposes is designed, to verify correctness of the present invention.The curve of describing among Fig. 5 is the amplitude transmission curve based on the active low-pass filter of positive feedback inductance method of substitution among Fig. 3, and the vertical coordinate axle of this curve chart and horizontal axis represent with dB to be the amplitude and the correspondent frequency (MHz) of unit respectively.Know from this curve: (1) passband gain is-3.14dB; (2) three dB bandwidth is 60MHz; (3) realize the outer 5 rank filter characteristics of band.The design's power consumption consumes 3mW, and the IIP3 linearity is 13dBm in the band.

By changing the PMOS pipe in the importation and the 3rd PMOS pipe, the 2nd PMOS manage and the ratio of the width of the 4th PMOS pipe, as shown in table 1, obtain different passband gains.Width (W along with pipe of the PMOS in the importation and the 2nd PMOS pipe ₁) ratio constantly increase, the passband gain of low pass filter constantly increases, and multiple input signals is just arranged more by follow-up processing of circuit.

Table 1: the passband gain that the transistorized width ratio of transistor importation and illusory part is different and emulation obtains among Fig. 3

Transistorized width	W 1	W d	W 11	Gain (dB) in the band
					1 ratio	0.1	0.9	1	-23.3
2 ratios	0.3	0.7	1	-12.2
					3 ratios	0.7	0.3	1	-6.1
4 ratios	0.9	0.1	1	-3.1

Active low-pass filter based on positive feedback inductance method of substitution of the present invention can also be replaced whole NPN bipolar tube, perhaps whole PNP bipolar tube with the whole PMOS transistors among Fig. 3.The high-order active low-pass filter of all right other exponent numbers of while technical solutions according to the invention.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. the active low-pass filter based on positive feedback inductance method of substitution is characterized in that, adopts full PMOS pipe to realize that this active low-pass filter comprises:

Capacitor cell is used for comprehensive low-frequency filter characteristics;

Input unit is used in voltage domain converted input signal;

Dummy cell is used for balance output common mode level and ghost effect;

The active inductance unit is used to realize the active inductance based on positive feedback;

Wherein, described capacitor cell is by the first electric capacity (C ₁), the second electric capacity (C ₂), the 3rd electric capacity (C ₃), the 4th electric capacity (C ₄) and the 5th electric capacity (C ₅) form the second electric capacity (C ₂) and the 4th electric capacity (C ₄) be used for the conversion active inductance; Wherein, the first electric capacity (C ₁) positive pole meet the anode (V of first node _1p), the first electric capacity (C ₁) negative pole meet the negative terminal (V of first node _1n); Second electric capacity (the C ₂) positive pole meet the anode (V of Section Point _2p), the second electric capacity (C ₂) negative pole meet the negative terminal (V of Section Point _2n); The 3rd electric capacity (C ₃) positive pole meet the anode (V of the 3rd node _3p), the negative pole of the 3rd electric capacity (C3) meets the negative terminal (V of the 3rd node _3n); The 4th electric capacity (C ₄) positive pole meet the anode (V of the 4th node _4p), the 4th electric capacity (C ₄) negative pole meet the negative terminal (V of the 4th node _4n); The 5th electric capacity (C ₅) positive pole meet the anode (V of output node _Op), the 5th electric capacity (C ₅) negative pole meet the negative terminal (V of output node _On);

Described input unit is by PMOS pipe (M _1l), the 2nd PMOS manages (M _1r), the 3rd PMOS manages (M _Dl), the 4th PMOS manages (M _Dr), the 5th PMOS manages (M _Ol) and the 6th PMOS pipe (M _Or) form; The one PMOS manages (M _1l) grid connect input anode (V _Ip), a PMOS manages (M _1l) source electrode connect the anode (V of first node _1p); The 2nd PMOS manages (M _1r) grid meet input negative terminal (V _In), the 2nd PMOS manages (M _1r) source electrode connect the negative terminal (V of first node _1n); The 3rd PMOS manages (M _Dl) grid meet bias voltage (V _b), the 3rd PMOS manages (M _Dl) source electrode meet the anode (V of first node _1p); The 4th PMOS manages (M _Dr) grid meet bias voltage (V _b), the 4th PMOS manages (M _Dr) source electrode meet the negative terminal (V of first node _1n); The 5th PMOS manages (M _O1) grounded drain voltage (GND), the 5th PMOS manages (M _O1) grounded-grid voltage (GND), the 5th PMOS manages (M _O1) source electrode, a PMOS manage (M _1l) drain electrode and the 3rd PMOS pipe (M _D1) drain electrode link together; The 6th PMOS manages (M _Or) grounded drain voltage (GND), the 6th PMOS manages (M _Or) grounded-grid voltage (GND), the 6th PMOS manages (M _Or) source electrode, the 2nd PMOS manage (M _1r) drain electrode and the 4th PMOS pipe (M _Dr) drain electrode link together;

Described dummy cell is by the 7th PMOS pipe (M _11l), the 8th PMOS manages (M _11r), the 9th PMOS manages (M _12l) and the tenth PMOS pipe (M _12r) form; The 7th PMOS manages (M _11l) grid meet bias voltage (V _b), the 7th PMOS manages (M _11l) source electrode meet the anode (V of output node _Op); The 8th PMOS manages (M _11r) grid meet bias voltage (V _b), the 8th PMOS manages (M _11r) source electrode meet the negative terminal (V of output node _On); The 9th PMOS manages (M _12l) grounded drain voltage (GND), the 9th PMOS manages (M _12l) grounded-grid voltage (GND), the 9th PMOS manages (M _12l) source electrode and the 7th PMOS pipe (M _11l) drain electrode link to each other; The tenth PMOS manages (M _12r) grounded drain voltage (GND), the tenth PMOS manages (M _12r) grounded-grid voltage (GND), the tenth PMOS manages (M _12r) source electrode and the 8th PMOS pipe (M _11r) drain electrode link to each other;

Described active inductance unit is by the 11 PMOS pipe (M _2l), the 12 PMOS manages (M _2r), the 13 PMOS manages (M _6l), the 14 PMOS manages (M _6r), the 15 PMOS manages (M _10l), the 16 PMOS manages (M _10r), the 17 PMOS manages (V _3l), the 18 PMOS manages (V _3r), the 19 PMOS manages (V _5l), the 20 PMOS manages (M _5r), the 21 PMOS manages (M _7l), the 22 PMOS manages (M _7r), the 23 PMOS manages (M _9l), the 24 PMOS manages (M _9r), the 25 PMOS manages (M _4l), the 26 PMOS manages (M _4r), the 27 PMOS manages (M _8l) and the 28 PMOS pipe (M _8r) form; The 11 PMOS manages (M _2l) drain electrode meet the anode (V of first node _1p), the 11 PMOS manages (M _2l) grid meet the negative terminal (V of first node _1n), the 11 PMOS manages (M _2l) source electrode connect supply voltage (VDD); The 12 PMOS manages (M _2r) drain electrode meet the negative terminal (V of first node _1n), the 12 PMOS manages (M _2r) grid meet the anode (V of first node _1p), the 12 PMOS manages (M _2r) source electrode connect supply voltage (VDD); The 13 PMOS manages (M _6l) drain electrode meet the anode (V of the 3rd node _3p), the 13 PMOS manages (M _6l) grid meet the negative terminal (V of the 3rd node _3n), the 13 PMOS manages (M _6l) source electrode connect supply voltage (VDD); The 14 PMOS manages (M _6r) drain electrode meet the negative terminal (V of the 3rd node _3n), the 14 PMOS manages (M _6r) grid meet the anode (V of the 3rd node _3p), the 14 PMOS manages (M _6r) source electrode connect supply voltage (VDD); The 15 PMOS manages (M _10l) drain electrode meet the anode (V of output node _Op), the 15 PMOS manages (M _10l) grid meet the negative terminal (V of output node _On), the 15 PMOS manages (M _10l) source electrode connect supply voltage (VDD); The 16 PMOS manages (M _10r) drain electrode meet the negative terminal (V of output node _On), the 16 PMOS manages (M _10r) grid meet the anode (V of output node _Op), the 16 PMOS manages (M _10r) source electrode connect supply voltage (VDD); The 17 PMOS manages (V _3l) drain electrode meet the anode (V of Section Point _2p), the 17 PMOS manages (V _3l) grid meet the negative terminal (V of Section Point _2n), the 17 PMOS manages (V _3l) source electrode meet the anode (V of first node _1p); The 18 PMOS manages (V _3r) drain electrode meet the negative terminal (V of Section Point _2n), the 18 PMOS manages (V _3r) grid meet the anode (V of Section Point _2p), the 18 PMOS manages (V _3r) source electrode meet the negative terminal (V of Section Point _2n); The 19 PMOS manages (V _5l) drain electrode meet the anode (V of Section Point _2p), the 19 PMOS manages (V _5l) grid meet the negative terminal (V of Section Point _2n), the 19 PMOS manages (V _5l) source electrode meet the anode (V of the 3rd node _3p); The 20 PMOS manages (M _5r) drain electrode meet the negative terminal (V of Section Point _2n), the 20 PMOS manages (M _5r) grid meet the anode (V of Section Point _2p), the 20 PMOS manages (M _5r) source electrode meet the negative terminal (V of the 3rd node _3n); The 21 PMOS manages (M _7l) draining meets the anode (V of the 4th node _4p), the 21 PMOS manages (M _7l) grid meet the negative terminal (V of the 4th node _4n), the 21 PMOS manages (M _7l) source electrode meet the anode (V of the 3rd node _3p); The 22 PMOS manages (M _7r) draining meets the negative terminal (V of the 4th node _4n), the 22 PMOS manages (M _7r) grid meet the anode (V of the 4th node _4p), the 22 PMOS manages (M _7r) source electrode meet the negative terminal (V of the 3rd node _3n); The 23 PMOS manages (M _9l) drain electrode meet the anode (V of the 4th node _4p), the 23 PMOS manages (M _9l) grid meet the negative terminal (V of the 4th node _4n), the 23 PMOS manages (M _9l) source electrode meet the anode (V of output node _5p); The 24 PMOS manages (M _9r) drain electrode meet the negative terminal (V of the 4th node _4n), the 24 PMOS manages (M _9r) grid meet the anode (V of the 4th node _4p), the 24 PMOS manages (M _9r) source electrode meet the negative terminal (V of output node _5n); The 25 PMOS manages (M _4l) drain and gate earthed voltage (GND), the 25 PMOS manages (M _4l) source electrode meet the anode (V of Section Point _2p); The 26 PMOS manages (M _4r) drain and gate earthed voltage (GND), the 26 PMOS manages (M _4r) source electrode meet the negative terminal (V of Section Point _2n); The 27 PMOS manages (M _8l) drain and gate earthed voltage (GND), the 27 PMOS manages (M _8l) source electrode meet the anode (V of the 4th node _4p); The 28 PMOS manages (M _8r) drain and gate earthed voltage (GND), the 28 PMOS manages (M _8r) source electrode meet the negative terminal (V of the 4th node _4n).

2. active low-pass filter as claimed in claim 1 is characterized in that, described PMOS pipe (M _1l) width and the 3rd PMOS pipe (M _Dl) the width sum equal the 7th PMOS pipe (M _11l) width; Described the 2nd PMOS pipe (M _1r) width and the 4th PMOS pipe (M _Dr) the width sum equal the 8th PMOS pipe (M _11r) width; The 7th PMOS manages (M _11l), the 8th PMOS manages (M _11r), the 17 PMOS manages (V _3l), the 18 PMOS manages (V _3r), the 19 PMOS manages (V _5l), the 20 PMOS manages (M _5r), the 21 PMOS manages (M _7l), the 22 PMOS manages (M _7r), the 23 PMOS manages (M _9l) and the 24 PMOS pipe (M _9r) width all equate.

3. the active low-pass filter based on positive feedback inductance method of substitution is characterized in that, adopts full NMOS pipe to realize that this active low-pass filter comprises:

Capacitor cell is used for comprehensive low-frequency filter characteristics;

Input unit is used in voltage domain converted input signal;

Dummy cell is used for balance output common mode level and ghost effect;

The active inductance unit is used to realize the active inductance based on positive feedback;

Wherein, described capacitor cell is by the first electric capacity (C ₁), the second electric capacity (C ₂), the 3rd electric capacity (C ₃), the 4th electric capacity (C ₄) and the 5th electric capacity (C ₅) form the second electric capacity (C ₂) and the 4th electric capacity (C ₄) be used for the conversion active inductance; Wherein, the first electric capacity (C ₁) positive pole meet the anode (V of first node _1p), the first electric capacity (C ₁) negative pole meet the negative terminal (V of first node _1n); Second electric capacity (the C ₂) positive pole meet the anode (V of Section Point _2p), the second electric capacity (C ₂) negative pole meet the negative terminal (V of Section Point _2n); The 3rd electric capacity (C ₃) positive pole meet the anode (V of the 3rd node _3p), the 3rd electric capacity (C ₃) negative pole meet the negative terminal (V of the 3rd node _3n); The 4th electric capacity (C ₄) positive pole meet the anode (V of the 4th node _4p), the negative pole of the 4th electric capacity (C4) meets the negative terminal (V of the 4th node _4n); The 5th electric capacity (C ₅) positive pole meet the anode (V of output node _Op), the 5th electric capacity (C ₅) negative pole meet the negative terminal (V of output node _On);

Described input unit is by NMOS pipe (M _1l), the 2nd NMOS manages (M _1r), the 3rd NMOS manages (M _Dl), the 4th NMOS manages (M _Dr), the 5th NMOS manages (M _Ol) and the 6th NMOS pipe (M _Or) form; The one NMOS manages (M _1l) grid connect input anode (V _Ip), a NMOS manages (M _1l) source electrode connect the anode (V of first node _1p); The 2nd NMOS manages (M _1r) grid meet input negative terminal (V _In), the 2nd NMOS manages (M _1r) source electrode connect the negative terminal (V of first node _1n); The 3rd NMOS manages (M _Dl) grid meet bias voltage (V _b), the 3rd NMOS manages (M _Dl) source electrode meet the anode (V of first node _1p); The 4th NMOS manages (M _Dr) grid meet bias voltage (V _b), the 4th PMOS manages (M _Dr) source electrode meet the negative terminal (V of first node _1n); The 5th PMOS manages (M _O1) drain electrode connect supply voltage (VDD), the 5th NMOS manages (M _O1) grid connect supply voltage (VDD), the 5th NMOS manages (M _O1) source electrode, a NMOS manage (M _1l) drain electrode and the 3rd NMOS pipe (M _D1) drain electrode link together; The 6th NMOS manages (M _Or) drain electrode connect supply voltage (VDD), the 6th NMOS manages (M _Or) grid connect supply voltage (VDD), the 6th NMOS manages (M _Or) source electrode, the 2nd NMOS manage (M _1r) drain electrode and the 4th NMOS pipe (M _Dr) drain electrode link together;

Described dummy cell is by the 7th NMOS pipe (M _11l), the 8th NMOS manages (M _11r), the 9th NMOS manages (M _12l) and the tenth NMOS pipe (M _12r) form; The 7th NMOS manages (M _11l) grid meet bias voltage (V _b), the 7th NMOS manages (M _11l) source electrode meet the anode (V of output node _Op); The 8th NMOS manages (M _11r) grid meet bias voltage (V _b), the 8th NMOS manages (M _11r) source electrode meet the negative terminal (V of output node _On); The 9th NMOS manages (M _12l) drain electrode connect supply voltage (VDD), the 9th NMOS manages (M _12l) grid connect supply voltage (VDD), the 9th NMOS manages (M _12l) source electrode and the 7th NMOS pipe (M _11l) drain electrode link to each other; The tenth NMOS manages (M _12r) drain electrode connect supply voltage (VDD), the tenth NMOS manages (M _12r) grid connect supply voltage (VDD), the tenth NMOS manages (M _12r) source electrode and the 8th NMOS pipe (M _11r) drain electrode link to each other;

Described active inductance unit is by the 11 NMOS pipe (M _2l), the 12 NMOS manages (M _2r), the 13 NMOS manages (M _6l), the 14 NMOS manages (M _6r), the 15 NMOS manages (M _10l), the 16 NMOS manages (M _10r), the 17 NMOS manages (V _3l), the 18 NMOS manages (V _3r), the 19 NMOS manages (V _5l), the 20 NMOS manages (M _5r), the 21 NMOS manages (M _7l), the 22 NMOS manages (M _7r), the 23 NMOS manages (M _9l), the 24 NMOS manages (M _9r), the 25 NMOS manages (M _4l), the 26 NMOS manages (M _4r), the 27 NMOS manages (M _8l) and the 28 NMOS pipe (M _8r) form; The 11 NMOS manages (M _2l) drain electrode meet the anode (V of first node _1p), the 11 NMOS manages (M _2l) grid meet the negative terminal (V of first node _1n), the 11 NMOS manages (M _2l) source ground voltage (GND); The 12 NMOS manages (M _2r) drain electrode meet the negative terminal (V of first node _1n), the 12 NMOS manages (M _2r) grid meet the anode (V of first node _1p), the 12 NMOS manages (M _2r) source ground voltage (GND); The 13 NMOS manages (M _6l) drain electrode meet the anode (V of the 3rd node _3p), the 13 NMOS manages (M _6l) grid meet the negative terminal (V of the 3rd node _3n), the 13 NMOS manages (M _6l) source ground voltage (GND); The 14 NMOS manages (M _6r) drain electrode meet the negative terminal (V of the 3rd node _3n), the 14 NMOS manages (M _6r) grid meet the anode (V of the 3rd node _3p), the 14 NMOS manages (M _6r) source ground voltage (GND); The 15 NMOS manages (M _10l) drain electrode meet the anode (V of output node _Op), the 15 NMOS manages (M _10l) grid meet the negative terminal (V of output node _On), the 15 NMOS manages (M _10l) source ground voltage (GND); The 16 NMOS manages (M _10r) drain electrode meet the negative terminal (V of output node _On), the 16 NMOS manages (M _10r) grid meet the anode (V of output node _Op), the 16 NMOS manages (M _10r) source ground voltage (GND); The 17 NMOS manages (V _3l) drain electrode meet the anode (V of Section Point _2p), the 17 NMOS manages (V _3l) grid meet the negative terminal (V of Section Point _2n), the 17 NMOS manages (V _3l) source electrode meet the anode (V of first node _1p); The 18 NMOS manages (V _3r) drain electrode meet the negative terminal (V of Section Point _2n), the 18 NMOS manages (V _3r) grid meet the anode (V of Section Point _2p), the 18 NMOS manages (V _3r) source electrode meet the negative terminal (V of Section Point _2n); The 19 NMOS manages (V _5l) drain electrode meet the anode (V of Section Point _2p), the 19 NMOS manages (V _5l) grid meet the negative terminal (V of Section Point _2n), the 19 NMOS manages (V _5l) source electrode meet the anode (V of the 3rd node _3p); The 20 NMOS manages (M _5r) drain electrode meet the negative terminal (V of Section Point _2n), the 20 NMOS manages (M _5r) grid meet the anode (V of Section Point _2p), the 20 NMOS manages (M _5r) source electrode meet the negative terminal (V of the 3rd node _3n); The 21 NMOS manages (M _7l) draining meets the anode (V of the 4th node _4p), the 21 NMOS manages (M _7l) grid meet the negative terminal (V of the 4th node _4n), the 21 NMOS manages (M _7l) source electrode meet the anode (V of the 3rd node _3p); The 22 NMOS manages (M _7r) draining meets the negative terminal (V of the 4th node _4n), the 22 NMOS manages (M _7r) grid meet the anode (V of the 4th node _4p), the 22 NMOS manages (M _7r) source electrode meet the negative terminal (V of the 3rd node _3n); The 23 NMOS manages (M _9l) drain electrode meet the anode (V of the 4th node _4p), the 23 NMOS manages (M _9l) grid meet the negative terminal (V of the 4th node _4n), the 23 NMOS manages (M _9l) source electrode meet the anode (V of output node _Op); The 24 NMOS manages (M _9r) drain electrode meet the negative terminal (V of the 4th node _4n), the 24 NMOS manages (M _9r) grid meet the anode (V of the 4th node _4p), the 24 NMOS manages (M _9r) source electrode meet the negative terminal (V of output node _On); The 25 NMOS manages (M _4l) drain and gate connect supply voltage (VDD), the 25 NMOS manages (M _4l) source electrode meet the anode (V of Section Point _2p); The 26 NMOS manages (M _4r) drain and gate connect supply voltage (VDD), the 26 NMOS manages (M _4r) source electrode meet the negative terminal (V of Section Point _2n); The 27 NMOS manages (M _8l) drain and gate connect supply voltage (VDD), the 27 NMOS manages (M _8l) source electrode meet the anode (V of the 4th node _4p); The 28 NMOS manages (M _8r) drain and gate connect supply voltage (VDD), the 28 BMOS manages (M _8r) source electrode meet the negative terminal (V of the 4th node _4n).

4. active low-pass filter as claimed in claim 3 is characterized in that, described NMOS pipe (M _1l) width and the 3rd NMOS pipe (M _Dl) the width sum equal the 7th NMOS pipe (M _11l) width; Described the 2nd NMOS pipe (M _1r) width and the 4th NMOS pipe (M _Dr) the width sum equal the 8th NMOS pipe (M _11r) width; The 7th NMOS manages (M _11l), the 8th NMOS manages (M _11r), the 17 NMOS manages (V _3l), the 18 NMOS manages (V _3r), the 19 NMOS manages V _5l), the 20 NMOS manages (M _5r), the 21 NMOS manages (M _7l), the 22 NMOS manages (M _7r), the 23 NMOS manages (M _9l) and the 24 NMOS pipe (M _9r) width all equate.

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