CN102111123A - Suspension difference active inducer based on positive feedback - Google Patents

Abstract

The invention relates to a suspension differential active inductance based on positive feedback, and belongs to the technical field of active inductance design. Including: differential impedance converter, including two pairs of positive feedback-based differential impedance converters and two capacitors composed of two pairs of cross-connected PMOS transistors, through two pairs of differential impedance converters, the two capacitors are transformed into floating differential active inductance ; The positive transconductance stabilizer, including two PMOS transistors, compensates the negative impedance of the impedance converter, and solves the stability problem of the active inductance; the negative transconductance canceller, including two pairs of cross-connected PMOS transistors, offsets the active inductance shunt impedance. The suspended differential active inductor of the present invention adopts the current multiplexing technology, is only composed of PMOS transistors, has a simple and symmetrical structure, and is easy to design for changing high and low quality factors (Q). It is used to replace the floating differential passive inductance, especially for the active filter design by the inductance substitution method.

Description

A kind of suspension difference active inductance based on positive feedback

Technical field

The present invention relates to a kind of suspension difference active inductance, belong to the active inductance design field based on positive feedback.

Background technology

Filter is requisite module in the various communication systems, for example intermediate-frequency filter in the radio frequency transceiver.Provided the single-ended structure of a kind of three rank among Fig. 1 (a), wherein passive inductance two ends V based on inductance capacitance ladder-type filter (LC Ladder Filter) ₁And V ₂Can be homophase, at this moment passive inductance be the single-ended connected mode that suspends.Fig. 1 (b) has provided the corresponding differential configuration of Fig. 1 (a), mainly is because differential configuration helps improving the linearity and suppresses common-mode noise.Suspending between first port of passive inductance and second port connects, and each port is again a differential configuration, the corresponding V of the first port anode and the first port negative terminal _1pAnd V _1n, the corresponding V of the second port anode and the second port negative terminal _2pAnd V _2n, at this moment passive inductance is a suspension difference connected mode, shown in Fig. 1 (c).

On silica-based technology, the metal spiral inductance that passive inductance normally forms on silicon-based substrate.Though spiral inductance is simple in structure, take bigger chip area, the influence that is subjected to silicon-based substrate loss and conductor losses makes the quality factor of spiral inductance and self-resonant frequency all very low.And characteristics such as active inductance is little because of chip occupying area, high quality factor are more favored.The realization of active inductance mainly adopts active transistor and passive component to simulate passive inductance characteristic.At present, employing realizes active inductance altogether based on degenerative impedance transformer and capacitance group.Fig. 2 provided corresponding diagram 3 based on degenerative suspension difference active inductance, be used for replacing the passive inductance of suspension difference of Fig. 3.

For shown in Figure 2 based on the transconductance cell in the degenerative suspension difference active inductance, with Nauta differential transconductance (Bram Nauta shown in Figure 3, " A CMOS Transconductance-C Filter Technique for Very HighFrequencies " IEEE JOURNAL 0F SOLID-STATE CIRCUITS, VOL.27, N0.2.FEBRUARY 1992) be example.Positive mutual conductance is made up of four transistors; Negative transconductance is used to improve DC current gain; Four transistors that diode connects are used for determining output common mode voltage.Even only consider the positive mutual conductance that four transistors constitute; shown in Figure 2 needs 16 transistors based on degenerative suspension difference active inductance; other consider required transistor size in addition; usually need ten above transistors based on degenerative suspension fully differential active inductance; make that traditional suspension difference active inductance design is complicated, complicated based on height quality factor (Q) the variation design of degenerative suspension difference active inductance simultaneously.

Summary of the invention

The objective of the invention is to propose a kind of suspension difference active inductance, be used to replace the passive inductance of suspension difference, to be used for inductance method of substitution design active filter based on positive feedback.

The suspension difference active inductance based on positive feedback that the present invention proposes comprises:

The differential impedance converter, the electric capacity that is used for inductance that first electric capacity and second electric capacity are produced is transformed into the active inductance of suspension difference; The differential impedance converter by a PMOS manage, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe, first electric capacity and second electric capacity forms; The grid of the one PMOS pipe links to each other with the drain electrode of the 2nd PM0S pipe, and the drain electrode of a PMOS pipe links to each other with the grid of the 2nd PMOS pipe; The grid of the 2nd PM0S pipe links to each other with the drain electrode of the 3rd PMOS pipe, and the drain electrode of the 2nd PMOS pipe links to each other with the grid of the 3rd PMOS pipe, and the grid of the 3rd PMOS pipe links to each other with the drain electrode of the 4th PMOS pipe, and the drain electrode of the 3rd PMOS pipe links to each other with the grid of the 4th PMOS pipe;

First electric capacity and second electric capacity, be used to produce inductance, the anodal of first electric capacity links to each other the minus earth of first electric capacity with the drain electrode of the grid of the drain electrode of an above-mentioned PMOS pipe, above-mentioned the 2nd PMOS pipe, above-mentioned the 3rd PMOS pipe and the grid of above-mentioned the 4th PMOS pipe simultaneously; The anodal of second electric capacity links to each other the minus earth of second electric capacity with the grid of the drain electrode of the grid of an above-mentioned PMOS pipe, above-mentioned the 2nd PM0S pipe, above-mentioned the 3rd PMOS pipe and the drain electrode of above-mentioned the 4th PMOS pipe simultaneously;

Positive mutual conductance stabilizer is used for the negative impedance of above-mentioned differential impedance converter is compensated; Positive mutual conductance stabilizer is made up of the 5th PMOS pipe and the 6th PMOS pipe, the grid of the 5th PMOS pipe and drain electrode be ground connection simultaneously, and the source electrode of the 5th PMOS pipe links to each other with the positive pole of first electric capacity, the drain electrode of a PMOS pipe, the grid of the 2nd PMOS pipe, the drain electrode of the 3rd PMOS pipe and the grid of the 4th PMOS pipe simultaneously; The grid of the 6th PMOS pipe and drain electrode be ground connection simultaneously, and the source electrode of the 6th PMOS pipe links to each other with the positive pole of second electric capacity, the grid of a PMOS pipe, the drain electrode of the 2nd PMOS pipe, the grid of the 3rd PMOS pipe and the drain electrode of the 4th PMOS pipe simultaneously;

The negative transconductance Canceller is used to offset the parallel impedance of above-mentioned differential impedance converter; The negative transconductance Canceller by the 7th PMOS manage, the 8th PMOS pipe, the 9th PMOS pipe and the tenth PMOS pipe form; The grid of the 7th PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe, and the drain electrode of the 7th PMOS pipe links to each other with the source electrode of a described PMOS pipe, and the source electrode of the 7th PMOS pipe connects power supply; The grid of the 8th PMOS pipe links to each other with the source electrode of a described PMOS pipe, and the drain electrode of the 8th PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe, and the source electrode of the 8th PMOS pipe connects power supply; The grid of the 9th PMOS pipe links to each other with the source electrode of described the 4th PMOS pipe, and the drain electrode of the 9th PMOS pipe links to each other with the source electrode of described the 3rd PMOS pipe, and the source electrode of the 9th PMOS pipe connects power supply; The grid of the tenth PMOS pipe links to each other with the source electrode of described the 3rd PMOS pipe, and the drain electrode of the tenth PMOS pipe links to each other with the source electrode of described the 4th PMOS pipe, and the source electrode of the tenth PMOS pipe connects power supply;

The connected node of the grid of the drain electrode of the source electrode of an above-mentioned PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe becomes the first port anode of suspension difference active inductance, and the connected node of the drain electrode of the source electrode of above-mentioned the 2nd PMOS pipe, the 8th PMOS pipe and the grid of the 7th PMOS pipe becomes the first port negative terminal of suspension difference active inductance; The connected node of the grid of the drain electrode of the source electrode of above-mentioned the 3rd PMOS pipe, the 9th PMOS pipe and the tenth PMOS pipe becomes the second port negative terminal of suspension difference active inductance, and the connected node of the drain electrode of the source electrode of above-mentioned the 4th PMOS pipe, the tenth PMOS pipe and the grid of the 9th PMOS pipe becomes the second port anode of suspension difference active inductance.

The source electrode of above-mentioned PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe links to each other separately with substrate.

The suspension difference active inductance based on positive feedback that the present invention proposes adopts the current multiplexing technology, is made up of differential impedance converter, positive mutual conductance stabilizer and negative transconductance Canceller three parts.And the two pairs of impedance transformers based on positive feedback in the differential impedance converter only are made of four transistors, be used for the negative impedance of compensating impedance converter and the required transistor of shunt loss of counteracting active inductance in addition, used ten transistors altogether, therefore simple in structure, be easy to design; Suspension difference active inductance of the present invention, can change the parallel impedance and the series impedance of active inductance by transistorized size in adjustment negative transconductance stabilizer and the positive mutual conductance Canceller, and then the quality factor of change active inductance, therefore, the height quality factor (Q) of the suspension difference active inductance of the present invention's proposition change simplicity of design.

Description of drawings

Fig. 1 be existing three rank based on the single-ended structure (a) of inductance capacitance ladder-type filter and the schematic diagram of differential configuration (b), (c) be the suspension difference connected mode of passive inductance.

Fig. 2 is existing schematic diagram based on single-ended inductance of degenerative suspension (a) and suspension differential inductance (b).

Fig. 3 is the differential transconductance schematic diagram in the suspension differential inductance shown in Figure 2.

Fig. 4 is the suspension difference active inductance structural representation based on positive feedback that the present invention proposes.

Fig. 5 adopts the inductance value of suspension difference active inductance of the present invention with frequency variation curve figure.

Fig. 6 adopts the different quality factor (Q) of suspension difference active inductance of the present invention with frequency variation curve figure.

Embodiment

The suspension difference active inductance that the present invention proposes based on positive feedback, its structure comprises as shown in Figure 4:

The differential impedance converter, the electric capacity that is used for inductance that first electric capacity and second electric capacity are produced is transformed into the active inductance of suspension difference; The differential impedance converter by a PMOS manage, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe, first electric capacity and second electric capacity forms; The grid of the one PMOS pipe links to each other with the drain electrode of the 2nd PMOS pipe, and the drain electrode of a PMOS pipe links to each other with the grid of the 2nd PMOS pipe; The grid of the 2nd PMOS pipe links to each other with the drain electrode of the 3rd PMOS pipe, and the drain electrode of the 2nd PMOS pipe links to each other with the grid of the 3rd PMOS pipe, and the grid of the 3rd PMOS pipe links to each other with the drain electrode of the 4th PMOS pipe, and the drain electrode of the 3rd PMOS pipe links to each other with the grid of the 4th PMOS pipe;

First electric capacity and second electric capacity, be used to produce inductance, the anodal of first electric capacity links to each other the minus earth of first electric capacity with the drain electrode of the grid of the drain electrode of an above-mentioned PMOS pipe, above-mentioned the 2nd PMOS pipe, above-mentioned the 3rd PMOS pipe and the grid of above-mentioned the 4th PMOS pipe simultaneously; The anodal of second electric capacity links to each other the minus earth of second electric capacity with the grid of the drain electrode of the grid of an above-mentioned PMOS pipe, above-mentioned the 2nd PMOS pipe, above-mentioned the 3rd PMOS pipe and the drain electrode of above-mentioned the 4th PMOS pipe simultaneously;

Positive mutual conductance stabilizer is used for the negative impedance of above-mentioned differential impedance converter is compensated; Positive mutual conductance stabilizer is made up of the 5th PMOS pipe and the 6th PMOS pipe, the grid of the 5th PMOS pipe and drain electrode be ground connection simultaneously, and the source electrode of the 5th PMOS pipe links to each other with the positive pole of first electric capacity, the drain electrode of a PMOS pipe, the grid of the 2nd PMOS pipe, the drain electrode of the 3rd PMOS pipe and the grid of the 4th PMOS pipe simultaneously; The grid of the 6th PMOS pipe and drain electrode be ground connection simultaneously, and the source electrode of the 6th PMOS pipe links to each other with the positive pole of second electric capacity, the grid of a PMOS pipe, the drain electrode of the 2nd PMOS pipe, the grid of the 3rd PMOS pipe and the drain electrode of the 4th PMOS pipe simultaneously;

The negative transconductance Canceller is used to offset the parallel impedance of above-mentioned differential impedance converter; The negative transconductance Canceller by the 7th PMOS manage, the 8th PMOS pipe, the 9th PMOS pipe and the tenth PMOS pipe form; The grid of the 7th PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe, and the drain electrode of the 7th PMOS pipe links to each other with the source electrode of a described PMOS pipe, and the source electrode of the 7th PMOS pipe connects power supply; The grid of the 8th PMOS pipe links to each other with the source electrode of a described PMOS pipe, and the drain electrode of the 8th PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe, and the source electrode of the 8th PMOS pipe connects power supply; The grid of the 9th PMOS pipe links to each other with the source electrode of described the 4th PMOS pipe, and the drain electrode of the 9th PMOS pipe links to each other with the source electrode of described the 3rd PMOS pipe, and the source electrode of the 9th PMOS pipe connects power supply; The grid of the tenth PMOS pipe links to each other with the source electrode of described the 3rd PMOS pipe, and the drain electrode of the tenth PMOS pipe links to each other with the source electrode of described the 4th PMOS pipe, and the source electrode of the tenth PMOS pipe connects power supply;

The connected node of the grid of the drain electrode of the source electrode of an above-mentioned PMOS pipe, the 7th PMOS pipe and the 8th PMOS pipe becomes the first port anode of suspension difference active inductance, and the connected node of the drain electrode of the source electrode of above-mentioned the 2nd PMOS pipe, the 8th PMOS pipe and the grid of the 7th PMOS pipe becomes the first port negative terminal of suspension difference active inductance; The connected node of the grid of the drain electrode of the source electrode of above-mentioned the 3rd PMOS pipe, the 9th PMOS pipe and the tenth PMOS pipe becomes the second port negative terminal of suspension difference active inductance, and the connected node of the drain electrode of the source electrode of above-mentioned the 4th PMOS pipe, the tenth PMOS pipe and the grid of the 9th PMOS pipe becomes the second port anode of suspension difference active inductance.

The source electrode of above-mentioned PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe links to each other separately with substrate.

Below in conjunction with accompanying drawing, introduce content of the present invention in detail.

The differential impedance converter is used for first electric capacity and second electric capacity are transformed into the active inductance of suspension difference;

Positive mutual conductance stabilizer is used for the negative impedance of above-mentioned differential impedance converter is compensated;

The negative transconductance Canceller is used to offset the parallel impedance of active inductance.

In the such scheme, described differential impedance converter is managed (M by a PMOS _2l), the 2nd PMOS manages (M _2r), the 3rd PMOS manages (M _4l) and the 4th PMOS pipe (M _4r) form; The one PMOS manages (M _2l) grid and the 2nd PMOS pipe (M _2r) drain electrode link to each other, a PMOS manages (M _2l) drain electrode and the 2nd PMOS pipe (M _2r) grid link to each other; The 2nd PMOS manages (M _2r) grid and the 3rd PMOS pipe (M _4l) drain electrode link to each other, the 2nd PMOS manages (M _2r) drain electrode and the 3rd PMOS pipe (M _4l) grid link to each other, the 3rd PMOS manages (M _4l) grid and the 4th PMOS pipe (M _4r) drain electrode link to each other, the 3rd PMOS manages (M _4l) drain electrode and the 4th PMOS pipe (M _4r) grid link to each other; First electric capacity (the C _1l) anodal simultaneously and PMOS pipe (M _2l) drain electrode, the 2nd PMOS manage (M _2r) grid, the 3rd PMOS manage (M _4l) drain electrode and the 4th PMOS pipe (M _4r) grid link to each other the first electric capacity (C _1l) minus earth voltage (GND); Second electric capacity (the C _1r) anodal simultaneously and PMOS pipe (M _2l) grid, the 2nd PMOS manage (M _2r) drain electrode, the 3rd PMOS manage (M _4l) grid and the 4th PMOS pipe (M _4r) drain electrode link to each other the second electric capacity (C _1r) minus earth voltage (GND);

In the such scheme, described positive mutual conductance stabilizer is managed (M by the 5th PMOS _3l) and the 6th PMOS pipe (M _3r) form, the 5th PMOS manages (M _3l) grid and drain electrode ground connection simultaneously, the 5th PMOS manages (M ₃₁) source electrode simultaneously and the first electric capacity (C _1l) positive pole, a PMOS manage (M _2l) drain electrode, the 2nd PMOS manage (M _2r) grid, the 3rd PMOS manage (M _4l) drain electrode and the 4th PMOS pipe (M _4r) grid link to each other; The 6th PMOS manages (M _3r) grid and drain electrode ground connection simultaneously, the 6th PMOS manages (M _3r) source electrode simultaneously and the second electric capacity (C _1r) positive pole, a PMOS manage (M _2l) grid, the 2nd PMOS manage (M _2r) drain electrode, the 3rd PMOS manage (M _4l) grid and the 4th PMOS pipe (M _4r) drain electrode link to each other;

In the such scheme, described negative transconductance Canceller is managed (M by the 7th PMOS _1l), the 8th PMOS manages (M _1r), the 9th PMOS manages (M _5l) and the tenth PMOS pipe (M _5r) form; Grid (the M of the 7th PMOS pipe _1l) manage (M with described the 2nd PMOS _2r) source electrode link to each other, the 7th PMOS manages (M _1l) drain electrode and described PMOS pipe (M _2l) source electrode link to each other, the 7th PMOS manages (M _1l) source electrode connect supply voltage (VDD); The 8th PMOS manages (M _1r) grid and described PMOS pipe (M _2l) source electrode link to each other, the 8th PMOS manages (M _1r) drain electrode and described the 2nd PMOS pipe (M _2r) source electrode link to each other, the source electrode of the 8th PMOS pipe connects supply voltage (VDD); The 9th PMOS manages (M _5l) grid and described the 4th PMOS pipe (M _4r) source electrode link to each other, the 9th PMOS manages (M _5l) drain electrode and described the 3rd PMOS pipe (M _4l) source electrode link to each other, the 9th PMOS manages (M _5l) source electrode connect supply voltage (VDD); The tenth PMOS manages (M _5r) grid and described the 3rd PMOS pipe (M _4l) source electrode link to each other, the tenth PMOS manages (M _5r) drain electrode and described the 4th PMOS pipe (M _4r) source electrode link to each other, the tenth PMOS manages (M _5r) source electrode connect supply voltage (VDD);

Described PMOS pipe (M _2l) source electrode, the 7th PMOS manage (M _1l) drain electrode and the 8th PMOS pipe (M _1r) the connected node of grid become the first port anode (V of suspension difference active inductance _1p), described the 2nd PMOS pipe (M _2r) source electrode, the 8th PMOS manage (M _1r) drain electrode and the 7th PMOS pipe (M _1l) the connected node of grid become the first port negative terminal (V of suspension difference active inductance _1n); Described the 3rd PMOS pipe (M _4l) source electrode, the 9th PMOS manage (M _5l) drain electrode and the tenth PMOS pipe (M _5r) the connected node of grid become the second port negative terminal (V of suspension difference active inductance _2n), described the 4th PMOS pipe (M _4r) source electrode, the tenth PMOS manage (M _5r) drain electrode and the 9th PMOS pipe (M _5l) the connected node of grid become the second port anode (V of suspension difference active inductance _2p).

Described PMOS pipe (M _2l), the 2nd PMOS manages (M _2r), the 3rd PMOS manages (M _4l), the 4th PMOS manages (M _4r), the 5th PMOS manages (M _3l), the 6th PMOS manages (M _3r), the 7th PMOS manages (M _1l), the 8th PMOS manages (M _1r), the 9th PMOS manages (M _5l), the tenth PMOS manages (M _5r) source electrode link to each other separately with substrate.

Suspension difference active inductance based on positive feedback of the present invention, the suspension differential impedance converter of the core of suspension difference active inductance has only been used four transistors, the transistor of miscellaneous function in addition, the suspension difference active inductance that proposes has only been used ten transistors, wherein positive mutual conductance stabilizer is used for compensating the negative impedance of suspension difference active inductance, solves the stability problem of suspension difference active inductance.Change the size of series resistance in the suspension difference active inductance simultaneously by transistorized size in the change stabilizer.Wherein the negative transconductance Canceller is used for offsetting the parallel impedance of suspension difference active inductance.Change the quality factor of suspension difference active inductance by transistorized size in the change Canceller.

Below introduce the result that the suspension difference active inductance that the present invention is proposed carries out simulating, verifying:

Impedance transformer and two electric capacity that the core of suspension difference active inductance is made up of four transistors are formed.And positive mutual conductance stabilizer has compensated the negative impedance of impedance transformer, has solved the stability problem of the suspension difference active inductance that proposes.The negative transconductance Canceller has been offset the parallel impedance in the active inductance.Ignore transistorized output mutual conductance and parasitic capacitance, and establish (M _1l, M _1r) and (M _5l, M _5r) mutual conductance be Gm, establish (M _2l, M _2r) and (M _4l, M _4r) mutual conductance be G _m, establish (M _3l, M _3r) mutual conductance be 2*G _m, V _CpAnd V _CnIt all is C that two nodes connect electric capacity.The suspension difference active inductance L that can obtain proposing _AIFor:

$L_{\mathrm{AI}}=\frac{C}{G_m^2}---\left(1\right)$

In Cadence, adopt the suspension difference active inductance among CMOS 90nm radio frequency technological design Fig. 4, to verify correctness of the present invention.Active inductance parameter setting shown in Figure 4: V _CpAnd V _CnIt all is 215.6 flying methods (fF) that two nodes connect electric capacity; The transconductance value of the active inductance that proposes is set as the 4th group of numerical value of table 1.Can calculate the equivalent inductance value by formula (1) is 7.32uH, and the inductance value that calculates does not here comprise the information with frequency change.The curve of describing among Fig. 5 is the curve of the inductance value of the suspension difference active inductance that proposes among Fig. 4 with frequency change, and the vertical coordinate axle of this curve chart and horizontal axis represent with milihenry (mH) to be the inductance value and the correspondent frequency (Hz) of unit respectively.Know from this curve: (1) inductance value between 100MHz-400MHz is smooth, and at the 229.8MHz place, inductance value is 7.4uH, coincide with calculated value.(2) self-resonant frequency of this suspension difference active inductance is 538.5MHz.Consider transistorized output mutual conductance, transistorized mutual conductance has just been offset in the 4th group of mutual conductance distribution in the table 1, and at this time the quality factor of active inductance are subject to the parallel impedance (first port and second port) and the series impedance (V of active inductance _CpAnd V _Cn) (about the parallel impedance of active inductance and series impedance can be with reference to the CMOS Active Inductors and Transformers Principle of spring publishing house in 2008, Implementation, and Applications).Solid line has been described quality factor q=1.4 that the 4th group of corresponding in the correspondence table 1 mutual conductance distributes among Fig. 6.First to three group of mutual conductance distributes in the his-and-hers watches 1, and the transistor transconductance in the positive mutual conductance Canceller reduces 10%, has so just increased the series impedance of active inductance, has reduced the series loss of active inductance, has effectively improved quality factor.Mutual conductance in the table 1 distributes from first group to the 3rd group, and along with the mutual conductance in the negative transconductance Canceller constantly increases, the quality factor of the suspension difference active inductance of proposition constantly increase, and the Q value changes to 21 from 3.1.Mainly be because the mutual conductance increase in the negative impedance Canceller can be offset the shunt loss of active inductance, effectively improve the quality factor of active inductance.

The quality factor (Q) that table 1 obtains for transistor transconductance value among Fig. 4 and emulation

Transistor	M 1l、M 1r、M 5l、M 5r	M 2l、M 2r、M 4l、M 4r	M 3l、M 3r	Quality factor (Q)
					1 transconductance value	197.7uS	172.2uS	305.7uS	21
2 transconductance value	196.5uS	172.0uS	305.4uS	8.3

3 transconductance value	187.3uS	170.9uS	303.4uS	3.1
					4 transconductance value	171.6uS	171.6uS	336.5uS	1.4

Claims (1)

1. A suspension differential active inductor based on positive feedback, characterized in that the suspension differential active inductor comprises: The differential impedance converter is used to convert the capacitance of the inductance generated by the first capacitor and the second capacitor into a suspended differential active inductance; the differential impedance converter consists of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a first PMOS transistor. Composed of four PMOS transistors, a first capacitor and a second capacitor; the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the first PMOS transistor is connected to the gate of the second PMOS transistor; the second PMOS transistor The gate of the transistor is connected to the drain of the third PMOS transistor, the drain of the second PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the PMOS transistor is connected to the gate of the fourth PMOS transistor; The first capacitor and the second capacitor are used to generate inductance, and the positive electrode of the first capacitor is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the third PMOS transistor and the fourth PMOS transistor. The gate of the PMOS transistor is connected, the negative electrode of the first capacitor is grounded; the positive electrode of the second capacitor is simultaneously connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the third PMOS transistor and the first capacitor. The drains of the four PMOS transistors are connected, and the negative electrode of the second capacitor is grounded; The positive transconductance stabilizer is used to compensate the negative impedance of the above-mentioned differential impedance converter; the positive transconductance stabilizer is composed of a fifth PMOS transistor and a sixth PMOS transistor, and the gate and drain of the fifth PMOS transistor are grounded simultaneously, The source of the fifth PMOS transistor is connected to the positive pole of the first capacitor, the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the third PMOS transistor and the gate of the fourth PMOS transistor; the sixth The gate and the drain of the PMOS transistor are grounded simultaneously, and the source of the sixth PMOS transistor is simultaneously connected to the anode of the second capacitor, the gate of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the third PMOS transistor and The drains of the fourth PMOS transistors are connected; The negative transconductance canceller is used to cancel the parallel impedance of the differential impedance converter; the negative transconductance canceller is composed of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor and the tenth PMOS transistor; the seventh PMOS transistor The gate is connected to the source of the second PMOS transistor, the drain of the seventh PMOS transistor is connected to the source of the first PMOS transistor, and the source of the seventh PMOS transistor is connected to the power supply; The grid is connected to the source of the first PMOS transistor, the drain of the eighth PMOS transistor is connected to the source of the second PMOS transistor, and the source of the eighth PMOS transistor is connected to the power supply; the drain of the eighth PMOS transistor is connected to the power supply; The grid is connected to the source of the fourth PMOS transistor, the drain of the ninth PMOS transistor is connected to the source of the third PMOS transistor, and the source of the ninth PMOS transistor is connected to the power supply; The gate is connected to the source of the third PMOS transistor, the drain of the tenth PMOS transistor is connected to the source of the fourth PMOS transistor, and the source of the tenth PMOS transistor is connected to the power supply; The connection node of the source of the first PMOS transistor, the drain of the seventh PMOS transistor, and the gate of the eighth PMOS transistor becomes the positive terminal of the first port of the suspended differential active inductance, and the source of the second PMOS transistor and the gate of the eighth PMOS transistor The connected node between the drains of the eight PMOS transistors and the gate of the seventh PMOS transistor becomes the negative terminal of the first port of the suspended differential active inductance; the source of the above-mentioned third PMOS transistor, the drain of the ninth PMOS transistor and the tenth PMOS transistor The node connected to the gate of the transistor becomes the negative terminal of the second port of the suspended differential active inductance, and the node connected to the source of the fourth PMOS transistor, the drain of the tenth PMOS transistor, and the gate of the ninth PMOS transistor becomes the suspended differential Positive terminal of the second port of the active inductor. The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor The source and substrate are connected separately.

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