CN102263030A - A kind of preparation method of trench type power device - Google Patents
A kind of preparation method of trench type power device Download PDFInfo
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Abstract
Description
技术领域 technical field
本发明涉及半导体工艺技术领域,尤其涉及一种沟槽型功率器件的制备方法。The invention relates to the technical field of semiconductor technology, in particular to a preparation method of a trench type power device.
背景技术 Background technique
沟槽型功率器件具有击穿电压高,导通电阻低,开关速度快等显著优点,已经成为集成电路等领域的主流功率器件。现有的沟槽型功率器件的制备方法通常包括如下步骤:生长硬掩膜(Hard mask)层;在硬掩膜上进行光刻,露出沟槽区域;形成沟槽(Trench);进行多晶硅的淀积,填充沟槽;采用干法刻蚀进行多晶硅的回蚀,去掉多余的多晶硅;之后,还包括形成体区;形成源区;形成绝缘介质层,接触孔,金属层和钝化层等步骤。Trench power devices have significant advantages such as high breakdown voltage, low on-resistance, and fast switching speed, and have become mainstream power devices in the field of integrated circuits and other fields. The preparation method of existing trench type power device generally comprises the following steps: grow hard mask (Hard mask) layer; Carry out photoetching on hard mask, expose trench region; Form trench (Trench); Carry out polysilicon Deposition, fill trenches; etch back polysilicon by dry etching to remove excess polysilicon; after that, it also includes forming body region; forming source region; forming insulating dielectric layer, contact hole, metal layer and passivation layer, etc. step.
在实现上述沟槽型功率器件的制备过程中,发明人发现现有技术中至少存在如下问题:现有的制备方法容易造成多晶硅的残留。这是由于,采用干法刻蚀进行多晶硅的回蚀的步骤中,如图1所示,需要刻蚀的多晶硅面积大,而且较厚,因此刻蚀的过程中产生的副产聚合物较多,如图2所示,有可能覆盖在多晶层表面的部分区域,导致部分区域的进一步正常刻蚀受到阻碍,将在刻蚀后留下块状的残留物。另外,由于多晶层厚,在多晶硅淀积的工序,多晶表面会产生一些点状的凸起物这也会导致多晶回蚀的时候,不能刻蚀干净,造成多晶硅的残留。而如果造成多晶硅残留,最终将导致器件结构的栅极源极短路,产生漏电,严重影响成品率。During the preparation process of the aforementioned trench-type power devices, the inventors found that at least the following problems exist in the prior art: the existing preparation methods are likely to cause polysilicon residues. This is because, in the step of etching back polysilicon by dry etching, as shown in Figure 1, the area of polysilicon to be etched is large and thick, so the by-product polymer produced in the etching process is more , as shown in FIG. 2 , may cover some areas on the surface of the polycrystalline layer, causing further normal etching of some areas to be hindered, leaving blocky residues after etching. In addition, due to the thickness of the polycrystalline layer, some point-shaped protrusions will appear on the surface of the polycrystalline silicon during the process of polycrystalline silicon deposition, which will also cause the polycrystalline silicon to be etched back and cannot be etched clean, resulting in polycrystalline silicon residues. However, if polysilicon remains, it will eventually lead to a short circuit between the gate and source of the device structure, resulting in leakage, which will seriously affect the yield.
发明内容 Contents of the invention
本发明的实施例提供了一种沟槽型功率器件的制备方法,能够有效解决由于多晶硅表面的凸起以及多晶硅干法刻蚀过程中聚合物残留所导致的多晶硅残留问题。The embodiment of the present invention provides a method for preparing a trench power device, which can effectively solve the problem of polysilicon residues caused by protrusions on the polysilicon surface and polymer residues during polysilicon dry etching.
为达到上述目的,本发明的实施例采用如下技术方案:In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
一种沟槽型功率器件的制备方法,包括:A method for preparing a trench power device, comprising:
在衬底上设置硬掩膜层;disposing a hard mask layer on the substrate;
在所述硬掩膜层上设置过渡层;disposing a transition layer on the hard mask layer;
在所述过渡层上进行光刻,形成沟槽窗口;performing photolithography on the transition layer to form a trench window;
在所述衬底上与所述沟槽窗口对应的区域形成沟槽;forming a trench on the substrate in a region corresponding to the trench window;
向所述沟槽内填充多晶硅;filling the trench with polysilicon;
采用抛光的方式将所述沟槽以外区域的多晶硅研磨掉。The polysilicon in the area outside the trench is ground away by polishing.
采用上述技术方案后,本发明实施例提供的沟槽型功率器件的制备方法,通过改变工艺流程,在沟槽刻蚀前增加一层过渡层,后续采用多晶硅的抛光方式,代替目前的多晶硅干法刻蚀,解决由于多晶表面的凸起以及多晶干法刻蚀过程中聚合物残留导致的多晶残留问题,进而解决了成品器件的栅极源极漏电问题,大大提高成品率。另外,相对于干法刻蚀,采用抛光的方式,进一步降低了成本。After adopting the above-mentioned technical solution, the preparation method of the trench type power device provided by the embodiment of the present invention, by changing the process flow, adding a transition layer before trench etching, and subsequently adopting the polishing method of polysilicon, instead of the current dry polysilicon It solves the polycrystalline residue problem caused by the protrusion of the polycrystalline surface and the polymer residue in the polycrystalline dry etching process, and then solves the gate-source leakage problem of the finished device, greatly improving the yield. In addition, compared with dry etching, polishing is used to further reduce the cost.
附图说明 Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1为现有技术中进行多晶硅回蚀前的状态示意图;FIG. 1 is a schematic diagram of the state before performing polysilicon etch-back in the prior art;
图2为现有技术中进行多晶硅回蚀后的状态示意图;2 is a schematic diagram of the state after polysilicon etch-back in the prior art;
图3为本发明实施例提供的制备方法的工艺流程图;Fig. 3 is the process flow chart of the preparation method provided by the embodiment of the present invention;
图4(a)为本发明实施例一的工艺流程图;Fig. 4 (a) is the process flow chart of embodiment one of the present invention;
图4(b)为与图4(a)所示的工艺流程相对应的实施效果图。Fig. 4(b) is an implementation effect diagram corresponding to the process flow shown in Fig. 4(a).
具体实施方式 Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
如图3所示,本发明实施例提供的一种沟槽型功率器件的制备方法,包括如下步骤:As shown in FIG. 3, a method for manufacturing a trench-type power device provided by an embodiment of the present invention includes the following steps:
S11,在衬底上设置硬掩膜层;S11, disposing a hard mask layer on the substrate;
S12,在所述硬掩膜层上设置过渡层;S12, disposing a transition layer on the hard mask layer;
S13,在所述过渡层上进行光刻,形成沟槽窗口;S13, performing photolithography on the transition layer to form a trench window;
S14,在所述衬底上与所述沟槽窗口对应的区域形成沟槽;S14, forming a trench on the substrate in a region corresponding to the trench window;
S15,向所述沟槽内填充多晶硅;S15, filling polysilicon into the trench;
S16,采用抛光的方式将所述沟槽以外区域的多晶硅研磨掉。S16, polishing away the polysilicon in the area outside the trench by polishing.
本发明实施例提供的沟槽型功率器件的制备方法,能够有效解决由于多晶硅表面的凸起以及多晶硅干法刻蚀过程中聚合物残留所导致的多晶硅残留问题。The preparation method of the trench type power device provided by the embodiment of the present invention can effectively solve the problem of polysilicon residue caused by protrusions on the surface of polysilicon and polymer residue during polysilicon dry etching.
其中,S11步骤中所沉积的过渡层将作为后续S16步骤进行抛光的停止层,可采用氮化硅(Si3N4)层。由于Si3N4的物理性质与多晶硅的不同,因此抛光的速率不同,所以在S16步骤进行沟槽以外区域的抛光研磨时,当抛光设备监控的抛光速率发生变化时,就能够判断,沟槽以外区域的多晶硅已经被研磨干净,即在S16步骤中,采用抛光的方式进行沟槽以外区域的多晶硅的研磨,当抛光速率发生变化时,就可停止抛光。这里注意的是,还可以采用其他材料的过渡层,这里不做限定。Wherein, the transition layer deposited in the step S11 will be used as a stop layer for polishing in the subsequent step S16, and a silicon nitride (Si 3 N 4 ) layer may be used. Since the physical properties of Si 3 N 4 are different from those of polysilicon, the polishing rate is different. Therefore, when the polishing of the area other than the groove is performed in step S16, when the polishing rate monitored by the polishing equipment changes, it can be judged that the groove The polysilicon in the area outside the groove has been polished, that is, in step S16, the polysilicon in the area outside the groove is ground by polishing, and the polishing can be stopped when the polishing rate changes. It should be noted here that transition layers of other materials may also be used, which is not limited here.
进一步地,S16步骤中所采用的抛光方式优选为化学机械抛光。化学机械抛光在机械抛光的同时,加入了化学制剂,能够和被抛光物发生反应,使被抛光物的抛光面更加的平整,也进一步地减少多晶硅残留的机会。Further, the polishing method used in step S16 is preferably chemical mechanical polishing. In chemical mechanical polishing, chemical agents are added at the same time as mechanical polishing, which can react with the object to be polished, so that the polished surface of the object to be polished is smoother, and the chance of polysilicon residue is further reduced.
另外,不同区域的抛光精度可能略有差别,如果某些区域磨的少了,可能这些区域会有少量多晶硅的残留。因此,为了保证能将沟槽以外区域的多晶硅完全去除干净,避免多晶硅的残留,可以采用过量抛光的方式,将过渡层,如Si3N4层也磨去一些,即S16步骤具体可为:采用抛光的方式进行沟槽以外区域的多晶硅的研磨;当抛光速率发生变化时,继续进行一定时间的抛光后停止抛光。其中,过量抛光的时间可根据实际情况和过渡层的厚度灵活掌握。In addition, the polishing accuracy of different areas may be slightly different. If some areas are less polished, there may be a small amount of polysilicon residue in these areas. Therefore, in order to ensure that the polysilicon in the area outside the trench can be completely removed and avoid polysilicon residue, excessive polishing can be used to remove some of the transition layer, such as the Si 3 N 4 layer, that is, the step S16 can be specifically: Polishing is used to grind the polysilicon in areas other than the groove; when the polishing rate changes, the polishing is continued for a certain period of time and then stopped. Wherein, the time for excessive polishing can be flexibly controlled according to the actual situation and the thickness of the transition layer.
为了使本领域的技术人员更好的理解本发明的技术方案,下面通过具体实施例并结合附图对本发明的实施例进行详细描述。这里要注意的是,以下的具体实施例只是为了描述本发明,但不限于本发明。In order to enable those skilled in the art to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below through specific embodiments and in conjunction with the accompanying drawings. It should be noted here that the following specific examples are only for describing the present invention, but not limiting the present invention.
实施例一Embodiment one
本实施例为沟槽型双重扩散金属半导体氧化物(DMOS,Doubl-Deffused Metel Oxide Semiconductor)场效应管的制备方法,如图4所示,其中,图4(a)为本实施例的工艺流程图,图4(b)为与图4(a)的工艺流程相对应的实施效果图,包括下列步骤:This embodiment is a method for preparing a trench type double-diffused metal semiconductor oxide (DMOS, Doubl-Deffused Metel Oxide Semiconductor) field effect transistor, as shown in Figure 4, wherein, Figure 4 (a) is the process flow of this embodiment Fig. 4 (b) is an implementation effect diagram corresponding to the technological process of Fig. 4 (a), comprising the following steps:
S21,在Si衬底上生长SiO2硬掩膜层;S21, growing a SiO 2 hard mask layer on the Si substrate;
本步骤的实施效果见S21′。See S21' for the implementation effect of this step.
S22,在SiO2硬掩膜层上沉积Si3N4过渡层;S22, depositing a Si 3 N 4 transition layer on the SiO 2 hard mask layer;
本步骤的实施效果见S22′。Si3N4过渡层将作为后续步骤对沟槽之外区域的多晶硅进行抛光的停止层。See S22' for the implementation effect of this step. The Si 3 N 4 transition layer will serve as a stop layer for subsequent steps to polish the polysilicon in areas outside the trench.
S23,在Si3N4过渡层上进行光刻,形成沟槽窗口;S23, performing photolithography on the Si 3 N 4 transition layer to form a trench window;
本步骤的实施效果见S23′。See S23' for the implementation effect of this step.
S24,采用等离子干法刻蚀,在Si衬底上与沟槽窗口对应的区域形成沟槽;S24, using plasma dry etching to form a trench on the Si substrate in a region corresponding to the trench window;
本步骤中,首先依次对Si3N4过渡层和SiO2硬掩膜层与沟槽窗口对应的区域进行干法刻蚀,打开硬掩膜层和过渡层,露出衬底上需要形成沟槽的区域;然后对Si衬底上的沟槽区域,即与沟槽窗口对应的区域进行干法刻蚀,形成沟槽,并对沟槽底部进行圆滑处理,实施效果见S24′。In this step, first perform dry etching on the Si 3 N 4 transition layer and the SiO 2 hard mask layer corresponding to the trench window, open the hard mask layer and the transition layer, and expose the trench that needs to be formed on the substrate. area; then perform dry etching on the trench area on the Si substrate, that is, the area corresponding to the trench window, to form a trench, and smooth the bottom of the trench, see S24' for the implementation effect.
S25,进行沟槽壁的氧化;S25, performing oxidation of the groove wall;
本步骤的实施效果见S25′。See S25' for the implementation effect of this step.
S26,向沟槽内填充多晶硅;S26, filling the trench with polysilicon;
本步骤的实施效果见S26′。See S26' for the implementation effect of this step.
S27,采用化学机械抛光的方式,将沟槽之外区域的多晶研磨掉。S27, using a chemical mechanical polishing method to grind away the polycrystal in the area outside the trench.
本步骤中,将通过对抛光速率的检测判断抛光程度。由于Si3N4的抛光速率与多晶硅的不同,当抛光设备监控的抛光速率发生变化时,就可以判断,沟槽以外区域的多晶硅已经被研磨干净。但为了能将沟槽以外区域的多晶完全去除干净,本步骤可采用过量抛光的方式,当抛光速率发生变化时,继续抛光一定的时间,将Si3N4层也磨去一些,这样,就可以完全避免多晶硅的残留。而且与干法刻蚀相比,化学机械抛光的成本较低,也就降低了制备沟槽型功率器件的工艺成本。本步骤的实施效果见S27′。In this step, the degree of polishing will be judged by detecting the polishing rate. Since the polishing rate of Si 3 N 4 is different from that of polysilicon, when the polishing rate monitored by the polishing equipment changes, it can be judged that the polysilicon in the area outside the trench has been polished. However, in order to completely remove the polycrystals in areas other than the trenches, this step can use excessive polishing. When the polishing rate changes, continue polishing for a certain period of time to remove some of the Si 3 N 4 layer. In this way, The residue of polysilicon can be completely avoided. Moreover, compared with dry etching, the cost of chemical mechanical polishing is lower, which reduces the process cost of manufacturing trench power devices. See S27' for the implementation effect of this step.
S27步骤后,先将Si衬底上的Si3N4过渡层和SiO2硬掩膜层去掉,然后进行包括形成P型体区,形成源区,形成绝缘介质层、接触孔、金属层和钝化层等其余步骤。需要指出的是,这些步骤均可按照常规的沟槽型DMOS的制备方法进行即可,由于与现有技术相同,这里不再赘述。After step S27, the Si 3 N 4 transition layer and the SiO 2 hard mask layer on the Si substrate are removed earlier, and then include forming a P-type body region, forming a source region, forming an insulating dielectric layer, a contact hole, a metal layer and Passivation layer and other steps. It should be pointed out that these steps can be carried out according to the conventional trench-type DMOS preparation method, and since they are the same as those in the prior art, details will not be repeated here.
综上所述,本发明实施例提供的沟槽型功率器件的制备方法,通过改变工艺流程,在沟槽刻蚀前增加一层过渡层,后续采用多晶硅的抛光方式,代替目前的多晶硅干法刻蚀,解决由于多晶硅表面的凸起以及多晶硅干法刻蚀过程中聚合物残留导致的多晶硅残留问题,进而解决了成品的栅极源极短路、漏电问题,大大提高成品率。另外,相对于干法刻蚀,采用抛光的方式,进一步降低了成本。To sum up, the method for preparing a trench power device provided by the embodiment of the present invention, by changing the process flow, adding a transition layer before trench etching, and subsequently adopting polysilicon polishing method, instead of the current polysilicon dry method Etching solves the polysilicon residue problem caused by the protrusion on the polysilicon surface and the polymer residue in the polysilicon dry etching process, and then solves the gate-source short circuit and leakage problems of the finished product, greatly improving the yield. In addition, compared with dry etching, polishing is used to further reduce the cost.
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
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CN106252405A (en) * | 2015-06-15 | 2016-12-21 | 北大方正集团有限公司 | Super-junction structure and lithographic method thereof and there is the field-effect transistor of this super-junction structure |
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CN101872724A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) |
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CN1438683A (en) * | 2001-12-20 | 2003-08-27 | 东部电子株式会社 | Method for short-channel transistor of semiconductor element |
CN101345209A (en) * | 2003-12-12 | 2009-01-14 | 三星电子株式会社 | Slurry Components and CMP Method Utilizing Them |
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CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
CN106252405A (en) * | 2015-06-15 | 2016-12-21 | 北大方正集团有限公司 | Super-junction structure and lithographic method thereof and there is the field-effect transistor of this super-junction structure |
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