CN101872724A - Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) - Google Patents
Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which comprises the following steps of: when filling a groove, firstly filling a P-type extension into the groove by utilizing an epitaxial process, and then filling the groove by utilizing polycrystalline silicon; and then finishing subsequent process steps. A P-thin layer structure in the invention is formed by firstly filling the groove through the P-type extension and then filling the groove by utilizing the polycrystalline silicon, the complexity of a groove filling process can be reduced by utilizing the better groove filling capability of the polycrystalline silicon, and the cost of the process is lowered by utilizing the high-batch processing capability of the polycrystalline silicon.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to the manufacture method of a kind of super junction MOSFET.
Background technology
VDMOSFET can reduce conducting resistance by the thickness of attenuate drain terminal drift region.Yet the thickness of attenuate drain terminal drift region will reduce the puncture voltage of device, and therefore in VDMOS, the puncture voltage that improves device is a pair of contradiction with the conducting resistance that reduces device.Super junction MOSFET adopts new structure of voltage-sustaining layer, utilize a series of P type and the N type semiconductor thin layer of alternately arranging, under low reverse voltage, P type N type district is exhausted, realize that electric charge compensates mutually, thereby make N type district under high-dopant concentration, can realize high puncture voltage, thereby obtain low on-resistance and high-breakdown-voltage simultaneously, the theoretical limit of the power MOSFET that breaks traditions (comprising VDMOS) conducting resistance.
The structure of super junction MOSFET device and manufacture method can be divided into two big classes: the first kind is to utilize repeatedly photoetching-epitaxial growth and inject to obtain P type and N type doped region alternately; Second class is an open channels on N type silicon epitaxy layer, inserts P type polycrystalline in groove, or tilts to inject p type impurity, or inserts P type extension.Above-mentioned first kind technology is complex process not only, realize that difficulty is big, and cost is very high; The second class methods medium dip is injected because stability and poor repeatability fail to be used for to produce in batches, need the P type polysilicon process of impurity concentration cannot realize on technology that so P type extension is inserted technology and received very big concern.Existing P type extension is inserted technology and is generally carried out the epitaxial growth of P type after forming groove, utilize cmp to be ground to N type extension later on, carry out thermal oxidation by the silicon that will have damage again, by wet method the silica that forms is removed again, thereby obtain smooth, P type that replaces and N type structure.But P type extension is inserted the trench process more complicated, and technology difficulty is big, technology cost height.
Summary of the invention
Technical problem to be solved by this invention provides the manufacture method of a kind of super junction MOSFET, can adopt step simple, and technology with low cost is made super junction MOSFET.
For solving the problems of the technologies described above, the technical scheme of the manufacture method of super junction MOSFET of the present invention is to comprise the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and P-type extension;
(7) silicon nitride film and silicon oxide film removal are obtained P-type and N-type structure alternately;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
Another technical scheme of the manufacture method of super junction MOSFET of the present invention is to comprise the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and P-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained P-type and N-type structure smooth and that replace by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
The another technical scheme of the manufacture method of super junction MOSFET of the present invention is to comprise the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and N-type extension;
(7) silicon nitride film and silicon oxide film removal are obtained alternating N-type and P-type structure;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
A technical scheme again of the manufacture method of super junction MOSFET of the present invention is to comprise the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and N-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained smooth and alternating N-type and P-type structure by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
The P-laminate structure is to insert groove earlier by P-type extension among the present invention, utilize polysilicon that groove is filled up again, can utilize the complexity of the better trench fill ability minimizing of polysilicon trench fill technology, utilize the high batch process ability of polysilicon, reduce the cost of technology.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1～Figure 10 is the schematic diagram of each step of manufacture method of super junction MOSFET of the present invention.
Reference numeral is among the figure, 1.N+ substrate, 2.N-type extension, 3. bed course oxide-film, 4. nitride film, 5. photoresist, 6.P-extension, 7. polysilicon, 8. grid oxygen, 9. grid polycrystalline silicon, 10. source N+, 11.P+ the contact zone, 12.P trap, 13. spacer medium films, 14. surface metal-layers, 15. back metal films.
Embodiment
The invention discloses the manufacture method of a kind of super junction MOSFET, its first embodiment comprises the steps: in conjunction with the accompanying drawings
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating, as shown in Figure 1 as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove, as shown in Figure 2;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove, as shown in Figure 3 as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove, as shown in Figure 4;
(5) utilize polysilicon that groove is filled up, as shown in Figure 5;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and P-type extension, as shown in Figure 6;
(7) silicon nitride film and silicon oxide film removal are obtained P-type and N-type structure alternately, as shown in Figure 7;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device, as Fig. 8～shown in Figure 10.
In the above-described embodiments, utilize polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
Second embodiment of the manufacture method of super junction MOSFET of the present invention compares with first embodiment, and the step after polysilicon fills up groove is different, and second embodiment comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and P-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained P-type and N-type structure smooth and that replace by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
In the above-described embodiments, utilize polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
Above-mentioned two embodiment mades be N type MOSFET device, following two embodiment mades of the manufacture method of super junction MOSFET of the present invention be P type MOSFET device.The 3rd embodiment comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and N-type extension;
(7) silicon nitride film and silicon oxide film removal are obtained alternating N-type and P-type structure;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
In the above-described embodiments, utilize polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
Second embodiment of the manufacture method of super junction MOSFET of the present invention compares with first embodiment, and the step after polysilicon fills up groove is different, and second embodiment comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and N-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained smooth and alternating N-type and P-type structure by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
In the above-described embodiments, utilize polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
In sum, the P-laminate structure is to insert groove earlier by P-type extension among the present invention, utilizes polysilicon that groove is filled up again, can utilize the better trench fill ability of polysilicon to reduce the complexity of trench fill technology, utilize the high batch process ability of polysilicon, reduce the cost of technology.
Claims (8)
1. the manufacture method of a super junction MOSFET is characterized in that, comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and P-type extension;
(7) silicon nitride film and silicon oxide film removal are obtained P-type and N-type structure alternately;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
2. the manufacture method of super junction MOSFET according to claim 1 is characterized in that, utilizes polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
3. the manufacture method of a super junction MOSFET is characterized in that, comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on N-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that P-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and P-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained P-type and N-type structure smooth and that replace by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, P type trap, source electrode, the P+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
4. the manufacture method of super junction MOSFET according to claim 3 is characterized in that, utilizes polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
5. the manufacture method of a super junction MOSFET is characterized in that, comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) utilize silicon nitride as the barrier layer, carry out time etching or the cmp of polysilicon and N-type extension;
(7) silicon nitride film and silicon oxide film removal are obtained alternating N-type and P-type structure;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
6. the manufacture method of super junction MOSFET according to claim 5 is characterized in that, utilizes polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
7. the manufacture method of a super junction MOSFET is characterized in that, comprises the steps:
(1) the growth oxide-film and then is grown up on silicon chip as the silicon nitride of deielectric-coating as the resilient coating of the following deielectric-coating that will grow up on P-type epitaxial silicon chip;
(2) utilize photoetching to form the figure of groove;
(3) utilize silicon nitride to make mask or utilize photoresist to finish the etching of groove as mask;
(4) utilize epitaxy technique that N-type extension is inserted groove;
(5) utilize polysilicon that groove is filled up;
(6) pass through back to carve or grind removal silicon nitride and polysilicon above the silicon oxide layer and N-type extension;
(7) silicon nitride film and silicon oxide film are removed, obtained smooth and alternating N-type and P-type structure by cmp;
(8) utilize existing maturation process to form gate oxidation, polysilicon gate, N type trap, source electrode, the N+ contact zone, contact hole, surface metal, back metal obtains the MOSFET device.
8. the manufacture method of super junction MOSFET according to claim 7 is characterized in that, utilizes polysilicon that groove is filled up first growth one deck deielectric-coating before in the described step (5).
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| CN108091683A (en) * | 2017-12-11 | 2018-05-29 | 深圳迈辽技术转移中心有限公司 | Super-junction structure of semiconductor power device and preparation method thereof |
| CN108091683B (en) * | 2017-12-11 | 2020-09-22 | 深圳迈辽技术转移中心有限公司 | Super junction structure of semiconductor power device and manufacturing method thereof |
| CN111223931A (en) * | 2018-11-26 | 2020-06-02 | 深圳尚阳通科技有限公司 | Trench MOSFET and method of manufacturing the same |
| CN111223931B (en) * | 2018-11-26 | 2023-06-23 | 深圳尚阳通科技股份有限公司 | Trench MOSFET and manufacturing method thereof |
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Application publication date: 20101027 |