CN102244058A - Square flat semiconductor package without lead pins, manufacturing method and metal plate for the same - Google Patents

Abstract

A method for manufacturing semiconductor package without leads includes stamping metal plate to obtain chip pad and multiple convex welding pads, making at least one cross section area of said convex welding pad be greater than another cross section area under it and making at least one cross section area of chip pad be greater than another cross section area under it to make chip pad and convex welding pad be embedded in package colloid.

Description

Square flat semiconductor package without lead pins, manufacturing method and metal plate for the same

technical field

The present invention relates to a packaging structure and a manufacturing method thereof, in particular to a quad flat non-leaded semiconductor package (Quad Flat Non Leaded Package, QFN) and a manufacturing method thereof.

Background technique

The existing chip uses a lead frame (Lead Frame) as a chip carrier to form a semiconductor package, and the lead frame mainly includes a chip seat and a plurality of guide pins formed around the chip seat, and glued on the chip seat After connecting the chip and electrically connecting the chip and the lead pins with bonding wires, the packaging resin is used to coat the chip, the chip holder, the bonding wires and the inner section of the lead pins to form the semiconductor package with a lead frame.

As far as the development of integrated circuit technology is concerned, the semiconductor process is constantly evolving towards a more highly integrated process, and a high-density assembly structure is the goal pursued by the industry. The carrier used in the chip size package includes: lead frame, flexible substrate or rigid substrate, etc., because the lead frame has the characteristics of low cost and easy processing. , which is a commonly used chip size package type for electronic products; among them, the quad flat no-pin package (QFN) is a chip size package (lead frame based CSP) with a lead frame as the base material, which is characterized in that there is no There are external leads, that is, there are no external leads for electrical connection with the outside world, so that the overall size can be reduced.

Please refer to FIG. 4A, which is a cross-sectional view of a quadrilateral flat no-lead structure (QFN) disclosed in US Pat. A chip 42 is fixed on the lead frame 40 of the pin 41, and the chip 42 is electrically connected to the lead 41 by a bonding wire 43, forming a packaging material 44 to cover the lead frame 40, the chip 42, and the bonding wire 43 , and make the bottom surface of the pin 41 of the lead frame 40 exposed on the surface of the packaging material 44, so that the QFN semiconductor package structure can directly pass through the solder material (not shown in the figure) through the exposed surface of the exposed pin 41 And it is electrically connected with an external device such as a printed circuit board (printed circuit board).

The above-mentioned existing lead frame structure can provide a small number of I/Os, which cannot satisfy high-end products, and the pins may fall off after the singulation process. Furthermore, since the exposed pin 41 is flush with the surface of the packaging material 44, when the solder ball 46 is formed on the exposed pin 41 to electrically connect with the printed circuit board of the external device, as shown in FIG. 4B, the The solder balls 46 are prone to bridging (solder bridge), resulting in bridging or short circuit between the pins 41 , resulting in poor electrical connection.

In order to obtain more input/output quantities, there are also lead frames formed on copper foil substrates by etching to obtain more pins. However, the etching process steps are numerous and time-consuming, and regardless of the package shown in FIG. 4A Parts or lead frames obtained by etching have the problem of glue overflow when filling the encapsulant, which makes it impossible to implant solder balls and affects the electrical connection between solder balls and pins. In addition, the structure of the lead frame formed by etching is separated and incomplete, and there is often a situation of desoldering during ultrasonic welding.

Therefore, in view of the above-mentioned problems, how to provide more input/output quantities with a simplified process and avoid problems such as pin drop-off and packaging colloid overflow in existing semiconductor packages has become an urgent problem to be solved at present. .

Contents of the invention

In view of the various deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a quadrilateral flat semiconductor package without lead pins and its manufacturing method and a metal plate for manufacturing the semiconductor package, providing more The number of inputs/outputs can be reduced, and problems such as pin drop-off and packaging colloid overflow of existing semiconductor packages can be avoided.

In order to achieve the above object, the present invention provides a quadrilateral flat semiconductor package without leads, comprising: a chip pad, wherein, within the thickness range of the chip pad, at least one cross-sectional area of the chip pad is larger than its Another cross-sectional area below; a plurality of bump pads are arranged around the chip pad, wherein, within the thickness range of the bump pad, at least one cross-sectional area of the bump pad is larger than another cross-section below it area, and the top surface of the bump pad is higher than the top surface of the chip pad; the chip arranged on the chip pad; the bonding wire electrically connects the chip and each of the bump pads; and the encapsulant covers the chip pad. The chip pads, bump pads, chips and bonding wires are placed so that the chip pads and bump pads are embedded in the encapsulation compound and the bottom surfaces of the bump pads and chip pads are exposed.

In order to obtain the semiconductor package of the present invention, the present invention also provides a method for making a square flat semiconductor package without lead pins, comprising: preparing a metal plate defining a plurality of chip placement areas; stamping the metal plate with a mold, A chip pad is formed on each of the chip-placement areas on the metal plate, and a plurality of bump pads are formed on the periphery of the chip-placement area, wherein, within the thickness range of the chip pad and the bump pad, the bump pads At least one cross-sectional area of the pad is larger than another cross-sectional area below it, and at least one cross-sectional area of the chip pad is larger than another cross-sectional area below it, and the bottom surface of the bump pad is higher than the bottom surface of the chip pad; Place a chip on each of the chip pads; electrically connect the chip and the bump pad with a bonding wire; cover the metal plate, the chip, and the bonding wire with encapsulant, so that the bump pad is embedded in the encapsulant; removing the bottom of the metal plate, distributing the chip pad and each of the bump pads at intervals; and cutting the encapsulant to form a plurality of semiconductor packages.

In the aforementioned manufacturing method, the mold may include a male mold, a female mold, and a plurality of inserts, and the female mold has a plurality of arrayed cavities and grooves for communicating with the cavities on the same row, Wherein, the groove is provided for the insert to slide therein, so that the area of the opening of the cavity is smaller than the area of the bottom of the cavity.

In another embodiment, the stamping step of forming the die pad and bump pad includes stamping the metal plate with a die to form a plurality of die pad and bump pad; and pressing the die pad and bump pad top surface, so that within the thickness range of the chip pad and the bump pad, at least one cross-sectional area of the bump pad is larger than another cross-sectional area below it, and at least one cross-sectional area of the chip pad is larger than its Another cross-sectional area below.

On the other hand, the present invention also provides a metal plate for manufacturing a quadrilateral flat semiconductor package without lead pins, comprising: a plurality of bump pads integrally formed on the metal plate, and surrounded by the bump pads A chip placement area is provided, wherein, within the thickness range of the bump pad, at least one cross-sectional area of the bump pad is larger than another cross-sectional area below it; a chip pad is located in the chip placement area, wherein, in the Within the thickness range of the chip pad, at least one cross-sectional area of the chip pad is larger than another cross-sectional area below it; and a plurality of holes are correspondingly formed on the bottom surface of each of the bump pads.

It can be seen from the above that the semiconductor package and its manufacturing method of the present invention are to stamp out the bump pads on the metal plate first, then place and electrically connect the chips and form the encapsulation gel, and then perform the singulation operation, which can avoid embarrassment. There is a problem of glue overflow when pouring the encapsulant. In addition, the bump pad on the metal plate of the present invention has the function of embedding, which can prevent the bump pad from falling off from the encapsulant after forming the encapsulant. In addition, the top surface of the bump pad is higher than the top surface of the chip pad, which can reduce the height of the bonding wire and reduce the volume of the overall package. The semiconductor package and the manufacturing method of the present invention not only prevent glue overflow and bump pads from falling off, but also have the advantages of simplifying the process and providing more input/output quantities.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Fig. 1A to Fig. 1E " are the schematic diagrams of the manufacturing method of the quadrilateral flat semiconductor package without guide pins of the present invention, wherein Fig. 1B' is a top view of the master mold of Fig. 1B; Fig. 1D' is a schematic diagram of a semiconductor package with holes, Fig. 1E is a schematic diagram of a semiconductor package with bump pads flush with the sides of the encapsulant; and FIG. 1E' is a schematic diagram of a semiconductor package with a solder mask;

2A to 2C are schematic diagrams of another method for forming bump pads according to the present invention;

3A to 3C are schematic diagrams of another method for stamping and forming chip pads according to the present invention, wherein FIG. 3C is a schematic diagram of a semiconductor package with chip pads; and

4A and 4B are cross-sectional views of a conventional quad flat no-lead (QFN) package with a lead frame as a chip carrier.

Among them, reference signs

1, 3 semiconductor packages 10, 20, 30 metal plates

11, 31 chip area 12, 22, 32 mold

121 male mold 122 female mold

123 Insert 1221 Recess

1222 Groove 13, 23, 33 Convex Pads

131 holes 14, 34, 42 chips

15, 35, 43 welding wire 16, 36 packaging colloid

17, 37, 46 solder balls 18 solder mask

181 hole 221, 221'upper mold

222 lower mold 19, 29, 38 chip pads

381 convex pad 40 lead frame

41-pin 44-pin package

Detailed ways

The implementation of the present invention will be described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should also be noted that the "top surface" and "bottom surface" described in this specification are not absolute spatial concepts, but change with the spatial relationship of the constituent elements, that is, inverting the semiconductor package shown in this pattern In case of pieces, the "top" becomes the "bottom" and the "bottom" becomes the "top". Therefore, the use of these terms "top surface" and "bottom surface" is used to explain the connection relationship between the constituent elements in the semiconductor package disclosed in the present invention, so that the semiconductor package disclosed in the present invention is within the equivalent range There are reasonable changes and substitutions, but not intended to limit the scope of the present invention to a specific embodiment (Embodiment).

first embodiment

Please refer to FIG. 1A to FIG. 1E ”, which illustrate the manufacturing method of the quadrilateral flat semiconductor package without leads of the present invention.

As shown in FIG. 1A, a metal plate 10 defining a plurality of chip placement areas 11 is prepared. The metal plate can be copper. In addition, the upper and lower surfaces of the metal plate 10 can be formed with metal layers by electroplating, which can include metal layers selected from One or more materials from the group consisting of gold, palladium, silver, copper and nickel, e.g. gold/palladium/nickel/palladium layers sequentially or gold/nickel/copper/nickel/silver, gold/nickel/copper /silver, palladium/nickel/palladium, gold/nickel/gold or palladium/nickel/gold multi-layer metal one of them.

As shown in FIG. 1B and FIG. 1B', the metal plate 10 is stamped with a mold 12 to form a chip pad 19 in each of the chip placement areas 11 on the metal plate 10, and a plurality of protrusions are formed on the periphery of the chip placement area 11. Welding pad 13, wherein, within the thickness h and h' range of the chip pad 19 and the bump pad 13, at least one cross-sectional area of the bump pad 13 is larger than another cross-sectional area below it, and the chip pad At least one cross-sectional area of the pad 19 is larger than another cross-sectional area below it, and the bottom surface of the bump pad 13 is higher than the bottom surface of the chip pad 19 . The bump pad 13 can be dovetail-shaped or semi-dovetail-shaped. As shown in FIG. The area of is greater than the area of another cross-section below. In addition, after stamping the metal plate, forming a metal layer on the upper and lower surfaces of the metal plate (not shown).

In practice, the mold 12 includes a male mold 121, a female mold 122 and a plurality of inserts 123, and as shown in FIG. The groove 1222 is used to communicate with the recesses 1221 located on the same row, wherein the groove 1222 is for the insert 123 to slide therein, so that the opening area of the recess 1221 is smaller than the bottom area of the recess 1221, so that after stamping A dovetail-shaped bump pad 13 is obtained.

As shown in FIG. 1C, a chip 14 is placed on each of the chip pads 19, and then the chip 14 and the bump pad 13 are electrically connected with the bonding wire 15; then the metal plate 10, the chip 14 and the bonding wire 15 Cover the encapsulant 16 on the top, because the area of any cross-section of the dovetail-shaped bump pad 13 is greater than the area of the other cross-section below (in the present invention, the cross-section of the hole 131 in the bump pad 13 is also calculated in the bump solder pad 13. pad 13), for example, the area of the top surface is greater than the area of the bottom surface, so that the bump pad 13 is embedded in the encapsulant 16. In addition, because the bottom surface of the bump pad 13 is higher than the bottom surface of the chip pad 19, And the top surface of the bump pad 13 is higher than the top surface of the chip pad 19, which can reduce the height of the wire bonding and reduce the volume of the overall package. Moreover, because the metal plate is a continuous structure, it can reduce desoldering during ultrasonic welding. Defects. Furthermore, since the metal plate is still in a continuous structure when forming the encapsulation gel, the problem of glue overflow can be prevented.

As shown in FIG. 1D , the bottom of the metal plate 10 is removed by milling or etching, so that the die pads 19 and bump pads 13 are spaced apart from each other. Referring to Fig. 1D' again, different from the bottom of the chip pad 19 and bump pad 13 in Fig. 1D being flush with the bottom of the encapsulant, when removing the bottom of the metal plate 10, since the stamping depth can be set during stamping, it can If necessary, holes 131 are formed on the bottom surface of the chip pads and bump pads 13 obtained by removing the metal plate 10. As shown in FIG. Better bonding strength is provided between them, and finally the encapsulant 16 is cut to form a plurality of semiconductor packages 1 . On the other hand, when two adjacent packaging units have shared bump pads, in the cutting step, as shown in FIG. The side of the outermost bump pad 13 of the resulting semiconductor package is exposed and flush with the side of the encapsulant 16 . Of course, as shown in FIG. 1E , two adjacent packaging units do not have a shared bump pad 13 , and the encapsulant 16 covers the sides of the bump pad 13 .

In addition, as shown in FIG. 1E ”, it may also include forming a solder resist layer 18 on the bottom surface of the encapsulant 16 after removing the metal plate 10, and making the solder resist layer 18 have a plurality of corresponding positions exposed. The chip pad 19 and the solder mask opening 181 of the bump pad 13. In this example, although the bump pad 13 with the hole 131 is used for illustration, it is not limited to this aspect.

second embodiment

This embodiment is roughly the same as the aforementioned manufacturing method, the difference lies in the different stamping methods. 2A to 2C, the step of forming the chip pads and bump pads by stamping includes first punching the metal plate 20 with a mold 22 comprising an upper mold 221 and a lower mold 222 to form a plurality of chip pads 29 and Protrusion welding pad 23; And once again, suppress the top surface of the chip pad 29 and the convex welding pad 23, so that within the thickness range of the chip pad 29 and the convex welding pad 23, even if the top surface of the convex welding pad 23 is not the largest area, there is still a relationship that at least one cross-sectional area is greater than the other cross-sectional area below it, so that after the encapsulation compound is formed, the bump pad 23 is embedded in the encapsulation compound, and similarly, the chip pad 29 At least one cross-sectional area is larger than another cross-sectional area below it. Specifically, as shown in FIG. 2B , another upper mold 221' can be used to press the top surface of the chip pad 29 and the bump pad 23 again, and finally the metal plate 20 with the bump pad 23 can be obtained by demoulding.

third embodiment

This embodiment is roughly the same as the aforementioned manufacturing method, the difference lies in the shape of the chip pad. As shown in FIG. 3A, the step of stamping the metal plate 30 also includes stamping the chip area 31 with a mold 32 to form a chip pad 38, which is composed of a plurality of bumps 381, and its shape can be similar to that of the bump pad. 33 same. Likewise, within the thickness range of the die pad 38 , at least one cross-sectional area of the die pad 38 is larger than another cross-sectional area below it.

According to the aforementioned manufacturing method, the present invention provides a square flat semiconductor package 1, 3 without guide pins, as shown in Figure 1E and Figure 3C, the semiconductor package 1, 3 includes: chip pads 19, 38, wherein , within the thickness range of the chip pad 19, 38, at least one cross-sectional area of the chip pad is larger than another cross-sectional area below it; a plurality of bump pads 13, 33 are arranged on the chip pad 19 , 38, wherein, within the thickness range of the bump pad 13, 33, at least one cross-sectional area of the bump pad 13, 33 is larger than another cross-sectional area below it, and the bump pad 13, 33 The top surface is higher than the top surface of the chip pads 19, 38; chips 14, 34 are arranged on the chip pads 19, 38; bonding wires 15, 35 are electrically connected to the chips 14, 34 and the bump pads 13,33; and encapsulation colloid 16,36, coating this set chip pad 19,38, bump pad 13,33, chip 14,34 and bonding wire 15,35, make this set chip pad 19,38 and bump welding The pads 13 , 33 are embedded in the encapsulant 16 , 36 and expose the bottom surfaces of the bump pads 13 , 33 and the chip pads 19 , 38 . In addition, solder balls 17 , 37 may be connected to the bottom surfaces of the bump pads 13 , 33 and chip pads 19 , 38 .

In the semiconductor package of the present invention, the bump pads 13 and the die pads 19 can be dovetail-shaped as shown in FIG. 1E , or can be semi-dovetail-shaped or other shapes.

As shown in FIG. 1E', the semiconductor package can also include a solder resist layer 18, which is formed on the bottom surface of the encapsulant 16, and the solder resist layer 18 has a plurality of corresponding exposed chip pads 19 and bump soldering. The solder mask opening 181 of the pad 13 .

On the other hand, according to the aforementioned manufacturing method, the present invention provides a metal plate for manufacturing a square flat semiconductor package without lead pins. As shown in FIG. 1C, the metal plate 10 includes: a plurality of bump pads 13, It is integrally formed on the metal plate 10, and the bump pads 13 surround the chip area 11, wherein, within the thickness range of the bump pad 13, at least one cross-sectional area of the bump pad 13 is larger than Another cross-sectional area below it; the chip pad 19 is located in the chip area 11, wherein, within the thickness range of the chip pad 19, at least one cross-sectional area of the chip pad 19 is greater than another cross-sectional area below it area; and a plurality of holes 131 are correspondingly formed on the bottom surface of each of the bump pads 13 .

In the semiconductor package and its manufacturing method of the present invention, the bump pads are stamped out on the metal plate first, then placed and electrically connected to the chip and form the packaging colloid, and then the singulation operation is performed, which can avoid the prior art potting and packaging In addition, the chip pads and bump pads on the metal plate of the present invention have the function of embedding, which can prevent the bump pads from falling out of the packaging gel after forming the packaging gel, thereby improving reliability. And preferably, the stamping method can also make the height of the chip pad lower than the bump pad, which is beneficial to reduce the height of the package, reduce the volume and improve the thermal conductivity. The semiconductor package and the manufacturing method of the present invention not only prevent glue overflow And the protruding welding pad falls off, and has the advantages of simplifying the manufacturing process and providing more input/output quantities.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (12)

1. A quadrilateral flat semiconductor package without leads, characterized in that it comprises: A die pad, wherein, within the thickness range of the die pad, at least one cross-sectional area of the die pad is larger than another cross-sectional area below it; A plurality of bump pads are arranged around the chip pad, wherein, within the thickness range of the bump pad, at least one cross-sectional area of the bump pad is larger than another cross-sectional area below it, and the bump pad The top surface of the chip pad is higher than the top surface of the chip pad; The chip is arranged on the chip pad; bonding wires electrically connecting the chip and each of the bump pads; and The encapsulation colloid covers the chip pads, bump pads, chips and bonding wires so that the chip pads and bump pads are embedded in the package colloid and expose the bottom surfaces of the bump pads and chip pads. 2 . The square flat semiconductor package without leads according to claim 1 , wherein the bump pad is dovetail or semi-dovetail. 3 . 3 . The quadrilateral flat semiconductor package without leads according to claim 1 , wherein the chip pad is in a dovetail shape or a semi-dovetail shape. 4 . 4. The quadrilateral flat semiconductor package without lead pins according to claim 1, further comprising a solder resist layer formed on the bottom surface of the encapsulant, and the solder resist layer has a plurality of supply pairs exposing each of the Open holes in the solder mask layer for chip pads and bump pads. 5. A method for making a quadrilateral flat semiconductor package without guide pins, characterized in that it comprises: preparing a metal plate defining a plurality of chip placement areas; Stamping the metal plate with a mold to form a chip pad on each of the chip areas on the metal plate, and form a plurality of bump pads on the periphery of the chip area, wherein the thickness of the chip pad and the bump pad Within the range, at least one cross-sectional area of the bump pad is larger than another cross-sectional area below it, and at least one cross-sectional area of the chip pad is larger than another cross-sectional area below it, and the bottom surface of the bump pad is high on the bottom surface of the chip pad; Place chips on each of the chip pads; electrically connecting the chip and the bump pads with bonding wires; Covering the metal plate, chip and bonding wire with encapsulation compound, so that the bump pad is embedded in the encapsulation compound; removing the bottom of the metal plate so that the chip pad and each of the bump pads are spaced apart from each other; and The encapsulant is cut to form a plurality of semiconductor packages. 6. The method for manufacturing a quadrilateral flat semiconductor package without guide pins according to claim 5, wherein the mold comprises a male mold, a female mold and a plurality of inserts, and the female mold has a plurality of arrayed arrangements The recesses and grooves are used to communicate with the recesses located in the same row, wherein the grooves allow the inserts to slide therein, so that the opening area of the recesses is smaller than the bottom area of the recesses. 7. The method for manufacturing a quadrilateral flat semiconductor package without lead pins according to claim 5, wherein the step of forming the chip pad and the bump pad by stamping comprises punching the metal plate with a mold to form a plurality of pads. chip pad and bump pad; and pressing the top surface of the chip pad and bump pad so that within the thickness range of the chip pad and bump pad, at least one cross-sectional area of the bump pad is larger than another A cross-sectional area, and at least one cross-sectional area of the die pad is larger than another cross-sectional area below it. 8 . The method for manufacturing a quadrilateral flat semiconductor package without leads according to claim 5 , wherein the top surface of the bump pad is higher than the top surface of the chip pad. 9 . 9 . The method for manufacturing a quadrilateral flat semiconductor package without leads according to claim 5 , further comprising forming a metal layer on the upper and lower surfaces of the metal plate before or after stamping the metal plate. 10 . The method for manufacturing a quadrilateral flat semiconductor package without leads according to claim 6 , wherein the bump pads are dovetail-shaped or semi-dovetail-shaped. 11 . 11. The manufacturing method of the quadrilateral flat semiconductor package without lead pins according to claim 5, further comprising forming a solder mask on the bottom surface of the encapsulant after removing the metal plate, and making the The solder resist layer has a plurality of solder resist layer openings for correspondingly exposing the corresponding chip pads and bump pads. 12. A metal plate for manufacturing a quadrilateral flat semiconductor package without leads, characterized in that it comprises: A plurality of bump pads are integrally formed on the metal plate, and the bump pads surround the chip area, wherein, within the thickness range of the bump pads, at least one cross-sectional area of the bump pads greater than the area of another cross-sectional area beneath it; A chip pad is located in the chip pad area, wherein, within the thickness range of the chip pad, at least one cross-sectional area of the chip pad is larger than another cross-sectional area below it; and A plurality of holes are correspondingly formed on the bottom surface of each bump pad.

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