CN104167369B - Manufacturing method of chip packaging structure - Google Patents
Manufacturing method of chip packaging structure Download PDFInfo
- Publication number
- CN104167369B CN104167369B CN201310336975.7A CN201310336975A CN104167369B CN 104167369 B CN104167369 B CN 104167369B CN 201310336975 A CN201310336975 A CN 201310336975A CN 104167369 B CN104167369 B CN 104167369B
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- Prior art keywords
- carrier
- chip
- patterned metal
- metal layer
- dielectric layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 143
- 229910052751 metal Inorganic materials 0.000 claims abstract description 143
- 238000000034 method Methods 0.000 claims abstract description 95
- 239000000084 colloidal system Substances 0.000 claims abstract description 37
- 238000012856 packing Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 140
- 238000001465 metallisation Methods 0.000 description 11
- 239000000178 monomer Substances 0.000 description 11
- 238000003466 welding Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000012792 core layer Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A method for manufacturing a chip packaging structure comprises the following steps. First, a first carrier is provided. The first loader comprises a first surface and a patterned metal layer. The patterned metal layer is disposed on the first surface. Then, a dielectric layer is formed on the first surface to cover the patterned metal layer. Then, the patterned metal layer and the dielectric layer on the first carrier are transferred to the second carrier. Then, a plurality of chips are arranged on the patterned metal layer, so that the chips are electrically connected with the patterned metal layer. And finally, forming a packaging colloid on the second loader, wherein the packaging colloid covers the chip, the patterned metal layer and the dielectric layer. Then, the second carrier is removed. And then, cutting the packaging colloid and the dielectric layer between the chips to form a plurality of chip packaging structures.
Description
Technical field
The invention relates to a kind of manufacture method of encapsulating structure, and in particular to a kind of chip-packaging structure
Manufacture method.
Background technology
At present in semiconductor processing, chip packaging carrying plate is one of commonly used potted element.Chip packaging carrying plate
A for example, multilayer circuit board, it is mainly superimposed by multilayer line layer and multilayer dielectric layer and is constituted.
In general, above-mentioned multilayer circuit board was to make multilayer line and multilayer dielectric up and down in a core substrate in the past
Layer, and core substrate is to have certain thickness carrier.Multilayer line and multilayer dielectric layer are then with fully-additive process（fully
additive process）, semi-additive process（semi-additive process）, subtractive process（subtractive process）
Or other methods being suitable for are alternately stacked on core substrate.With electronic component slimming, if cannot be effectively reduced
The thickness of core substrate, certainly will be unfavorable for reducing the gross thickness of chip-packaging structure.The thickness of core substrate thus change need to be coordinated
Thin, to configure in the confined space of electronic component.However, when the reduced down in thickness of core substrate, the core substrate of slimming
Due to rigid deficiency, therefore easily increase degree of difficulty and the fraction defective of substrate process and packaging technology.
Content of the invention
The present invention provides a kind of manufacture method of chip-packaging structure, and the chip-packaging structure that it is produced does not have support plate
Core Rotating fields, thus there is relatively thin package thickness.
The present invention proposes a kind of manufacture method of chip-packaging structure, and it comprises the following steps.First, one first is provided to hold
Carry device.First carrier includes a first surface and a patterned metal layer.Patterned metal layer is arranged on first surface.Connect
, form a dielectric layer on first surface, with overlay pattern metal level.Then, by the patterned gold on the first carrier
Belong to layer and dielectric layer is transferred on one second carrier.Then, multiple chips are set on patterned metal layer, make chip electrical
Connecting pattern metal level.Afterwards, form a packing colloid on the second carrier, and packing colloid covers chip, patterning
Metal level and dielectric layer.Then, remove the second carrier.Afterwards, the packing colloid between diced chip and dielectric layer is many to be formed
Individual chip-packaging structure.
The present invention proposes a kind of manufacture method of chip-packaging structure, and it comprises the following steps.First, one first is provided to hold
Carry device.First carrier includes a metal level, is arranged on the first carrier.Then, form a dielectric layer on metal level.Will
Metal level on first carrier and dielectric layer are transferred on one second carrier, and its dielectric layer attaches the second carrier.Connect
, remove the first carrier to expose metal level, and a Patternized technique is carried out to metal level, to form a pattern metal
Layer, patterned metal layer includes multiple conductive traces.Afterwards, multiple chips are set on patterned metal layer, make chip electrical
Connecting pattern metal level.Then, form a packing colloid on the second carrier, and packing colloid covers chip, patterning
Metal level and dielectric layer.Afterwards, remove the second carrier.Then, the packing colloid between diced chip and dielectric layer, with shape
Become multiple chip-packaging structures.
Based on above-mentioned, the present invention is prior to forming patterned metal layer and dielectric layer on the first carrier, then will be patterned into gold
Belong to layer and dielectric layer is transferred to and engages, covers the techniques such as packing colloid to carry out follow-up chip on the second carrier, afterwards, then
Remove the second carrier and continue and complete follow-up chip package process.Additionally, the present invention also can be prior to shape on the first carrier
Become a metal level and dielectric layer, then metal level and dielectric layer are transferred on the second carrier, then just metal level is carried out
Patterning, and carry out follow-up chip joint, cover the techniques such as packing colloid, afterwards, then remove the second carrier, to have continued
Become follow-up chip package process.So, the chip-packaging structure technique of the present invention can produce no support plate core layer structure
Chip-packaging structure, thus so that the thickness of chip-packaging structure is minimized.Additionally, the present invention first combines pattern with dielectric layer
Change metal level, re-form the packing colloid covering chip, patterned metal layer and dielectric layer afterwards, by this two benches sealing
Operation, makes the chip-packaging structure of the present invention have two kinds of glue-lines, therefore can be by from two kinds of different heat expansion coefficients
（Coefficients of thermal expansion, CTE）The situation to adjust chip-packaging structure warpage for the glue material.
It is that the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate appended accompanying drawing
It is described in detail below.
Brief description
Figure 1A to Fig. 1 I is that a kind of section of the manufacture method of the chip-packaging structure according to one embodiment of the invention shows
It is intended to.
Fig. 2A to Fig. 2 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Schematic diagram.
Fig. 3 A to Fig. 3 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Schematic diagram.
Fig. 4 A to Fig. 4 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Schematic diagram.
【Symbol description】
100、200、300、400：Chip-packaging structure
100a、200a、300a、400a：Sphere grid array encapsulates
100b、200b、300b、400b：Pad lattice array package
110、210、310、410：First carrier
112、212、312：First surface
120、220、320、420：Metal level
122、222、322、422：Patterned metal layer
124a、224a、324a、424a：Connection pad
130、230、330、430：Dielectric layer
132、432：Opening
140、240、340、440：Second carrier
150、250、350、450：Chip
160、260、360、460：Packing colloid
170、270、370、470：Soldered ball
180、280、380、480：Pad-type terminal
226、324：Articulamentum
226a、326a：Conductive trace
228：Patterning coating
Specific embodiment
Figure 1A to Fig. 1 I is that a kind of section of the manufacture method of the chip-packaging structure according to one embodiment of the invention shows
It is intended to.Referring to Figure 1A and Figure 1B, in the present embodiment, the manufacture method of chip-packaging structure comprises the following steps：First
First, provide one first carrier 110.First carrier 110 includes a first surface 112 and a patterned metal layer 122.Pattern
Change metal level 122 to be arranged on first surface 112.Specifically, in the present embodiment, patterned metal layer 122 is arranged at
Method on one surface 112 can be initially formed a metal level 120 in the first surface 112 of the first carrier 110 as shown in Figure 1A
On.Then, more as shown in Figure 1B, a Patternized technique is carried out to metal level 120, to form above-mentioned patterned metal layer 122,
Patterned metal layer 122 includes multiple conductive trace 122a, and wherein, Patternized technique is, for example, etch process.
Then, refer to Fig. 1 C, form a dielectric layer 130 on first surface 112.In the present embodiment, dielectric layer 130
It is comprehensively overlay pattern metal level 122.Specifically, dielectric layer 130 is, for example, packing colloid, and passes through such as mold
The mode of encapsulating is covered on patterned metal layer 122, but the present invention does not limit to the material of dielectric layer 130 and it is formed at
Mode on first surface 112.Then, referring to Fig. 1 C and Fig. 1 D, by the pattern on the first carrier 110 in Fig. 1 C
Change metal level 122 and dielectric layer 130 is transferred on second carrier 140 of Fig. 1 D.Specifically, shift patterned metal layer
122 and the mode of dielectric layer 130 for example, the second carrier 140 is attached on the surface of dielectric layer 130 of Fig. 1 C, then remove
First carrier 110, to expose patterned metal layer 122.
Please referring next to Fig. 1 E, multiple chips 150 are set on patterned metal layer 122, make chip 150 electric connection figure
Case metal level 122, afterwards, re-forms a packing colloid 160 on the second carrier 140, and packing colloid 160 covers chip
150th, patterned metal layer 122 and dielectric layer 130.In the present embodiment, chip 150 is to be arranged in the way of such as flip chip bonding
On patterned metal layer 122, but the present invention does not limit to the mode that chip 150 is arranged on patterned metal layer 122, at this
In other bright embodiments not illustrated, chip 150 also for example can be arranged at patterned metal layer 122 in the way of routing joint
On.
Then, referring to Fig. 1 E and Fig. 1 F, remove the second carrier 140 in Fig. 1 E, to expose dielectric layer
130, in dielectric layer 130, its split shed 132 exposes the figure of part to re-form multiple openings 132 as shown in Figure 1 F afterwards
Case metal level 122.Then, in opening 132, to form multiple connection pad 124a, wherein connection pad 124a is respectively for filling conduction material
It is electrically connected with the conductive trace 122a of patterned metal layer 122.Afterwards, as shown in Figure 1 G, monomer metallization processes are carried out, meaning
That is, the packing colloid 160 between diced chip 150 and dielectric layer 130, makes separated from one another between chip 150, to form multiple chip envelopes
Assembling structure 100.So, that is, the technique completing the chip-packaging structure 100 of the present embodiment.
It should be noted that in one embodiment of this invention, multiple soldered balls 170 also can be first respectively provided with connection pad 124a
On, then carry out monomer metallization processes, to form multiple sphere grid arrays as shown in fig. 1h（Ball Grid Array, BGA）Encapsulation
100a, enables chip-packaging structure to be connected with other electronic components by soldered ball 170.The embodiment that other do not illustrate in the present invention
In, after also can forming multiple connection pad 124a, form a welding resisting layer on dielectric layer 130 and connection pad 124a, and corresponding connection pad
124a forms multiple openings to define Zhi Qiu area on welding resisting layer, then arranges soldered ball 170 again in Zhi Qiu area, makes soldered ball
170 are connected with connection pad 124a.Certainly, in another embodiment of the invention, can also multiple pad-type terminal 180 replacement soldered balls
170 are arranged on connection pad 124a, then carry out monomer metallization processes, to form multiple pad lattice arrays as shown in Figure 1 I（Land Grid
Array, LGA）Encapsulation 100b, enables chip-packaging structure to be connected with other electronic components by pad-type terminal 180.
So, the chip-packaging structure 100 that the present embodiment is formed does not have support plate core Rotating fields and anti-welding green paint
（Solder Mask）, thus its package thickness can be reduced.Additionally, the present embodiment is first using packing colloid as dielectric layer 130, it
Re-form the packing colloid 160 covering chip 150, patterned metal layer 122 and dielectric layer 130 afterwards, by two benches sealing
Operation, makes the chip-packaging structure 100 of the present embodiment have two-layer packing colloid, thus can be by from two kinds of different heat expansions
Coefficient（Coefficients of thermal expansion, CTE）Packing colloid stick up adjusting chip-packaging structure 100
Bent situation.
Fig. 2A to Fig. 2 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Schematic diagram.Here should be noted that, the chip envelope of the manufacture method of the chip-packaging structure of the present embodiment and Figure 1A to Fig. 1 I
The manufacture method of assembling structure is substantially similar, therefore eliminates the explanation of constructed content.Explanation with regard to clipped can be joined
Examine previous embodiment, it is no longer repeated for the present embodiment.
Referring to Fig. 2A to Fig. 2 C, the manufacture method of the chip-packaging structure of the present embodiment is also first to provide first to hold
Carry device 210, the wherein first carrier 210 includes first surface 212 and patterned metal layer 222, and patterned metal layer 222 sets
It is placed on first surface 212.Only in the present embodiment, the method that patterned metal layer 222 is arranged on first surface 212 can be first
As shown in Figure 2 A, form a metal level 220 on the first carrier 210, and be surface-treated on metal level 220 to be formed
One patterning coating 228.Then, as shown in Figure 2 B, for mask, one patterning is carried out to metal level 220 to pattern coating 228
Technique, to form patterned metal layer 222, wherein, patterned metal layer 222 includes an articulamentum 226 and multiple connection pad
224a, and connection pad 224a is on articulamentum 226.Specifically, Patternized technique be, for example, half etch process, imply that only in
Etch multiple connection pad 224a on the metal level 220 of Fig. 2A, and connection pad 224a is still connected to each other with articulamentum 226.
Then, as shown in Figure 2 C, form dielectric layer 230 on first surface 212.In the present embodiment, dielectric layer 230 is
At least it is filled between connection pad 224a and exposes a surface of connection pad 224a, and other embodiments not illustrated in the present invention
In, dielectric layer 230 also can be completely covered connection pad 224a.Specifically, dielectric layer 230 is, for example, a welding resisting layer（Solder
Resist）, and be filled between connection pad 224a by way of printing is coated with, certainly, the present invention is not limited thereto.Then,
Referring to Fig. 2 C and Fig. 2 D, by the patterned metal layer 222 on the first carrier 210 in Fig. 2 C and 230 turns of dielectric layer
Move on second carrier 240 of Fig. 2 D.In the present embodiment, the mode example of transfer patterned metal layer 222 and dielectric layer 230
As on the surface that the dielectric layer 230 for being attached at the second carrier 240 in Fig. 2 C and connection pad 224a expose, then remove first and hold
Carry device 210, to expose the articulamentum 226 of patterned metal layer 222.Then, then referring concurrently to Fig. 2 D and Fig. 2 E, in Fig. 2 D
Articulamentum 226 carry out a Patternized technique, to form the conductive trace of the multiple correspondences the plurality of connection pad 224a in Fig. 2 E
226a.
Then, as shown in Figure 2 F, multiple chips 250 are set on the conductive trace 226a of patterned metal layer 222, make core
Piece 250 is electrically connected with conductive trace 226a, afterwards, re-forms a packing colloid 260 on the second carrier 240, and packaging plastic
Body 260 covers chip 250, patterned metal layer 222 and dielectric layer 230.In the present embodiment, chip 250 is with such as upside-down mounting
The mode of weldering is arranged on patterned metal layer 222, but the present invention does not limit to chip 250 and is arranged at patterned metal layer 222
On mode.Then, referring to Fig. 2 F and Fig. 2 G, remove the second carrier 240 in Fig. 2 F, to expose connection pad 224a
Surface, in other embodiments not illustrated of the present invention, when connection pad 224a is to be covered by dielectric layer 230, then removing
After second carrier 240, corresponding connection pad 224a forms opening, so that the surface of connection pad 224a exposes in dielectric layer 230.Connect
And carry out monomer metallization processes again, this means, the packing colloid 260 between diced chip 250 and dielectric layer 230, to form multiple chips
Encapsulating structure 200.So, that is, the technique completing the chip-packaging structure 200 of the present embodiment.
It should be noted that in one embodiment of this invention, also can first be respectively provided with multiple as previously described in a prior embodiment
Soldered ball 270 is on the surface that connection pad 224a exposes, then carries out monomer metallization processes, to form multiple sphere grid arrays as illustrated in figure 2h
Encapsulation 200a, enables chip-packaging structure to be connected with other electronic components by soldered ball 270.The reality that other do not illustrate in the present invention
Apply in example, also can after removing the second carrier 240 and so that connection pad 224a is exposed, formed a welding resisting layer in dielectric layer 230 and
On connection pad 224a, and corresponding connection pad 224a forms multiple openings on welding resisting layer, to define Zhi Qiu area, then arranges soldered ball again
270 in Zhi Qiu area, so that soldered ball 270 is connected with connection pad 224a.And in another embodiment of the invention, can also multiple pad-type
Terminal 280 replacement soldered ball 270 is arranged on the surface of connection pad 224a exposure, then carries out monomer metallization processes, to form multiple such as figures
Pad lattice array package 200b shown in 2I, enables chip-packaging structure to be connected with other electronic components by pad-type terminal 280.
Fig. 3 A to Fig. 3 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Illustrate.Here should be noted that, the manufacture method of the chip-packaging structure of the present embodiment and the chip package of Figure 1A to Fig. 1 I
The manufacture method of structure is substantially similar, therefore eliminates the explanation of constructed content.Explanation with regard to clipped refers to
Above-described embodiment, it is no longer repeated for the present embodiment.
Referring to Fig. 3 A to Fig. 3 C, the manufacture method of the chip-packaging structure of the present embodiment is also to provide the first carrying
Device 310, the wherein first carrier 310 includes first surface 312 and patterned metal layer 322, and patterned metal layer 322 is arranged
On first surface 312.Only in the present embodiment, the method that patterned metal layer 322 is arranged on first surface 312 can first such as
Shown in Fig. 3 A, provide a metal level 320, wherein metal level 320 includes an articulamentum 324 and multiple conductive trace 326a, conductive
Trace 326a is located on articulamentum 324 that is to say, that conductive trace 326a is connected to each other with articulamentum 324.Then, refer to
Fig. 3 B, metal level 320 is arranged on the first carrier 310, makes conductive trace 326a attach the first carrier 310, afterwards, please
Referring concurrently to Fig. 3 B and Fig. 3 C, Patternized technique is carried out to the articulamentum 324 of the metal level 320 in Fig. 3 B, multiple right to be formed
Answer the connection pad 324a of conductive trace 326a.Above-mentioned patterned metal layer 322 is by conductive trace 326a and corresponding conduction mark
The connection pad 324a of line 326a is formed.
Then, refer to Fig. 3 D, form dielectric layer 330 on first surface 312.In the present embodiment, dielectric layer 330 is
At least be filled between connection pad 324a and conductive trace 326a and expose a surface of connection pad 324a, the present invention other not
In the embodiment illustrating, dielectric layer 330 also can be completely covered connection pad 324a.Specifically, dielectric layer 330 is, for example, welding resisting layer,
And be filled between connection pad 324a and conductive trace 326a by way of printing is coated with, or dielectric layer 330 is, for example, packaging plastic
Body, and be filled between connection pad 324a and conductive trace 326a by way of such as mold encapsulating and cover connection pad 324a, when
So, the present invention is not limited thereto.Afterwards, referring to Fig. 3 D and Fig. 3 E, by the figure on the first carrier 310 in Fig. 3 D
Case metal level 322 and dielectric layer 330 are transferred on one second carrier 340.In the present embodiment, shift patterned metal layer
322 and the mode of dielectric layer 330 for example, the second carrier 340 is attached at the dielectric layer 330 of Fig. 3 D and connection pad 324a exposes
Surface on, then remove the first carrier 310, to expose conductive trace 326a.
Hold above-mentioned, referring again to shown in Fig. 3 F, the multiple chips 350 of setting are in the conductive trace of patterned metal layer 322
On 326a, chip 350 is made to be electrically connected with conductive trace 326a.Afterwards, re-form a packing colloid 360 in the second carrier 340
On, and packing colloid 360 covers chip 350, patterned metal layer 322 and dielectric layer 330.Then, referring to Fig. 3 F and
Fig. 3 G, removes the second carrier 340 in Fig. 3 F to expose connection pad 324a, in other embodiments not illustrated of the present invention
In, if connection pad 324a is to be covered by dielectric layer 330, after removing the second carrier 340, corresponding connection pad 324a is in dielectric layer
Form opening, so that the surface of connection pad 324a exposes in 330.Then monomer metallization processes are carried out again, to form multiple chip envelopes
Assembling structure 300.So, that is, the technique completing the chip-packaging structure 300 of the present embodiment.It should be noted that the present invention's
In one embodiment, can first be respectively provided with multiple soldered balls 370 on the surface that connection pad 324a exposes, then carry out monomer metallization processes, with
Form multiple sphere grid array encapsulation 300a as shown in figure 3h, enable chip-packaging structure to pass through soldered ball 370 and other electronics units
Part connects.In the embodiment that other do not illustrate in the present invention, removing the second carrier 340 and connection pad 324a can be made to expose
Afterwards, form a welding resisting layer on dielectric layer 330 and connection pad 324a, and corresponding connection pad 324a form multiple openings on welding resisting layer,
To define Zhi Qiu area, soldered ball 370 is then set in Zhi Qiu area again, so that soldered ball 370 is connected with connection pad 324a.The present invention's
In another embodiment, multiple pad-type terminal 380 replacement soldered balls 370 can also be arranged on connection pad 324a, then carry out monomer chemical industry
Skill, to form multiple pad lattice array package 300b as shown in fig. 31.Enable chip-packaging structure pass through pad-type terminal 380 and its
He connects electronic component.
Fig. 4 A to Fig. 4 I is a kind of section of the manufacture method of the chip-packaging structure according to another embodiment of the present invention
Schematic diagram.Here should be noted that, the chip envelope of the manufacture method of the chip-packaging structure of the present embodiment and Figure 1A to Fig. 1 I
The manufacture method of assembling structure is substantially similar, therefore eliminates the explanation of constructed content.Explanation with regard to clipped can be joined
Examine above-described embodiment, it is no longer repeated for the present embodiment.
Please refer to Fig. 4 A, the manufacture method of the chip-packaging structure of the present embodiment comprises the following steps：First, provide one
First carrier 410.First carrier 410 includes a metal level 420, is arranged on the first carrier 410.Then, as Fig. 4 B
Shown, form a dielectric layer 430 on metal level 420.Afterwards, referring to Fig. 4 B and Fig. 4 C, first in Fig. 4 B is held
Carry the metal level 420 on device 410 and dielectric layer 430 is transferred on the second carrier 440 in Fig. 4 C.In the present embodiment, turn
The mode of shifting metal level 420 and dielectric layer 430 is, for example, the surface of the dielectric layer 430 that the second carrier 440 is attached at Fig. 4 B
On, then remove the first carrier 410, to expose metal level 420.Then, referring to Fig. 4 C and Fig. 4 D, in Fig. 4 C
Metal level 420 carries out a Patternized technique, and to form the patterned metal layer 422 of Fig. 4 D, wherein patterned metal layer 422 includes
Multiple conductive trace 422a.In other words, the manufacture method of the chip-packaging structure of the present embodiment is to be initially formed a metal level 420
On the first carrier 410, then dielectric layer 430 is set on metal level 420, then transfer metal level 420 and dielectric layer 430 to
Second carrier 440, just carries out Patternized technique afterwards to form patterned metal layer 422.And previous embodiment is then opened for one
Begin to form a patterned metal layer on the first carrier, just continue afterwards and be configured dielectric layer, transfer pattern metal
Layer and dielectric layer are to steps such as the second carriers.
Hold above-mentioned, referring again to Fig. 4 E, multiple chips 450 are set on patterned metal layer 422, make chip 450 electrical
Connecting pattern metal level 422, afterwards, re-forms a packing colloid 460 on the second carrier 440, and packing colloid 460 covers
Cover core piece 450, patterned metal layer 422 and dielectric layer 430.In the present embodiment, chip 450 is in the way of such as flip chip bonding
It is arranged on patterned metal layer 422.Then, referring to Fig. 4 E and Fig. 4 F, remove the second carrier 440 in Fig. 4 E with
Exposed dielectric layer 430, afterwards, re-forms multiple openings 432 in the dielectric layer 430 exposing.Opening 432 exposes the figure of part
Case metal level 422.Then refill conduction material in opening 432, to form multiple connection pad 424a.Afterwards, as shown in Figure 4 G,
Carry out monomer metallization processes, this means, the packing colloid 460 between diced chip 450 and dielectric layer 430, to form multiple chip envelopes
Assembling structure 400.So, that is, the technique completing the chip-packaging structure 400 of the present embodiment.It should be noted that the present invention's
In one embodiment, can first be respectively provided with multiple soldered balls 470 on connection pad 424a, then carry out monomer metallization processes, with formed multiple such as
Sphere grid array encapsulation 400a shown in Fig. 4 H, enables chip-packaging structure to be connected with other electronic components by soldered ball 470.At this
In another embodiment of invention, multiple pad-type terminal 480 replacement soldered balls 470 can also be arranged on connection pad 424a, then carry out list
Body metallization processes, to form multiple pad lattice array package 400b as shown in fig. 41, enable chip-packaging structure to pass through pad-type terminal
480 are connected with other electronic components.
In sum, the present invention is prior to forming patterned metal layer and dielectric layer on the first carrier, then will be patterned into gold
Belong to layer and dielectric layer is transferred to and engages, covers the techniques such as packing colloid to carry out follow-up chip on the second carrier, afterwards, then
Remove the second carrier and continue and complete follow-up chip package process.Additionally, the present invention also can be prior to shape on the first carrier
Become a metal level and dielectric layer, then metal level and dielectric layer are transferred on the second carrier, then just metal level is carried out
Patterning, and carry out follow-up chip joint, cover the techniques such as packing colloid, afterwards, then remove the second carrier, to have continued
Become follow-up chip package process.So, the chip-packaging structure technique of the present invention can produce no support plate core layer structure
Chip-packaging structure, thus so that the thickness of chip-packaging structure is minimized.Additionally, the present invention first combines pattern with dielectric layer
Change metal level, re-form the packing colloid covering chip, patterned metal layer and dielectric layer afterwards, by this two benches sealing
Operation, makes the chip-packaging structure of the present invention have two kinds of glue-lines, therefore can be by from two kinds of different heat expansion coefficients
（Coefficients of thermal expansion, CTE）The situation to adjust chip-packaging structure warpage for the glue material.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, therefore the present invention
Protection domain when being defined depending on the defined person of appended claims.
Claims (17)
1. a kind of manufacture method of chip-packaging structure is it is characterised in that include：
There is provided the first carrier, this first carrier includes first surface and patterned metal layer, and this patterned metal layer sets
It is placed on this first surface；
Form dielectric layer on this first surface, to cover this patterned metal layer；
This patterned metal layer on this first carrier and this dielectric layer are transferred on the second carrier；
Multiple chips are set on this patterned metal layer, make the plurality of chip be electrically connected with this patterned metal layer；
Formed packing colloid on this second carrier, and this packing colloid cover the plurality of chip, this patterned metal layer with
And this dielectric layer；
Remove this second carrier；And
Cut this packing colloid and this dielectric layer of the plurality of chip chamber, to form multiple chip-packaging structures.
2. the manufacture method of chip-packaging structure as claimed in claim 1, should it is characterised in that providing this first carrier
First carrier includes this first surface and the step of this patterned metal layer further includes：
Form metal level on this first carrier；And
Patternized technique is carried out to this metal level, to form this patterned metal layer, this patterned metal layer includes multiple conductions
Trace.
3. chip-packaging structure as claimed in claim 2 manufacture method it is characterised in that by this first carrier should
When patterned metal layer and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
4. the manufacture method of chip-packaging structure as claimed in claim 3 is it is characterised in that further include：
After removing this second carrier, formed in multiple this dielectric layer being opened on exposure, the plurality of opening exposes part
This patterned metal layer；And
, in the plurality of opening, to form multiple connection pads, the plurality of connection pad is electric with the plurality of conductive trace respectively for filling conduction material
Property connect.
5. the manufacture method of chip-packaging structure as claimed in claim 4 is it is characterised in that further include：
It is respectively provided with multiple soldered balls on the plurality of connection pad.
6. the manufacture method of chip-packaging structure as claimed in claim 1, should it is characterised in that providing this first carrier
First carrier includes this first surface and the step of this patterned metal layer further includes：
Form metal level on this first carrier；And
Patternized technique is carried out to this metal level, to form this patterned metal layer, this patterned metal layer include articulamentum with
And multiple connection pad, the plurality of connection pad is located on this articulamentum.
7. the manufacture method of chip-packaging structure as claimed in claim 6 is it is characterised in that this dielectric layer is at least filled in this
Between multiple connection pads.
8. chip-packaging structure as claimed in claim 7 manufacture method it is characterised in that by this first carrier should
When patterned metal layer and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
9. the manufacture method of chip-packaging structure as claimed in claim 8 is it is characterised in that further include：
After this patterned metal layer on this first carrier and this dielectric layer are transferred on this second carrier, to this even
Connect layer and carry out Patternized technique, to form the conductive trace of the plurality of connection pad of multiple correspondences, the plurality of chip is arranged at this
On multiple conductive traces, the plurality of chip is made to be electrically connected with the plurality of conductive trace.
10. the manufacture method of chip-packaging structure as claimed in claim 9 is it is characterised in that further include：
After removing this second carrier, it is respectively provided with multiple soldered balls on the plurality of connection pad.
The manufacture method of 11. chip-packaging structures as claimed in claim 1, should it is characterised in that providing this first carrier
First carrier includes this first surface and the step of this patterned metal layer further includes：
There is provided metal level, this metal level includes articulamentum and multiple conductive trace, the plurality of conductive trace is located on this articulamentum；
This metal level is arranged on this first carrier, makes the plurality of conductive trace attach this first carrier；And
Patternized technique is carried out to this articulamentum of this metal level, to form the connection pad of the plurality of conductive trace of multiple correspondences, its
In this patterned metal layer include the plurality of conductive trace and the plurality of connection pad.
The manufacture method of 12. chip-packaging structures as claimed in claim 11 is it is characterised in that this dielectric layer is at least filled in
Between the plurality of conductive trace and the plurality of connection pad.
The manufacture method of 13. chip-packaging structures as claimed in claim 12 is it is characterised in that by this first carrier
When this patterned metal layer and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
The manufacture method of 14. chip-packaging structures as claimed in claim 13 is it is characterised in that further include：
After removing this second carrier, it is respectively provided with multiple soldered balls on the plurality of connection pad.
A kind of 15. manufacture methods of chip-packaging structure are it is characterised in that include：
There is provided the first carrier, this first carrier includes metal level, be arranged on this first carrier；
Form dielectric layer on this metal level；
This metal level on this first carrier and this dielectric layer are transferred on the second carrier, wherein this dielectric layer attaches and is somebody's turn to do
Second carrier；
Remove this first carrier to expose this metal level；
Patternized technique is carried out to this metal level, to form patterned metal layer, this patterned metal layer includes multiple conduction marks
Line；
Multiple chips are set on this patterned metal layer, make the plurality of chip be electrically connected with this patterned metal layer；
Formed packing colloid on this second carrier, and this packing colloid cover the plurality of chip, this patterned metal layer with
And this dielectric layer；
Remove this second carrier；And
Cut this packing colloid and this dielectric layer of the plurality of chip chamber, to form multiple chip-packaging structures.
The manufacture method of 16. chip-packaging structures as claimed in claim 15 is it is characterised in that further include：
After removing this second carrier, formed in multiple this dielectric layer being opened on exposure, the plurality of opening exposes part
This patterned metal layer；And
, in the plurality of opening, to form multiple connection pads, the plurality of connection pad is electric with the plurality of conductive trace respectively for filling conduction material
Property connect.
The manufacture method of 17. chip-packaging structures as claimed in claim 16 is it is characterised in that further include：
It is respectively provided with multiple soldered balls on the plurality of connection pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102117579A TWI550732B (en) | 2013-05-17 | 2013-05-17 | Manufacturing method of chip package structure |
| TW102117579 | 2013-05-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104167369A CN104167369A (en) | 2014-11-26 |
| CN104167369B true CN104167369B (en) | 2017-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310336975.7A Active CN104167369B (en) | 2013-05-17 | 2013-08-05 | Manufacturing method of chip packaging structure |
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| Country | Link |
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| CN (1) | CN104167369B (en) |
| TW (1) | TWI550732B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110224002A (en) | 2019-06-18 | 2019-09-10 | 京东方科技集团股份有限公司 | A kind of microLED panel preparation method and Preparation equipment |
| CN111883502B (en) * | 2020-08-03 | 2022-07-01 | 中国电子科技集团公司第三十八研究所 | Solder micro-bump array preparation method |
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|---|---|---|---|---|
| US5886409A (en) * | 1996-01-16 | 1999-03-23 | Hitachi, Ltd. | Electrode structure of wiring substrate of semiconductor device having expanded pitch |
| TW512500B (en) * | 2000-12-05 | 2002-12-01 | Jr-Gung Huang | Transfer bump encapsulation |
| TW200802764A (en) * | 2006-06-02 | 2008-01-01 | Chipmos Technologies Inc | Chip package with array pads and method for manufacturing the same |
| CN102244013A (en) * | 2010-05-14 | 2011-11-16 | 新科金朋有限公司 | Semiconductor device and manufacturing method thereof |
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2013
- 2013-05-17 TW TW102117579A patent/TWI550732B/en active
- 2013-08-05 CN CN201310336975.7A patent/CN104167369B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886409A (en) * | 1996-01-16 | 1999-03-23 | Hitachi, Ltd. | Electrode structure of wiring substrate of semiconductor device having expanded pitch |
| TW512500B (en) * | 2000-12-05 | 2002-12-01 | Jr-Gung Huang | Transfer bump encapsulation |
| TW200802764A (en) * | 2006-06-02 | 2008-01-01 | Chipmos Technologies Inc | Chip package with array pads and method for manufacturing the same |
| CN102244013A (en) * | 2010-05-14 | 2011-11-16 | 新科金朋有限公司 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201445649A (en) | 2014-12-01 |
| CN104167369A (en) | 2014-11-26 |
| TWI550732B (en) | 2016-09-21 |
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