CN102158403A - Efficient data stream transmission communication structure suitable for on chip network and operating method thereof - Google Patents
Efficient data stream transmission communication structure suitable for on chip network and operating method thereof Download PDFInfo
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Abstract
The invention discloses an efficient data stream transmission communication structure suitable for an on chip network and an operating method thereof. Processing procedures of data streams in the process of information transmission are taken as guidance. The structure comprises a package module of the data streams in a resource node module, a sending and storing module, a sending data stream state registration and sending control module, an arbitration judgment control module, an exchange switching array, a receiving data stream state registration and receiving control module, a receiving and storing module, an unpacking module in a destination resource node module and an external resource node routing module. According to the invention, mass data transmission between resource routing nodes of the on chip network can be efficiently and safely realized; the extended function is good; the structure division is clear; and the improvement are easily performed aiming at different design needs.
Description
Technical field
The present invention relates to a kind of efficient data flow transmission communication structure and method of work thereof that is applicable to network-on-chip, belong to communication technical field.
Background technology
Network-on-chip, the English NOC that is called for short, be meant on single-chip integrated a large amount of computational resource and the SOC (system on a chip) that connects the communication network of these resources, comprise and calculating and two subsystems of communicating by letter that Communications Processor Module and the network that interconnection line constituted therebetween are called as the chip-on communication network.
At present; though do not wane at the research of NOC heat of a specified duration, concentrate on theoretical research and laboratory exploratory stage mostly, still there is not the product of scale; one of the main reasons is exactly that difficulty has that high efficient and reliable, protocol security are complete, the communication structure of flexible standard, and these improve the crucial direction of systematic function just.
At the chip-on communication Network Design, emphasis of the present invention is as follows: module design, and nuclear interface standardizing improves the adaptability to the NOC topological structure; Adopt the alteration switch array structure to set up data transmission channel, transfer of data is parallel, high efficient and reliable; Adopt the tunnel technology of many buffer memorys, the data flow transmission performance is efficient; The clear pack arrangement of dividing data compactly is to formulate reasonable safe communication agreement.
Summary of the invention
At the deficiencies in the prior art, the present invention proposes a kind of efficient data flow transmission communication structure and method of work thereof that is applicable to network-on-chip, to realize efficient communication between resource node in the design that promotes multilayer NOC system, and make communication interface standardization, the present invention be particularly useful for the data flow transmission treatment system that bulk information was handled and transmitted to needs.Can produce through the integrated circuit technology design, be embodied as multiple nucleus system efficiently.
The technical scheme of transport communication structure of the present invention is as follows:
A kind of efficient data flow transmission communication structure that is applicable to network-on-chip, it is characterized in that, the transport communication structure comprises a plurality of data analysis layers, comprises a plurality of communication units, alteration switch array 108, arbitration control module 107 and interlayer communication unit in each data analysis layer;
Described communication unit comprises resource node module 101, send data flow state deposits and sends control module 105, sends memory module 106, receives memory module 109 and control module 110 is deposited and received to the receiving data stream state; Described resource node module 101 comprises packetization module 103, parse module 104 and data operation processing module 102; Wherein sending memory module 106 links to each other with alteration switch array 108 by data/address bus respectively with reception memory module 109; Data operation processing module 102 and packetization module 103, send data flow state and deposit and send control module 105 and send memory module 106 orders and link to each other; Data operation processing module 102 also with parse module 104, receive memory module 109 and receiving data stream state and deposit and receive control module 110 orders and link to each other;
In data analysis layer, described arbitration control module 107 links to each other with alteration switch array 108, each communication unit and interlayer communication unit respectively by control bus; Described alteration switch array 108 is the two-dimensional grid matrix form, each bar line in the two-dimensional grid is represented a circuit-switched data bus 401, represent that by i, j ground i is capable, the intersection point of j row, 402 controls of one switch arrays are all arranged at the grid intersection point ij403 place of i ≠ j, and whether it is communicated with, and closed this switch can be communicated with the transmission channel of ij resource node module; Described interlayer communication unit comprises that outer resource node routing module 111, interlayer receive memory module 112 and interlayer sends memory module 113; Described interlayer receives memory module 112 and links to each other with alteration switch array 108 by data/address bus respectively with interlayer transmission memory module 113;
Described transmission memory module 106 comprises buffer memory selection logic 302, sends buffer memory 303 and send and select module 304; Described reception memory module 109 comprises buffer memory selection logic 302, receives and select module 305 and receive buffer memory 306; Send memory module 106 and receive memory module 109 and constitute the storing virtual passage;
The outer resource node routing module 111 of all data analysis layers is connected with each other by data/address bus;
The communication unit of initiating communication is a source communication unit; The communication unit of received communication is the purpose communication unit; The data analysis layer at source communication unit place is the source data processing layer; The data analysis layer at purpose communication unit place is the destination data processing layer; Source communication unit and purpose communication unit are called with layer when same data analysis layer; Source communication unit and purpose communication unit are called different layer not when same data analysis layer.
A kind of method of work that is applicable to efficient data flow transmission communication structure in the network-on-a-chip is characterized in that method of work is as follows:
1) in source communication unit, resource node module 101 is added packet header bag tail with data to be sent by packetization module 103 and is constituted a packet;
2) in source communication unit, packet buffer memory in sending memory module 106 selects logic 302 to be loaded into the transmission buffer memory 303 of corresponding purpose source communication unit, send memory module 106 and extract contained packet state information in the packet header, and the arbitration control module 107 that is sent in the source data processing layer is carried out the transmission state judgment processing;
3) in the source data processing layer, arbitration control module 107 is carried out the transmission state judgment processing: whether at first judge source communication unit and purpose communication unit with layer, if with layer, carry out step a); If different layer carries out step b):
A): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the transmission memory module 106 of source communication unit and the reception memory module 109 of purpose communication unit, set up transmission channel;
B): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the interlayer that sends memory module 106 and interlayer communication unit and send memory module 113, through outer resource node routing module 111, the interlayer that sends memory module 113 and destination data processing layer between the control connectivity layer receives memory module 112, in the destination data processing layer, receive and keep the reception memory module 109 of storing up in module 112 and the purpose communication unit indirectly through arbitration control module 107 control connectivity layers, set up transmission channel;
Passage arbitration method for building up described in the step 3) is specially:
If i. there is not the data congestion race condition, arbitration control module 107 control alteration switch arrays 108 are communicated with corresponding data transmission channel, and the transmission memory module 106 of promptly setting up source communication unit is replied with the transmission channel of 109 of the reception memory modules of purpose communication unit and to arbitrating control module 107;
Ii. if any there being the data congestion race condition, then arbitrating control module 107 and utilize the dynamic priority lookup method to judge the priority of each data transmission channel; If network-on-a-chip allows to interrupt taking place, the low data channel of priority is made way for the high data channel transmission of priority under 107 controls of arbitration control module; The transmission memory module 106 of source communication unit is communicated with the reception memory module 109 of purpose communication unit;
The dynamic priority lookup method is:
1.. arbitration control module 107 includes the priority state registers group, when the network-on-chip electrifying startup, loads default value in the priority state registers group, and the priority state registers group identifies the default priority of each data transmission channel; When network-on-chip moved, the priority state registers group regularly circulated and adjusts once, and it is minimum that the priority of the highest data transmission channel of priority is become, and the priority of remainder data transmission channel improves one-level respectively;
2.. when data congestion was competed, arbitration control module 107 at first compared the priority height of the sign of the transmission priority in the packet packet header 204 in each data transmission channel, and the high person of priority is prior to the low person's transmission of priority; When the priority height is identical, arbitration control module 107 inquiry priority state registers group, the prioritised transmission order of affirmation data transmission channel;
4) send data flow state and deposit and send the transmission channel that control module 105 is set up according to step 3), the control data bag transfers to reception memory module 109 in the purpose communication unit by the transmission buffer memory 303 in the source communication unit through send selecting module 304, receiving reception in the memory module 109 selects module 305 that packet is loaded into reception buffer memory 306 corresponding to source communication unit, packet bag tail as finishing sign, is finished transmission;
5) control module 110 is deposited and received to the accepting state in the purpose communication unit, cancels used transmission channel, and the resource node module 101 in the notice purpose communication unit is extracted packet;
6) in the purpose communication unit, data operation processing module 102 is extracted the data of packets: select logic 302 to take out the data of packet from receive buffer memory 306 by the buffer memory that receives in the memory module 109, unpack and use data in the packet by parse module 104.
Packetization module in the resource node module is used for data preparation to be sent is become packet, and adds packet header bag mantissa certificate, and header data sign transmission beginning provides packet all kinds of state informations simultaneously, and the bag tail is used to indicate the end of transmission.The state information of the various needs of the beginning of packet header identification data packet and packet wherein, it is respectively 31~30 according to data bit: data type sign 201; 29~26: source and purpose resource node place layer sequence number sign 202; 25~22: the place layer is endogenous to identify 203 with purpose resource node sequence number; 21~18: notebook data bag transmission priority sign 204; 17: transmission interrupts allowing sign 205; 16~15: keep stand-by 206; 15~0: data stream packets length mark 207.The bag tail tag is known the end of packet.
Send memory module and be used for the various objectives resource node is ready for sending buffer memory, deposit and send to control under the control module in the transmission data flow state and finish the data transmission.
The arbitration control module is used to realize control that the data interchange channel is set up, and congested according to the competition of dynamic priority lookup method deal with data.
Receive memory module and be used for different resource nodes is prepared to receive buffer memory separately, deposit and receive under the control module control at the receiving data stream state and realize Data Receiving.
Parse module is used for unpacking after receiving packet, recovers the data of transmission and send further processing.
Expansion when outer resource node routing module is used for purpose resource node when data flow not at this layer is transmitted.
The present invention has following advantage:
The present invention is directed to the data flow transmission data, with each functional unit blockization, nuclear interface standardizing strengthens the adaptability to the NOC topological structure; Handling process orderliness to data flow is clear, adopts the alteration switch array structure to set up data transmission channel, and transfer of data is parallel, high efficient and reliable; Adopt the tunnel technology of many buffer memorys, be convenient to the processing congested to data greatly, the data flow transmission performance is efficient; The interlayer method for routing reduces the burden of resource node significantly; Clear succinct dividing data pack arrangement, the reasonable safety of the formulation of communication protocol, this communication structure is transmitting data stream fast and safely, has good flexibility and practicality.
Description of drawings
Fig. 1 is the structural representation of same data analysis layer of the present invention;
Fig. 2 is a packing of the present invention back packet middle wrapping head form schematic diagram;
Fig. 3 is that the storage extended channel of transmission memory module 106 of the present invention is formed schematic diagram;
Fig. 4 is an alteration switch array schematic diagram of the present invention;
Wherein, 101, resource node module; 102, data operation processing module; 103, packetization module; 104, parse module; 105, send data flow state and deposit and send control module; 106, send memory module; 107, arbitration control module; 108, alteration switch array; 109, receive memory module; 110, control module is deposited and received to the receiving data stream state; 111, outer resource node routing module; 112, interlayer receives memory module; 113, interlayer sends memory module;
201, data type sign; 202, source and purpose resource node place layer sequence number sign; 203, the place layer is endogenous identifies with purpose resource node sequence number; 204, notebook data bag transmission priority sign; 205, transmission interrupts allowing sign; 206, reservation is stand-by; 207, data stream packets length mark;
302, buffer memory is selected logic; 303, send buffer memory; 304, send the selection module; 305, receive the selection module; 306, receive buffer memory;
401, data/address bus; 402, grid intersection point; 403, switch arrays.
Embodiment
Be described in further detail of the present invention below by drawings and Examples, but be not limited thereto.
Embodiment 1,
As shown in Figure 1, a kind of efficient data flow transmission communication structure that is applicable to network-on-chip, it is characterized in that the transport communication structure comprises a plurality of data analysis layers, comprise a plurality of communication units, alteration switch array 108, arbitration control module 107 and interlayer communication unit in each data analysis layer;
Described communication unit comprises resource node module 101, send data flow state deposits and sends control module 105, sends memory module 106, receives memory module 109 and control module 110 is deposited and received to the receiving data stream state; Described resource node module 101 comprises packetization module 103, parse module 104 and data operation processing module 102; Wherein sending memory module 106 links to each other with alteration switch array 108 by data/address bus respectively with reception memory module 109; Data operation processing module 102 and packetization module 103, send data flow state and deposit and send control module 105 and send memory module 106 orders and link to each other; Data operation processing module 102 also with parse module 104, receive memory module 109 and receiving data stream state and deposit and receive control module 110 orders and link to each other;
In data analysis layer, described arbitration control module 107 links to each other with alteration switch array 108, each communication unit and interlayer communication unit respectively by control bus; Described alteration switch array 108 is the two-dimensional grid matrix form, each bar line in the two-dimensional grid is represented a circuit-switched data bus 401, represent that by i, j ground i is capable, the intersection point of j row, 402 controls of one switch arrays are all arranged at the grid intersection point ij403 place of i ≠ j, and whether it is communicated with, and closed this switch can be communicated with the transmission channel of ij resource node module; Described interlayer communication unit comprises that outer resource node routing module 111, interlayer receive memory module 112 and interlayer sends memory module 113; Described interlayer receives memory module 112 and links to each other with alteration switch array 108 by data/address bus respectively with interlayer transmission memory module 113;
Described transmission memory module 106 comprises buffer memory selection logic 302, sends buffer memory 303 and send and select module 304; Described reception memory module 109 comprises buffer memory selection logic 302, receives and select module 305 and receive buffer memory 306; Send memory module 106 and receive memory module 109 and constitute the storing virtual passage;
The outer resource node routing module 111 of all data analysis layers is connected with each other by data/address bus;
The communication unit of initiating communication is a source communication unit; The communication unit of received communication is the purpose communication unit; The data analysis layer at source communication unit place is the source data processing layer; The data analysis layer at purpose communication unit place is the destination data processing layer; Source communication unit and purpose communication unit are called with layer when same data analysis layer; Source communication unit and purpose communication unit are called different layer not when same data analysis layer.
Figure 2 shows that the data format in the packet, Senior Two position 201 signs distinguish general data and data packet header, wrap tail.Header data comprises: source and purpose resource node place layer sequence number identify 202 fields, are used for identifying the layer sequence number at the source and the purpose resource node place of multilayer NOC packet; Source and purpose resource node be sequence number sign 203 in its place layer, is used for the sequence number of identifying resource node at self place layer, together constitutes the ID of each resource node with layer sequence number sign; Notebook data bag transmission priority sign 204 is used for judging for arbitration modules provides to arbitrate when data congestion takes place, and determines order of priority, also is used for simultaneously controlling under the situation that allows transmission of data packets to interrupt taking place and interrupts; Whether transmission is interrupted allowing sign 205, allow in this transmission of data packets to be interrupted to make way for the higher packet prioritised transmission of priority level in order to identify; Data stream packets length mark 207 in order to the identification data packet length, satisfies the specific needs to processing data packets.
Fig. 3 is the storing virtual passage, the resource node module will send packet and send buffer memory 303 through selecting logic 302 to deliver to, send buffer memory 303 and prepare a transmission buffer memory separately at other each resource node modules in the layer and the outer resource node module of layer, data cached thereafter bag selects module 304 to send through sending.During reception, packet selects module 305 to send into reception buffer memory 306 through receiving, prepare one at other each resource nodes in the layer separately with the outer resource node of layer and receive buffer memory, the purpose resource node selects logic 302 that packet is delivered to the reception resource node through buffer memory.
Figure 4 shows that the alteration switch array, it is the two-dimensional grid matrix form, each bar line is represented a circuit-switched data bus 401, represent that by i, j ground i is capable, the intersection point of j row, all have switch arrays 402 (being designated switch arrays ij) to control it at the grid intersection point ij403 place of i ≠ j and whether be communicated with, closed this switch can be communicated with the transmission channel of ij resource node.
Embodiment 2,
A kind of method of work that is applicable to efficient data flow transmission communication structure in the network-on-a-chip is characterized in that method of work is as follows:
1) in source communication unit, resource node module 101 is added packet header bag tail with data to be sent by packetization module 103 and is constituted a packet;
2) in source communication unit, packet buffer memory in sending memory module 106 selects logic 302 to be loaded into the transmission buffer memory 303 of corresponding purpose source communication unit, send memory module 106 and extract contained packet state information in the packet header, and the arbitration control module 107 that is sent in the source data processing layer is carried out the transmission state judgment processing;
3) in the source data processing layer, arbitration control module 107 is carried out the transmission state judgment processing: whether at first judge source communication unit and purpose communication unit with layer, if with layer, carry out step a); If different layer carries out step b):
A): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the transmission memory module 106 of source communication unit and the reception memory module 109 of purpose communication unit, set up transmission channel;
B): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the interlayer that sends memory module 106 and interlayer communication unit and send memory module 113, through outer resource node routing module 111, the interlayer that sends memory module 113 and destination data processing layer between the control connectivity layer receives memory module 112, in the destination data processing layer, receive and keep the reception memory module 109 of storing up in module 112 and the purpose communication unit indirectly through arbitration control module 107 control connectivity layers, set up transmission channel;
Passage arbitration method for building up described in the step 3) is specially:
If i. there is not the data congestion race condition, arbitration control module 107 control alteration switch arrays 108 are communicated with corresponding data transmission channel, and the transmission memory module 106 of promptly setting up source communication unit is replied with the transmission channel of 109 of the reception memory modules of purpose communication unit and to arbitrating control module 107;
Ii. if any there being the data congestion race condition, then arbitrating control module 107 and utilize the dynamic priority lookup method to judge the priority of each data transmission channel; If network-on-a-chip allows to interrupt taking place, the low data channel of priority is made way for the high data channel transmission of priority under 107 controls of arbitration control module; The transmission memory module 106 of source communication unit is communicated with the reception memory module 109 of purpose communication unit;
The dynamic priority lookup method is:
1.. arbitration control module 107 includes the priority state registers group, when the network-on-chip electrifying startup, loads default value in the priority state registers group, and the priority state registers group identifies the default priority of each data transmission channel; When network-on-chip moved, the priority state registers group regularly circulated and adjusts once, and it is minimum that the priority of the highest data transmission channel of priority is become, and the priority of remainder data transmission channel improves one-level respectively;
2.. when data congestion was competed, arbitration control module 107 at first compared the priority height of the sign of the transmission priority in the packet packet header 204 in each data transmission channel, and the high person of priority is prior to the low person's transmission of priority; When the priority height is identical, arbitration control module 107 inquiry priority state registers group, the prioritised transmission order of affirmation data transmission channel;
4) send data flow state and deposit and send the transmission channel that control module 105 is set up according to step 3), the control data bag transfers to reception memory module 109 in the purpose communication unit by the transmission buffer memory 303 in the source communication unit through send selecting module 304, receiving reception in the memory module 109 selects module 305 that packet is loaded into reception buffer memory 306 corresponding to source communication unit, packet bag tail as finishing sign, is finished transmission;
5) control module 110 is deposited and received to the accepting state in the purpose communication unit, cancels used transmission channel, and the resource node module 101 in the notice purpose communication unit is extracted packet;
6) in the purpose communication unit, data operation processing module 102 is extracted the data of packets: select logic 302 to take out the data of packet from receive buffer memory 306 by the buffer memory that receives in the memory module 109, unpack and use data in the packet by parse module 104.
Claims (2)
1. efficient data flow transmission communication structure that is applicable to network-on-chip, it is characterized in that, the transport communication structure comprises a plurality of data analysis layers, comprises a plurality of communication units, alteration switch array 108, arbitration control module 107 and interlayer communication unit in each data analysis layer;
Described communication unit comprises resource node module 101, send data flow state deposits and sends control module 105, sends memory module 106, receives memory module 109 and control module 110 is deposited and received to the receiving data stream state; Described resource node module 101 comprises packetization module 103, parse module 104 and data operation processing module 102; Wherein sending memory module 106 links to each other with alteration switch array 108 by data/address bus respectively with reception memory module 109; Data operation processing module 102 and packetization module 103, send data flow state and deposit and send control module 105 and send memory module 106 orders and link to each other; Data operation processing module 102 also with parse module 104, receive memory module 109 and receiving data stream state and deposit and receive control module 110 orders and link to each other;
In data analysis layer, described arbitration control module 107 links to each other with alteration switch array 108, each communication unit and interlayer communication unit respectively by control bus; Described alteration switch array 108 is the two-dimensional grid matrix form, each bar line in the two-dimensional grid is represented a circuit-switched data bus 401, represent that by i, j ground i is capable, the intersection point of j row, 402 controls of one switch arrays are all arranged at the grid intersection point ij403 place of i ≠ j, and whether it is communicated with, and closed this switch can be communicated with the transmission channel of ij resource node module; Described interlayer communication unit comprises that outer resource node routing module 111, interlayer receive memory module 112 and interlayer sends memory module 113; Described interlayer receives memory module 112 and links to each other with alteration switch array 108 by data/address bus respectively with interlayer transmission memory module 113;
Described transmission memory module 106 comprises buffer memory selection logic 302, sends buffer memory 303 and send and select module 304; Described reception memory module 109 comprises buffer memory selection logic 302, receives and select module 305 and receive buffer memory 306; Send memory module 106 and receive memory module 109 and constitute the storing virtual passage;
The outer resource node routing module 111 of all data analysis layers is connected with each other by data/address bus;
The communication unit of initiating communication is a source communication unit; The communication unit of received communication is the purpose communication unit; The data analysis layer at source communication unit place is the source data processing layer; The data analysis layer at purpose communication unit place is the destination data processing layer; Source communication unit and purpose communication unit are called with layer when same data analysis layer; Source communication unit and purpose communication unit are called different layer not when same data analysis layer.
2. the method for work that is applicable to efficient data flow transmission communication structure in the network-on-a-chip as claimed in claim 1 is characterized in that method of work is as follows:
1) in source communication unit, resource node module 101 is added packet header bag tail with data to be sent by packetization module 103 and is constituted a packet;
2) in source communication unit, packet buffer memory in sending memory module 106 selects logic 302 to be loaded into the transmission buffer memory 303 of corresponding purpose source communication unit, send memory module 106 and extract contained packet state information in the packet header, and the arbitration control module 107 that is sent in the source data processing layer is carried out the transmission state judgment processing;
3) in the source data processing layer, arbitration control module 107 is carried out the transmission state judgment processing: whether at first judge source communication unit and purpose communication unit with layer, if with layer, carry out step a); If different layer carries out step b):
A): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the transmission memory module 106 of source communication unit and the reception memory module 109 of purpose communication unit, set up transmission channel;
B): in the source data processing layer, arbitration control module 107 is according to passage arbitration method for building up control alteration switch array 108 closed respective switch, be communicated with the interlayer that sends memory module 106 and interlayer communication unit and send memory module 113, through outer resource node routing module 111, the interlayer that sends memory module 113 and destination data processing layer between the control connectivity layer receives memory module 112, in the destination data processing layer, receive and keep the reception memory module 109 of storing up in module 112 and the purpose communication unit indirectly through arbitration control module 107 control connectivity layers, set up transmission channel;
Passage arbitration method for building up described in the step 3) is specially:
If i. there is not the data congestion race condition, arbitration control module 107 control alteration switch arrays 108 are communicated with corresponding data transmission channel, and the transmission memory module 106 of promptly setting up source communication unit is replied with the transmission channel of 109 of the reception memory modules of purpose communication unit and to arbitrating control module 107;
Ii. if any there being the data congestion race condition, then arbitrating control module 107 and utilize the dynamic priority lookup method to judge the priority of each data transmission channel; If network-on-a-chip allows to interrupt taking place, the low data channel of priority is made way for the high data channel transmission of priority under 107 controls of arbitration control module; The transmission memory module 106 of source communication unit is communicated with the reception memory module 109 of purpose communication unit;
Described dynamic priority lookup method is:
1.. arbitration control module 107 includes the priority state registers group, when the network-on-chip electrifying startup, loads default value in the priority state registers group, and the priority state registers group identifies the default priority of each data transmission channel; When network-on-chip moved, the priority state registers group regularly circulated and adjusts once, and it is minimum that the priority of the highest data transmission channel of priority is become, and the priority of remainder data transmission channel improves one-level respectively;
2.. when data congestion was competed, arbitration control module 107 at first compared the priority height of the sign of the transmission priority in the packet packet header 204 in each data transmission channel, and the high person of priority is prior to the low person's transmission of priority; When the priority height is identical, arbitration control module 107 inquiry priority state registers group, the prioritised transmission order of affirmation data transmission channel;
4) send data flow state and deposit and send the transmission channel that control module 105 is set up according to step 3), the control data bag transfers to reception memory module 109 in the purpose communication unit by the transmission buffer memory 303 in the source communication unit through send selecting module 304, receiving reception in the memory module 109 selects module 305 that packet is loaded into reception buffer memory 306 corresponding to source communication unit, packet bag tail as finishing sign, is finished transmission;
5) control module 110 is deposited and received to the accepting state in the purpose communication unit, cancels used transmission channel, and the resource node module 101 in the notice purpose communication unit is extracted packet;
6) in the purpose communication unit, data operation processing module 102 is extracted the data of packets: select logic 302 to take out the data of packet from receive buffer memory 306 by the buffer memory that receives in the memory module 109, unpack and use data in the packet by parse module 104.
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1701274B1 (en) * | 2005-03-08 | 2008-02-13 | Commissariat A L'energie Atomique | Communication node architecture in a globaly asynchronous network on-chip system |
CN101131858A (en) * | 2007-09-28 | 2008-02-27 | 山东大学 | Three-dimensional multi-port memory and control method thereof |
CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
US20090125574A1 (en) * | 2007-11-12 | 2009-05-14 | Mejdrich Eric O | Software Pipelining On a Network On Chip |
CN101488922A (en) * | 2009-01-08 | 2009-07-22 | 浙江大学 | Network-on-chip router having adaptive routing capability and implementing method thereof |
CN101917333A (en) * | 2010-07-06 | 2010-12-15 | 西安电子科技大学 | Region-based photoelectric double-layer network-on-a-chip and routing method |
-
2011
- 2011-03-24 CN CN201110071734.5A patent/CN102158403B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1701274B1 (en) * | 2005-03-08 | 2008-02-13 | Commissariat A L'energie Atomique | Communication node architecture in a globaly asynchronous network on-chip system |
CN101131858A (en) * | 2007-09-28 | 2008-02-27 | 山东大学 | Three-dimensional multi-port memory and control method thereof |
US20090125574A1 (en) * | 2007-11-12 | 2009-05-14 | Mejdrich Eric O | Software Pipelining On a Network On Chip |
CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
CN101488922A (en) * | 2009-01-08 | 2009-07-22 | 浙江大学 | Network-on-chip router having adaptive routing capability and implementing method thereof |
CN101917333A (en) * | 2010-07-06 | 2010-12-15 | 西安电子科技大学 | Region-based photoelectric double-layer network-on-a-chip and routing method |
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WO2016000224A1 (en) * | 2014-07-02 | 2016-01-07 | 华为技术有限公司 | Computer system |
CN105393504B (en) * | 2014-07-02 | 2018-09-28 | 华为技术有限公司 | Computer system |
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CN114363246A (en) * | 2020-09-30 | 2022-04-15 | 北京灵汐科技有限公司 | Many-core network-on-chip data transmission method, device, equipment and medium |
CN112491620A (en) * | 2020-11-29 | 2021-03-12 | 中国航空工业集团公司洛阳电光设备研究所 | Multi-channel data transmission controller based on SRIO and adjusting method |
CN112437021A (en) * | 2020-11-30 | 2021-03-02 | 清华大学 | Routing control method, device, routing equipment and storage medium |
CN112491715A (en) * | 2020-11-30 | 2021-03-12 | 清华大学 | Routing device and routing equipment of network on chip |
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