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CN103595627A - NoC router based on multicast dimension order routing algorithm and routing algorithm thereof - Google Patents

NoC router based on multicast dimension order routing algorithm and routing algorithm thereof Download PDF

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Publication number
CN103595627A
CN103595627A CN201310628342.3A CN201310628342A CN103595627A CN 103595627 A CN103595627 A CN 103595627A CN 201310628342 A CN201310628342 A CN 201310628342A CN 103595627 A CN103595627 A CN 103595627A
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microplate
data
route
moderator
packet
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王伟
李润丰
陈�田
刘军
方芳
吴玺
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Hefei University of Technology
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Hefei University of Technology
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Abstract

The invention discloses a NoC router based on a multicast dimension order routing algorithm and the routing algorithm thereof. The router comprises an input control and routing arbiter, a cross option switch and an output buffer controller. The input control and routing arbiter is connected with the cross option switch, and the cross option switch is connected with the output buffer controller. A data package is analyzed through the arbiter after entering the input control and routing arbiter, one or more destination addresses contained in the data package are extracted, the transmitting directions are respectively judged, and the data package is transmitted to the cross option switch; the cross option switch copies the data package and transmits the data package to one or more corresponding output ports, and the output buffer controller is charge of sending data towards a next routing node. The NoC router and the routing algorithm of the NoC router have the advantages that the problem that router support is lacked in the process of performing multicast testing on a NoC chip containing multiple cores can be solved, the NoC router is simple in structure, the adaptability is high, and a multicast function can be achieved.

Description

NoC router and routing algorithm thereof based on multicast dimension order routing algorithm
Technical field
The present invention relates to a kind of NoC router and routing algorithm thereof based on multicast dimension order routing algorithm.
Background technology
Along with ic manufacturing technology flatly improves constantly and NoC(Network on Chip) development of designing technique and 3D integrated circuit technique, chip, to integrated numerous IP kernels that provided by third party, forms the future development of the large-scale circuit with many cores.How the numerous IP kernels in these chips being tested fast and effectively, is individual very stubborn problem, comprises and how to process the problem that the testing time is long and testing power consumption is excessive, rationally use the method for concurrent testing can effectively address these problems.
The network communications technology is used in and in NoC chip testing, transmits the Main Means that data are current chip tests.These communication technologys mainly comprise two kinds of unicast communication and multi-casting communications:
1, unicast communication: be a kind of network service that a kind of single source sends to single object recipient.Communications most in network are all transmitted with clean culture form.
2, multi-casting communication: claim again cast communication, be to transmit a kind of network service of data to one group of selected destination simultaneously.It realizes a point-to-point configuration and connects between sender and each recipient.If a sender transmits identical data to a plurality of recipients simultaneously, also only need copy a identical data packet.It has improved data-transmission efficiency.Reduce backbone network and occurred congested possibility.
Unicast communication is the master data load mode of NoC, and multi-casting communication is the demand that multi-core parallel concurrent is processed as a kind of communication technology of extensive utilization.Multi-casting communication simultaneously to a kind of network service of one group of selected destination transmission data, proposes the concept of ip multicast by Steve Deering in 1988 first in its thesis for the doctorate.But by multicasting technology for the research of chip testing seldom.
Multicast test uses multi-casting communication technology on NoC chip, and identical IP kernel is sent to test data simultaneously, so only needs to send a test data, and all isomorphism IP kernels can receive required test data.It is intended to realize on sheet the object of reusing to reach quick test of test data (comprising test and excitation and reference response) between isomorphism core by multicasting technology.As long as control like this each stage well to which core transmission data, just can well reduce the testing time, and reduce and even avoid the appearance of hot spot, accomplish that test is rapidly, accurately.
Limited due to network-on-chip area, power consumption, on sheet, the 26S Proteasome Structure and Function of route is often fairly simple, generally input port, route moderator, cross selection switch, output port etc., partly consists of.Most upper router adopts the simplest X-Y routing policy, to single direction, transmits data, and what have also has a Virtual Channel, can effectively avoid blocking up and the generation of deadlock.
Multicast router supports the router of multi-casting communication technology, it in general structure with ordinary tablet on router similar, different is that it can be analyzed a packet, find out one or more destination addresses that packet will arrive, according to circumstances to one or more directions, transmit identical packet simultaneously.The many core chips that transmit a large amount of same test data for needs, can effectively reduce the testing time, reduce testing power consumption.
At home and abroad in the research for 3D chip testing, for the research of multi-casting communication or many, but the research that the multicast router that will use for multicast test designs is not a lot.These multi-casting communication researchs are also applied to field tests to multicasting technology provides technical support.These research mainly concentrate on following some:
1, by using multicast measuring technology, the concentrated isomorphism core set that distributes is subdivided into a plurality of subsets that the testing time staggers and eliminates " hot spot ", and do not cause that by building the multiclass isomorphism core multicast test path parallel scheme of " hot spot " reduces the testing time, to reach, test walks abreast and the balance of the about interfascicular of heat.But do not study the concrete router topology for multicast test.
2, by a kind of connection-oriented path multicast mechanism, come to test for NoC.The message protocol that the method proposes is simple, practical, but has just studied concrete routing algorithm, and the design details of router is not described.
3, in NoC router, use the structure of the tree-shaped multicast of virtual circuit, by a kind of special unicast message (virtual circuit tree is set up message), set up virtual circuit table, router forwards the multicast message in succession passing through according to this virtual circuit table, but hardware spending is large.
4, in NoC router, use multicast parallel pipelining process line technology, well realized the Multicast function of multicast router, but can not solve Deadlock, the expense of router is relatively large.
Summary of the invention
The present invention is the weak point existing in above-mentioned prior art for avoiding, provide a kind of NoC router and routing algorithm thereof based on multicast dimension order routing algorithm, the problem of carrying out lacking in multicast test process router support with the NoC chip solving containing many cores.
The present invention is technical solution problem, and a kind of NoC router based on multicast dimension order routing algorithm is provided.
NoC router based on multicast dimension order routing algorithm, its design feature is, comprise input control and route moderator, cross selection switch and and output buffering and controller; Described input control and route moderator are connected with described cross selection switch, and described cross selection switch is connected with described output buffering and controller; Packet is resolved this packet by moderator after entering input control and route moderator, extracts the one or more destination addresses that comprise in this packet, judgement packet direction of transfer, and by Packet Generation to cross selection switch; Cross selection switch is accepted packet and the direction of transfer signal that described input control and route moderator are sent, and packet is sent to correct output port, and output buffering and controller are responsible for sending data to next routing node.
NoC router based on multicast dimension order routing algorithm of the present invention also has following technical characterstic.
Described packet adopts data microplate form, is divided into a microplate, middle microplate and tail microplate; Microplate is mainly used in pointing out the arrival of new data, and record the first two destination address information that data will be sent to; Middle microplate is mainly used in depositing the concrete data message of transmission; Tail microplate is used for being mainly used in reminder-data bag and transmits complete.
In described microplate, if can not deposit not complete destination address information because destination address information too much makes a microplate, use the follow-up middle microplate of a microplate to deposit the destination address information that a microplate has not yet been deposited.
The present invention also provides a kind of routing algorithm of the NoC router based on multicast dimension order routing algorithm.
A routing algorithm for the NoC router of multicast dimension order routing algorithm, its data transmission procedure is as follows:
Step 1: the data microplate of packet arrives input control and the route moderator of NoC router, and whether the data microplate that input control and the judgement of route moderator arrive is a microplate; If a microplate compares the data in this microplate with local routing node address data, the sending direction of judgement packet, by Packet Generation to cross selection switch;
Step 2: packet is transferred into cross selection switch; Cross selection switch receives the packet of input control and the transmission of route moderator; According to the sending direction of packet, cross selection switch is sent to by packet output buffering and the controller that packet will be carried;
Step 3: data have been sent to some output bufferings and controller module, now Req_que=1, writes buffer memory (Buffer_write=1) data, sends answer signal, and send request to downstream node data output signal to cross bar switch.Send answer signal Ack_que=1 now to last routing node, represent that data successfully forward.
In described step 1, the method for the sending direction of judgement packet is as follows:
Relatively the 3rd to the 6th of a microplate with local routing node address first 4, if the former is large, represent that destination node is on the right side of present node (the namely east E in Fig. 1), and the Select1 pin of putting input control and route moderator is " 001 "; If the latter is large, represent that destination node is in the left side of present node (the namely west W in Fig. 1), the Select1 pin of putting input control and route moderator is " 010 ";
The the 3rd of microplate the to the 6th with local routing node address first 4 when same large right overhead, relatively the 7th to the 10th of a microplate with local routing node address latter 4; If the former is large, represent that destination node is at the downside of present node, namely south (the namely south S in Fig. 1), the Select1 pin of putting input control and route moderator is " 011 "; If the latter is large, represent that destination node is at the upside (the namely north N in Fig. 1) of present node, the Select1 pin of putting input control and route moderator is " 100 ";
If the 7th to the 10th of a microplate with local routing node address rear 4 equally large, represent that present node is destination node (the namely local node L in Fig. 1), the Select1 pin of putting input control and route moderator is " 000 ".
In described step 2, the process that packet is transferred into cross selection switch is: when request signal that the port of one of them input control and route moderator is sent, if there is virtual circuit inhibit signal, first whether the direction of judgement transmission virtual circuit inhibit signal is consistent with the direction of request signal, be that same port sends, if not, represent that this route is taken by other ports, can not transmit asked signal; Whether the port direction that then detects this input control and route moderator has virtual circuit inhibit signal, if do not had, the Route Selection signal storage of just input control and route moderator being sent is in local storage, the data message sending is kept in local cache, and sends answer signal to input control and the route moderator of sending data.
Compared with the prior art, beneficial effect of the present invention is embodied in:
The present invention proposes a kind of NoC router and routing algorithm thereof based on multicast dimension order routing algorithm, NoC router is comprised of input control and route moderator, cross selection switch, output buffering and the large hardware components of controller three.Use special multi-case data microplate form, use specific multicast dimension order routing algorithm, adopt worm channel switching technology, by setting up the mode of virtual circuit, carry out the transmission of data.The multi-case data microplate adopting is divided into three kinds of a microplate, middle microplate and tail microplates; The routing algorithm adopting is a kind of routing algorithm of processing a plurality of destination address information developing based on X-Y routing algorithm.Of the present invention have Multicast function NoC router have simple in structure, complete function, strong adaptability, can realize the advantages such as Multicast function.
NoC router of the present invention and routing algorithm thereof, have problem that the NoC chip that can solve containing many cores carries out lacking in multicast test process router support, simple in structure, strong adaptability, can realize the advantages such as Multicast function.
Accompanying drawing explanation
Fig. 1 is the overall construction drawing of NoC router of the present invention.
Fig. 2 is input control and the route moderator pin schematic diagram of NoC router of the present invention.
Fig. 3 is the cross selection switch pin schematic diagram of NoC router of the present invention.
Fig. 4 is output buffering and the controller pin schematic diagram of NoC router of the present invention.
Fig. 5 is the special data microplate form schematic diagram of the routing algorithm of NoC router of the present invention.
Fig. 6 is the flow chart of the multicast dimension order routing algorithm of NoC router of the present invention.
Below, by embodiment, the invention will be further described.
Embodiment
Participate in Fig. 1~Fig. 6, the NoC router based on multicast dimension order routing algorithm, comprise input control and route moderator, cross selection switch and and output buffering and controller; Described input control and route moderator are connected with described cross selection switch, and described cross selection switch is connected with described output buffering and controller; Packet is resolved this packet by moderator after entering input control and route moderator, extracts the one or more destination addresses that comprise in this packet, judgement packet direction of transfer, and by Packet Generation to cross selection switch; Cross selection switch is accepted packet and the direction of transfer signal that described input control and route moderator are sent, and packet is sent to correct output port, and output buffering and controller are responsible for sending data to next routing node.
Described packet adopts data microplate form, is divided into a microplate, middle microplate and tail microplate; Microplate is mainly used in pointing out the arrival of new data, and record the first two destination address information that data will be sent to; Middle microplate is mainly used in depositing the concrete data message of transmission; Tail microplate is used for being mainly used in reminder-data bag and transmits complete.
In described microplate, if can not deposit not complete destination address information because destination address information too much makes a microplate, use the follow-up middle microplate of a microplate to deposit the destination address information that a microplate has not yet been deposited.
A routing algorithm for the NoC router of multicast dimension order routing algorithm, its data transmission procedure is as follows:
Step 1: the data microplate of packet arrives input control and the route moderator of NoC router, and whether the data microplate that input control and the judgement of route moderator arrive is a microplate; If a microplate is set to "True" by Route maintenance sign, and judge whether this microplate has comprised whole address informations, if not, wait for that subsequent packet contains the arrival of the middle microplate of address information; The data microplates that comprise address information when all are compared the address information in these microplates after arriving with local routing node address information, according to X-Y routing rule, judge the sending direction of packet, by Packet Generation to cross selection switch;
Step 2: data microplate is transferred into cross selection switch; Cross selection switch receives the packet of input control and the transmission of route moderator; If the data transmission direction of judgement is single direction in step 1, data microplate is sent to output buffering and the controller that data microplate will be carried; If the data transmission direction of judgement is multiple directions in step 1, according to different direction of transfer duplicate packet, reject with the different destination address of this direction of transfer, the packet of repacking is sent to corresponding output buffering and controller;
Step 3: data have been sent to some or certain several output bufferings and controller module, Req_que=1 now, data are write to buffer memory (Buffer_write=1), to cross bar switch, send answer signal, and send request to downstream node data output signal.Send answer signal Ack_que=1 now to last routing node, represent that data successfully forward.
In described step 1, the method for the sending direction of judgement packet is as follows:
The the 3rd to the 6th of compare address microplate with local routing node address first 4, if the former is large, represent that destination node is on the right side of present node (the namely east E in Fig. 1), and the Select1 pin of putting input control and route moderator is " 001 "; If the latter is large, represent that destination node is in the left side of present node (the namely west W in Fig. 1), the Select1 pin of putting input control and route moderator is " 010 ";
When the 3rd to the 6th of address microplate with local routing node address front 4 same when large, the 7th to the 10th of compare address microplate with local routing node address latter 4; If the former is large, represent that destination node is at the downside of present node, namely south (the namely south S in Fig. 1), the Select1 pin of putting input control and route moderator is " 011 "; If the latter is large, represent that destination node is at the upside (the namely north N in Fig. 1) of present node, the Select1 pin of putting input control and route moderator is " 100 ";
If the 7th to the 10th of address microplate with local routing node address rear 4 equally large, represent that present node is destination node (the namely local node L in Fig. 1), the Select1 pin of putting input control and route moderator is " 000 ".(whether latter 8 that check a microplate be complete 1, complete 1 if, represents that these data only send to a destination node, and the Select2 pin of putting input control and route moderator is " 111 ".Otherwise according to above-mentioned rule, determine the value of Select2.Check the value of Select1 and Select2, if both are equal, represent to send data to same direction, for fear of repeating to send data, put Select2 for " 111 ", invalid.)
In described step 2, the process that packet is transferred into cross selection switch is: when request signal that the port of one of them input control and route moderator is sent, if there is virtual circuit inhibit signal, first whether the direction of judgement transmission virtual circuit inhibit signal is consistent with the direction of request signal, be that same port sends, if not, represent that this route is taken by other ports, can not transmit asked signal; Whether the port direction that then detects this input control and route moderator has virtual circuit inhibit signal, if do not had, the Route Selection signal storage of just input control and route moderator being sent is in local storage, the data message sending is kept in local cache, and sends answer signal to input control and the route moderator of sending data.
Then analyze a current microplate and whether will be divided into multiple directions transmission at this routing node, if, their destination address is separately placed on to the 3rd to the 10th an of microplate, rear 8 sets, according to routing information, jump to different output ports, and send data to output buffer, then judging whether also needs data to send to other ports, if needed, continue to send.
NoC router based on multicast dimension order routing algorithm of the present invention, can to a plurality of different destination addresses, send message by a source address simultaneously, comprise input control and route moderator, cross selection switch and and output buffering and controller three parts hardware components, use can comprise the special data microplate form of a plurality of destination addresses, use multicast dimension order routing algorithm to carry out the forwarding of packet, adopt worm channel switching technology, by setting up the mode of virtual circuit, carry out the transmission of data.Described specific multicast dimension order routing algorithm is on the basis of common dimension order routing algorithm, increases multiaddress arbitration functions and past a plurality of output ports sending functions simultaneously.
As shown in Figure 5, described special data microplate form, is divided into three kinds of a microplate, middle microplate and tail microplates.Microplate is mainly used in pointing out the arrival of new data, and record the first two destination address information that data will be sent to; Middle microplate is mainly used in depositing the concrete data message of transmission, if destination address information is too much, a microplate cannot not deposited completely, can use the follow-up middle microplate of a microplate to deposit the destination address information that a microplate has not yet been deposited yet; Tail microplate is used for being mainly used in reminder-data bag and transmits complete.
Described multicast dimension order routing algorithm is a kind of Multicast Routing Algorithm based on X-Y dimension order route.First, router receives after the next microplate of transmission, analyzes a microplate, parses destination address information wherein, and judges whether follow-up middle microplate comprises remaining destination address information.Then, analyze these address informations, the direction of transfer of judgement packet.For several destination addresses that extract, according to specific forwarding strategy, the direction that judgement packet will send.Follow-up microplate is all sent to next routed port successively according to the direction of transfer of previous microplate, until the transmission of tail microplate is complete.
The specific forwarding rule of described multicast dimension order routing algorithm is to change according to the preferential routing algorithm of X.For the some destination addresses that extract, analyze the orientation of these destination addresses with respect to present node, if need the direction of forwarding data bag identical, press on ordinary tablet route such, data microplate is forwarded to correct direction, namely to a direction, transmits; If different, need to split data microplate address information, wherein unidirectional destination address and follow-up data are packaged into a packet, are so packaged into after several packets, route on ordinary tablet, exports these several packets respectively from the port of several different directions again.
As Fig. 1, described input control and route moderator are divided into east (East), west (West), south (South), north (North), local (Local) five, and what be used for respectively connecting four corners of the world four direction closes on router and local IP kernel; Described output buffering and controller are also divided into for east (East), west (West), south (South), north (North), local (Local) five; Described input control and route moderator are connected with cross selection switch respectively with output buffering and controller.
Described input control and route moderator comprise two input pins and the output pin being connected with upstream node, five output pins and the input pin that are connected with cross selection switch, and pin (ads) is injected in the clock signal pin (clk) being connected with the external world, reset signal pin (rst) and address; The described pin being connected with upstream node comprises packet input pin (Data_in), request signal input pin (Req_in), answer signal output pin (Ack_out); The described pin being connected with cross selection switch comprises data output pin (Data_sel), request output pin (Req_sel), reply input pin (Ack_sel), Route Selection signal pins 1(Select1), Route Selection signal pins 2(Select2), Route maintenance signal (Keep_sel);
Described cross selection switch comprises each five input pins and the output pin being connected with five input controls and route moderator, each two output pins and the input pin that are connected with five output bufferings and controller, and the clock signal pin (clk) being connected with the external world and reset signal pin (rst); The described pin being connected with one of them input control and route moderator comprises data input pin (Data_sel), request input pin (Req_sel), reply output pin (Ack_sel), Route Selection signal pins 1(Select1), Route Selection signal pins 2(Select2), Route maintenance signal (Keep_sel); The described pin being connected with output buffering and controller comprises data output pin (Data_que), and request output pin (Req_que), replys input pin (Ack_que);
Described output buffering and controller comprise two input pins that are connected with cross selection switch and an output pin, two output pins and the input pin that are connected with downstream node, and the clock signal pin (clk) being connected with the external world and reset signal pin (rst); The described pin being connected with cross selection switch comprises data input pin (Data_que), and request input pin (Req_que), replys output pin (Ack_que); The described pin being connected with downstream node comprises data output pin (Data_out), and request output pin (Req_out), replys input pin (Ack_in);
As Fig. 6, described multicast dimension order routing algorithm is to be developed by common X-Y dimension order routing algorithm, when router receives new data microplate and arrives current routing node, first judge whether this microplate is a microplate, if a microplate, analyze a microplate, parse destination address information wherein, and judge whether follow-up middle microplate comprises remaining destination address information, if also had, preserve the address information receiving, and wait for the arrival of follow-up microplate.If follow-up, there is no address information, just analyzed these address informations, the direction of transfer of judgement packet.For several destination addresses that extract, judge that each destination address is with respect to the directional information of present node, the output port that specified data bag will send, and again the destination address information of equidirectional is combined into a new microplate, send to respectively corresponding destination interface, and keep corresponding link.When next microplate arrives, the link of searching for each link keeps sign, copies this microplate, sends to respectively each link and keeps the genuine direction of flag bit.Follow-up microplate is all sent to next routed port successively according to the direction of transfer of previous microplate, until the transmission of tail microplate is complete, puts all links and keeps being masked as vacation.
Packet is resolved it by moderator after entering input control and route moderator, extracts the one or more destination addresses that wherein comprise, judgement direction of transfer; Then cross selection switch is accepted packet and the direction of transfer signal that moderator is sent, and packet is sent to correct output port, and output buffering and controller are responsible for sending data to next routing node.The present invention relates to the data input of five directions, and the output of the data of five directions, be respectively East, West, South, North, this locality.Shown in Fig. 1, be general structure frame of the present invention and main pinouts.The input that can see data in this figure has five directions, and the cross selection switch by 5*5 is sent to different directions by the data of input.
If Fig. 2 is input control and route moderator: this part mainly contains 12 signal line, and wherein " clk " is clock signal, and " rst " is reset signal." ads " is the address information that sends the current router injecting before data, and it is the holding wire of 8, and the X by current route in network, Y coordinate represent address, the front four bit representation directions X coordinates of " ads ", rear four bit representation Y-direction coordinates.After injecting " ads " signal, current routing address will can not change again." Data_in " is the data message that last route is sent, and " Req_in " is that the request that last route is sent sends data-signal, and " Ack_out " is the answer signal that current router sent to last router, and expression data are received." Data_sel " is the data message that input control device sends to cross selection switch, and " Req_sel " is the request signal that input control device sends to cross selection switch, and " Ack_sel " is the answer signal that cross bar switch is replied." Select1 " and " Select2 " are the both direction selection signals that route moderator is issued cross bar switch, totally 3 of this signals, wherein " 000 " representative is sent to this locality (Local) IP kernel, " 001 " representative is sent to (East) in the east, " 010 " representative is sent to west (West), " 011 " representative is sent to south (South), and " 100 " representative is sent to the north (North)." Keep_sel " is address inhibit signal, and after microplate arrival right overhead, just putting " Keep_sel " is 1, until tail microplate arrives, what play is the function that keeps virtual circuit.
If Fig. 3 is cross selection switch: data based its routing iinformation that this part is mainly responsible for input control and route moderator to transport is forwarded to different ports.Owing to having five input ports and five output ports, introduce one of them here." clk " is clock signal, and " rst " is reset signal." Data_sel " is the data-signal that input control and route moderator are sent; " Req_sel " is request signal; " Select1 " and " Select2 " are Route Selection signal, and this module is carried out the selection of output port according to these two signals; " Keep_sel " is virtual circuit inhibit signal, if this signal is 1, do not detect new Route Selection signal, or according to path transmissioning data before; " Ack_sel " is answer signal; " Data_que " sends to the data message of output buffer for cross bar switch; " Req_que " is request signal; " Ack_que " is answer signal.Other four input ports and four output ports therewith holding wire and the pin in figure are unanimous on the whole.The groundwork of this module is that data are sent to correct output port, and it is that the Route Selection signal (Select1 and Select2) of sending by reception route moderator is controlled data outbound course.
If Fig. 4 is output buffering and controller: this module is for controlling data output, data cached important module.This modular structure is fairly simple, " clk " is clock signal, " rst " is reset signal, the data message that " Data_que " sends for cross bar switch, the request signal that " Req_que " sends for cross bar switch, " Ack_que " is answer signal, " Data_out " is the data message that o controller sends to next route, " Req_out " is the request signal sending to next routing node, and " Ack_in " is the answer signal that next route is sent out node.
NoC router based on multicast dimension order routing algorithm of the present invention, has Multicast function, can to one or more destination nodes, send identical message simultaneously, for the NoC chip to containing many cores carries out multicast test, provides hardware guarantee.Packet is resolved it by moderator after entering input control and route moderator, extracts destination address wherein, judgement direction of transfer; Then cross selection switch is accepted packet and the direction of transfer signal that moderator is sent, and packet is sent to correct output port, and output buffering and controller are responsible for sending data to next route.The present invention is by using special data microplate form, use specific multicast dimension order routing algorithm, and the improvement to arbitration modules in router on general sheet and cross selection switch module, make moderator can identify a plurality of addresses and judge different transmission directions, then by cross selection switch by Packet Generation to different output ports.
Multicast router structure of the present invention has simple in structure, complete function, and strong adaptability, can realize the advantages such as Multicast function.

Claims (6)

1. the NoC router based on multicast dimension order routing algorithm, is characterized in that, comprise input control and route moderator, cross selection switch and and output buffering and controller; Described input control and route moderator are connected with described cross selection switch, and described cross selection switch is connected with described output buffering and controller; Packet is resolved this packet by moderator after entering input control and route moderator, extracts the one or more destination addresses that comprise in this packet, judgement packet direction of transfer, and by Packet Generation to cross selection switch; Cross selection switch is accepted packet and the direction of transfer signal that described input control and route moderator are sent, and packet is sent to correct output port, and output buffering and controller are responsible for sending data to next routing node.
2. the NoC router based on multicast dimension order routing algorithm according to claim 1, is characterized in that, described packet adopts data microplate form, is divided into a microplate, middle microplate and tail microplate; Microplate is mainly used in pointing out the arrival of new data, and record the first two destination address information that data will be sent to; Middle microplate is mainly used in depositing the concrete data message of transmission; Tail microplate is used for being mainly used in reminder-data bag and transmits complete.
3. the NoC router based on multicast dimension order routing algorithm according to claim 2, it is characterized in that, in described microplate, if can not deposit not complete destination address information because destination address information too much makes a microplate, use the follow-up middle microplate of a microplate to deposit the destination address information that a microplate has not yet been deposited.
4. a routing algorithm for the NoC router based on multicast dimension order routing algorithm, is characterized in that, data transmission procedure is as follows:
Step 1: the data microplate of packet arrives input control and the route moderator of NoC router, and whether the data microplate that input control and the judgement of route moderator arrive is a microplate; If a microplate is set to "True" by Route maintenance sign, and judge whether this microplate has comprised whole address informations, if not, wait for that subsequent packet contains the arrival of the middle microplate of address information.The data microplates that comprise address information when all are compared the address information in these data microplates after arriving with local routing node address information, according to X-Y routing rule, judge the sending direction of packet, by Packet Generation to cross selection switch;
Step 2: data microplate is transferred into cross selection switch; Cross selection switch receives the packet of input control and the transmission of route moderator; If the data transmission direction of judgement is single direction in step 1, data microplate is sent to output buffering and the controller that data microplate will be carried; If the data transmission direction of judgement is multiple directions in step 1, according to different direction of transfer duplicate packet, reject with the different destination address of this direction of transfer, the packet of repacking is sent to corresponding output buffering and controller;
Step 3: data have been sent to some or certain several output bufferings and controller module, Req_que=1 now, data are write to buffer memory (Buffer_write=1), to cross bar switch, send answer signal, and send request to downstream node data output signal.Send answer signal Ack_que=1 now to last routing node, represent that data successfully forward.
5. the routing algorithm of the NoC router based on multicast dimension order routing algorithm according to claim 3, is characterized in that, in described step 1, the method for the sending direction of judgement packet is as follows:
The the 3rd to the 6th of compare address microplate with local routing node address first 4, if the former is large, represent that destination node is on the right side of present node, and the Select1 pin of putting input control and route moderator is " 001 "; If the latter is large, represent that destination node is in the left side of present node, the Select1 pin of putting input control and route moderator is " 010 ";
When the 3rd to the 6th of address microplate with local routing node address front 4 same when large, the 7th to the 10th of compare address microplate with local routing node address latter 4; If the former is large, represent that destination node is at the downside of present node, south namely, the Select1 pin of putting input control and route moderator is " 011 "; If the latter is large, represent that destination node is at the upside of present node, the Select1 pin of putting input control and route moderator is " 100 ";
If the 7th to the 10th of address microplate with local routing node address rear 4 equally large, represent that present node is destination node, the Select1 pin of putting input control and route moderator is " 000 ".
6. the routing algorithm of the NoC router based on multicast dimension order routing algorithm according to claim 3, it is characterized in that, in described step 2, the process that packet is transferred into cross selection switch is: when request signal that the port of one of them input control and route moderator is sent, if there is virtual circuit inhibit signal, first whether the direction of judgement transmission virtual circuit inhibit signal is consistent with the direction of request signal, be that same port sends, if not, represent that this route is taken by other ports, can not transmit asked signal; Whether the port direction that then detects this input control and route moderator has virtual circuit inhibit signal, if do not had, the Route Selection signal storage of just input control and route moderator being sent is in local storage, the data message sending is kept in local cache, and sends answer signal to input control and the route moderator of sending data.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106161254A (en) * 2016-07-18 2016-11-23 中国科学院计算技术研究所 A kind of many purposes data transmission network road route device, method, chip, router
CN106603420A (en) * 2016-11-22 2017-04-26 北京控制工程研究所 Network-on-chip router with real-time and fault-tolerant feature
CN109150731A (en) * 2018-09-19 2019-01-04 合肥工业大学 Multicast packet connection circuit and its method for routing based on convolutional neural networks
CN109873771A (en) * 2019-01-21 2019-06-11 佛山市顺德区中山大学研究院 A kind of network-on-a-chip and its communication means
CN110659144A (en) * 2019-09-12 2020-01-07 无锡江南计算技术研究所 High throughput hybrid arbitrated routing mechanism supporting request-response multiport asynchronous multicast
CN111245730A (en) * 2020-01-15 2020-06-05 中山大学 Routing system and communication method of network on chip
CN112163673A (en) * 2020-09-28 2021-01-01 复旦大学 Population routing method for large-scale brain-like computing network
CN112532527A (en) * 2020-12-07 2021-03-19 清华大学 Routing control method and artificial intelligence processor
CN112988653A (en) * 2019-12-16 2021-06-18 北京希姆计算科技有限公司 Data processing circuit, apparatus and method
CN113203940A (en) * 2021-04-29 2021-08-03 桂林电子科技大学 Parallel testing method in 3D NoC test planning
CN114363246A (en) * 2020-09-30 2022-04-15 北京灵汐科技有限公司 Many-core network-on-chip data transmission method, device, equipment and medium
CN114615215A (en) * 2022-03-25 2022-06-10 中国电子科技集团公司第五十八研究所 Data packet coding method for inter-chip integrated routing on supporting chip
WO2024082748A1 (en) * 2022-10-17 2024-04-25 声龙(新加坡)私人有限公司 Data storage system, and data addressing and returning method for data storage structure of data storage system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1788500A (en) * 2003-05-14 2006-06-14 皇家飞利浦电子股份有限公司 Time-division multiplexing circuit-switching router
CN103038760A (en) * 2009-09-18 2013-04-10 德克萨斯系统大学董事会 Data multicasting in a distributed processor system
CN103283192A (en) * 2011-03-28 2013-09-04 松下电器产业株式会社 Repeater, method for controlling repeater, and program

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1788500A (en) * 2003-05-14 2006-06-14 皇家飞利浦电子股份有限公司 Time-division multiplexing circuit-switching router
CN103038760A (en) * 2009-09-18 2013-04-10 德克萨斯系统大学董事会 Data multicasting in a distributed processor system
CN103283192A (en) * 2011-03-28 2013-09-04 松下电器产业株式会社 Repeater, method for controlling repeater, and program

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZHONGHAI LU等: "Connection-oriented Multicasting in Wormhole-switched Networks on Chip", 《EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006. IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON》 *

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* Cited by examiner, † Cited by third party
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