CN101996868B - Forming method of P-type and N-type semiconductor thin layers arranged in alternant mode - Google Patents
Forming method of P-type and N-type semiconductor thin layers arranged in alternant mode Download PDFInfo
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- CN101996868B CN101996868B CN2009100577836A CN200910057783A CN101996868B CN 101996868 B CN101996868 B CN 101996868B CN 2009100577836 A CN2009100577836 A CN 2009100577836A CN 200910057783 A CN200910057783 A CN 200910057783A CN 101996868 B CN101996868 B CN 101996868B
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Abstract
The invention discloses a forming method of P-type and N-type semiconductor thin layers arranged in an alternant mode, comprising the following steps: 1) growing a layer of first epitaxial layer on a silicon substrate; 2) primarily etching on the first epitaxial layer to form grooves; 3) growing insulation layers on the surface of the first epitaxial layer and in the grooves; 4) removing the insulation layers at the bottoms of the grooves; 5) secondarily etching the grooves formed by the primary etching to form deep grooves; 6) filling the deep grooves by the selective epitaxy to form a second epitaxial layer which has opposite conduction type with the first epitaxial layer; 7) removing the insulation layers; and 8) removing the grooves by the chemical-mechanical lapping to obtain the P-type and N-type semiconductor thin layers arranged in alternant mode. By using the method of the invention, the problem of cavities existing in the grooves which are filled by the epitaxy is solved, and the thin layers of P-type and N-type semiconductor can be obtained and arranged in alternant without the cavities, thereby improving the performance of the device.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of P type of alternately arranging and the formation method of N type semiconductor thin layer.
Background technology
Existing super junction MOSFET adopts structure of voltage-sustaining layer---and utilize a series of P type of alternately arranging and N type semiconductor thin layer under cut-off state, under low voltage, just P type N type district to be exhausted; Realize that electric charge compensates each other; Thereby make P type N type district under high-dopant concentration, can realize high puncture voltage; Thereby obtain low on-resistance and high-breakdown-voltage simultaneously, broken conventional power MOSFET theoretical limit.
The structure of existing super junction MOSFET (metal oxide semiconductor field effect tube) device is as shown in Figure 1; The groove-shaped epitaxial loayer 3 that films of opposite conductivity is filled that has is arranged in the epitaxial loayer 2 on silicon substrate 1, and this top, zone is surrounded by P well region 5, N+ well region 6, P+ implanted layer 7 from outside to inside successively.Between two groove-shaped epitaxial loayers 3, be provided with polysilicon 4 on the epitaxial loayer 2, polysilicon 4 is provided with inter-level dielectric 8, and source metal electrode 9 covers whole inter-level dielectric 8 and epitaxial loayer 3.There is back metal electrode (drain electrode) 10 at silicon substrate 1 back side.
The main difficult point of this device manufacturing is the P type of alternately arrangement and the formation of N type semiconductor laminate structure.The formation technology of this structure has two kinds; First kind is to utilize repeatedly photoetching-epitaxial growth to obtain P type and N type doped region (see figure 2) alternately with injecting; Comprise the steps: at first growth one deck epitaxial loayer 11 on silicon substrate 1, and then inject the formation ion implanted region 12 that mixes in place; And then growth one deck epitaxial loayer 11, inject formation ion implanted region 12 again in last time identical injection phase.Multiple cycles epitaxial growth and injection like this reaches needed channel depth until epitaxial thickness, forms a plurality of ion implanted regions 13.Inject the doped region diffusion at boiler tube more at last and make a plurality of ion implanted regions 13 form the doped region 14 of a completion, complete like this P (N) type thin layer is just calculated completion.The problem that the method exists at first is that cost is higher, and extension all is that semiconductor is made cost higher technology, particularly extension with injecting, in general semiconductor is made generally for once; Next is a difficult technique with control, and epitaxial growth several times requires identical resistivity, and identical film quality is had relatively high expectations to the stable aspect of technology; Each in addition injection all requires in identical position, all requires very high to aligning, the precision aspect of injecting.
A kind of in addition manufacturing process is an open channels on N type silicon epitaxy layer; In groove, insert P type extension then; Specifically comprise the steps: the at first silicon epitaxy layer 2 of growth one bed thickness on silicon substrate 1; On this epitaxial loayer 2, form a groove 15 then, using with epitaxial loayer 2 has the silicon epitaxy filling groove 15 of contra-doping mutually again, forms epitaxial loayer 3 (see figure 3)s.The main difficult point of the method is that the extension of groove is filled.Because the difference of groove top and channel bottom growth rate generally have the cavity existence in groove inside so extension is filled the back, and the cavity can produce certain influence to the performance of device.
Summary of the invention
The technical problem that the present invention will solve provides a kind of P type of alternately arranging and the formation method of N type semiconductor thin layer; This method has solved the extension filling groove and has had empty problem; Can obtain not have the P type and the N type semiconductor thin layer alternately arranged in cavity, to improve the performance of device.
For solving the problems of the technologies described above, the present invention provides a kind of P type of alternately arranging and the formation method of N type semiconductor thin layer, comprises following steps:
1) growth one deck first epitaxial loayer on silicon substrate;
2) on first epitaxial loayer, carry out etching formation first time groove;
3) at first epi-layer surface and groove growth inside insulating barrier;
4) insulating barrier of removal channel bottom;
5) groove that the first time, etching formed is carried out etching formation second time deep trench;
6) with selective epitaxial deep trench is filled, form second epitaxial loayer, this second epitaxial loayer and first epitaxial loayer have films of opposite conductivity;
7) remove insulating barrier;
8) remove groove with cmp, can obtain P type and the N type semiconductor thin layer alternately arranged.
Compare with prior art, the present invention has following beneficial effect: in the P type that replaces of super junction and N type thin layer form, for first ditch groove on epitaxial loayer, insert the technology of the silicon epitaxy of phase contra-doping again, fill in the nothing cavity of groove is difficult point.The present invention mainly solves extension filling groove problem.Adopt the inventive method can obtain do not have empty P type and the N type semiconductor thin layer alternately arranged, to improve the performance of device.
Description of drawings
Fig. 1 is the cellular construction sketch map of existing super junction MOSFET device;
Fig. 2 is existing first kind of P type and N type semiconductor thin layer manufacturing process flow diagram of alternately arranging;
Fig. 3 is existing second kind of P type and N type semiconductor thin layer manufacturing process flow diagram of alternately arranging;
Fig. 4 is the variation relation sketch map of reactant concentration and gash depth in the gas phase CVD epitaxial growth;
Fig. 5 be during with the direct filling groove of epitaxy technique silicon epitaxy at the inner growing state sketch map of groove;
Fig. 6-Figure 14 is the schematic flow sheet of the inventive method.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.
The present invention proposes a kind of formation and replaces the P type of arrangement and the process of N type semiconductor thin layer, and this structure applications is in super junction MOSFET.The principal character of this method is: after N type epitaxial growth on the silicon substrate, etching groove is accomplished in two steps, and the etching depth in second step is equal to or greater than the height of the needed P type of device thin layer; Wherein after the first step etching at silicon chip surface and groove growth inside insulating barrier (this insulating barrier can adopt silica and/or silicon nitride), the inner insulating barrier of groove keeps after the second step etching; Etching groove is filled with selective epitaxial after accomplishing.
For gas phase CVD epitaxial growth, because the difference of groove internal-response substrate concentration, to channel bottom, growth rate is more and more slower from the groove top.The variation of reactant concentration is not linear variation with the variation of gash depth, but along with the increase of the degree of depth begins to change fast, more and more slower then, is tending towards constant (see figure 4) after arriving certain depth; The epitaxial growth rate variations is also similar.So during with the direct filling groove of epitaxy technique; Far away more apart from the groove top, epitaxial growth speed is slow more, though growth rate is tending towards constant after surpassing certain distance; But because faster a lot of near the groove top than groove, thus cause groove too early seal (see figure 5).
Like Fig. 6-shown in Figure 14, the inventive method specifically comprises the steps:
1) epitaxial growth on silicon substrate 1 forms epitaxial loayer 2, and its thickness is about 20.0-80.0 μ m (micron), sees Fig. 6;
2) on epitaxial loayer 2, carry out the etching groove first time, form groove 16, its width is about 1.0-10.0 μ m, and the degree of depth is about 1.0-10.0 μ m, sees Fig. 7;
3) behind first time etching groove, in groove 16 inside and superficial growth one layer insulating 17 (silica and/or silicon nitride), see Fig. 8;
4) insulating barrier 17 on 18 protection grooves 16 surfaces is with photoresist carved the insulating barrier 17 that goes to groove 16 bottoms with dry etching method, and the insulating barrier 17 of groove 16 sidewalls does not receive the influence of etching technics, sees Fig. 9;
5) remove photoresist 18 (see figure 10)s on groove 16 surface;
6) and then in groove 16 identical positions carry out the etching groove second time, for the second time etching is just deepened the groove of etching for the first time, and insulating barrier 17 reservations of flute surfaces and lateral growth after the etching for the first time.Like this through after twice etching and insulating barrier 17 growths; Can form a deep trench 19: deep trench 19 tops and surface have insulating barrier 17 to cover; Deep trench 19 bottoms have no material to cover, and the degree of depth of the deep trench 19 of etching formation for the second time should be equal to or greater than the height of the required P type thin layer of device, the width of this deep trench 19 and groove 16 identical (width is 1.0-10.0 μ m); The degree of depth is the 10.0-50.0 micron, sees Figure 11;
7), form and to have the epitaxial loayer 3 of films of opposite conductivity with epitaxial loayer 2 (like epitaxial loayer 2 are N types, and then epitaxial loayer 3 is P types with selective epitaxial filling groove 19; Like epitaxial loayer 2 are P types, and then epitaxial loayer 3 is N types); The temperature of this selective epitaxial process is 800-1100 degree centigrade, and pressure is the 20-760 holder; The silicon source is a dichloro-dihydro silicon, and flow is the 50-1000 ml/min; Etching gas is hydrogen chloride or hydrogen fluoride, and flow is the 50-1000 ml/min; When carrying out trench fill with the suitable selectivity epitaxy technique like this, because insulating barrier 17 protections are arranged at deep trench 19 tops, extension can not grown; Deep trench 19 bottom epitaxial growth speed approximately equals, the filling effect of groove can be greatly improved like this, sees Figure 12;
8) selective epitaxial is filled the back with dry method or wet etching, and perhaps other method such as cmp is removed insulating barrier 17, sees Figure 13;
9) grind off the empty groove in top with cmp again, can obtain the P type and the N type semiconductor thin layer of alternately arrangement, wherein the amount of cmp should be controlled under the bottom of groove 16, and on the bottom of deep trench 19, sees Figure 14.
Be 10 microns, the N type epitaxial loayer of 40 micron thick with width below, width is that 5 microns, the P type epitaxial loayer of 40 micron thick are that example is explained implementation method of the present invention:
1) N type epitaxial loayer 2 (see figure 6)s of growth one deck 42-52 micron thick on silicon substrate 1;
2) on N type epitaxial loayer 2, whenever carving width at a distance from 10 microns is that 5 microns, the degree of depth are strip-shaped grooves 16 (see figure 7)s of 2-10 micron;
3) in groove 16 inside and superficial growth one layer insulating 17 (silica and/or silicon nitride), thickness is 100-10000 dust (see figure 8);
4) 18 protect surperficial insulating barrier 17 with photoresist, carve insulating barrier 17 (see figure 9)s of going to groove 16 bottoms with lithographic method;
5) remove photoresist 18 (see figure 10)s on groove 16 surface;
6) carve the groove 19 (seeing Figure 11) that the shape width is identical, the degree of depth is the 40-50 micron in the position of groove 16;
7), form P type epitaxial loayer 3 (seeing Figure 12) with selective epitaxial filling groove 19;
8) remove insulating barrier 17 (seeing Figure 13) with dry method or wet etching;
9) remove groove with cmp, form the P type epitaxial loayer 3 of alternately arrangement and the semiconductor lamella (seeing Figure 14) of N type epitaxial loayer 2.
Claims (9)
1. one kind replaces the P type of arrangement and the formation method of N type semiconductor thin layer, it is characterized in that: comprise following steps:
1) growth one deck first epitaxial loayer on silicon substrate;
2) on first epitaxial loayer, carry out etching formation first time groove;
3) at first epi-layer surface and groove growth inside insulating barrier;
4) insulating barrier of removal channel bottom;
5) groove that the first time, etching formed is carried out etching formation second time deep trench; Keep for the second time after the etching for the first time the insulating barrier in the groove side surface growth after the etching, the degree of depth of the deep trench that forms of etching is equal to or greater than the height of the required P type thin layer of device for the second time;
6) with selective epitaxial deep trench is filled, form second epitaxial loayer, this second epitaxial loayer and first epitaxial loayer have films of opposite conductivity; The temperature of said selective epitaxial is 800-1100 degree centigrade, and pressure is the 20-760 holder; The silicon source of said selective epitaxial is a dichloro-dihydro silicon, and flow is the 50-1000 ml/min; The etching gas of said selective epitaxial is hydrogen chloride or hydrogen fluoride, and flow is the 50-1000 ml/min;
7) remove insulating barrier;
8) remove groove with cmp, can obtain P type and the N type semiconductor thin layer alternately arranged.
2. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer, it is characterized in that: the thickness of first epitaxial loayer is 20.0-80.0 μ m in the said step 1).
3. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer is characterized in that: the width of groove is 1.0-10.0 μ m said step 2), and the degree of depth is 1.0-10.0 μ m.
4. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer, it is characterized in that: insulating barrier is silica and/or silicon nitride in the said step 3).
5. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer; It is characterized in that: the etching of channel bottom insulating barrier adopts dry etch process in the said step 4); Flute surfaces is protected with photoresist, and the insulating barrier of trenched side-wall does not receive the influence of etching technics.
6. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer; It is characterized in that: the degree of depth of the deep trench of etching formation for the second time is equal to or greater than the height of the required P type thin layer of device in the said step 5); The width of this deep trench is 1.0-10.0 μ m, and the degree of depth is 10.0-50.0 μ m.
7. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer is characterized in that: dry etching or wet etching or cmp are adopted in the removal of insulating barrier in the said step 7).
8. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer is characterized in that: the amount of cmp in the said step 8), and under the bottom of groove, and on the bottom of deep trench.
9. the P type of alternately arranging as claimed in claim 1 and the formation method of N type semiconductor thin layer, it is characterized in that: said first epitaxial loayer is the P type, second epitaxial loayer is the N type; Perhaps said first epitaxial loayer is the N type, and second epitaxial loayer is the P type.
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| CN103000519B (en) * | 2011-09-09 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Method for removing silicon ridge produced in epitaxial deposition of super-junction high-pressure device |
| CN103094106B (en) * | 2011-10-28 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The P type be alternately arranged and the preparation method of N type semiconductor thin layer |
| CN103035493B (en) * | 2012-06-15 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Forming method for alternatively-arranged P columns and N columns of semiconductor component |
| CN105957897B (en) * | 2016-06-28 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove grid super node MOSFET |
| CN105895533B (en) * | 2016-06-28 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of super-junction structure |
| CN111573616B (en) * | 2020-04-24 | 2024-02-13 | 中国电子科技集团公司第十三研究所 | Composite high aspect ratio groove standard template and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170074A (en) * | 2007-11-13 | 2008-04-30 | 北京大学 | A method for improving ultra-deep sub-micro MOSFET radiation-resisting performance |
| CN101202222A (en) * | 2006-12-11 | 2008-06-18 | 东部高科股份有限公司 | Method of manufactruing trench mosfet device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202222A (en) * | 2006-12-11 | 2008-06-18 | 东部高科股份有限公司 | Method of manufactruing trench mosfet device |
| CN101170074A (en) * | 2007-11-13 | 2008-04-30 | 北京大学 | A method for improving ultra-deep sub-micro MOSFET radiation-resisting performance |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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