CN101661918B - Quad Flat No Lead Package - Google Patents
Quad Flat No Lead Package Download PDFInfo
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- CN101661918B CN101661918B CN2009100044085A CN200910004408A CN101661918B CN 101661918 B CN101661918 B CN 101661918B CN 2009100044085 A CN2009100044085 A CN 2009100044085A CN 200910004408 A CN200910004408 A CN 200910004408A CN 101661918 B CN101661918 B CN 101661918B
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- 229910000679 solder Inorganic materials 0.000 claims abstract 35
- 239000008393 encapsulating agent Substances 0.000 claims abstract 4
- 239000010410 layer Substances 0.000 claims description 214
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 239000000084 colloidal system Substances 0.000 abstract description 15
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000005728 strengthening Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 description 85
- 238000005538 encapsulation Methods 0.000 description 32
- 238000000034 method Methods 0.000 description 25
- 239000011248 coating agent Substances 0.000 description 20
- 238000000576 coating method Methods 0.000 description 20
- 238000012545 processing Methods 0.000 description 20
- 238000012856 packing Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 206010070834 Sensitisation Diseases 0.000 description 3
- 239000013039 cover film Substances 0.000 description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 230000008313 sensitization Effects 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006087 Brown hydroboration reaction Methods 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 208000003351 Melanosis Diseases 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a quad flat non-lead package, which comprises a patterned conductive layer, a first solder mask layer, a chip, a plurality of bonding wires and a packaging colloid. The patterned conductive layer has a surface. The first solder mask layer is disposed on the surface, wherein a portion of the surface of the first solder mask layer is exposed. The chip is disposed on the first solder mask layer, wherein the first solder mask layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder mask layer. The encapsulant encapsulates the patterned conductive layer, the first solder mask layer, the chip and the bonding wires. The quad flat non-leaded package of the invention is provided with the solder mask layer for strengthening the structural strength of the quad flat non-leaded package, so that the patterned conductive layer can have smaller thickness.
Description
Technical field
The invention relates to a kind of Chip Packaging, and particularly relevant for a kind of square flat non-pin (Quad Flat Non-leaded, QFN) encapsulation.
Background technology
Along with the high development of semi-conductor industry, electronics and semiconductor device are applied in the daily life widely, as aspects such as amusement, education, communications and transportation and electrical home appliances.Electronic product is towards design is complicated, size is little, in light weight and the development of hommization aspect, to bring the user more convenience.In encapsulating structure, lead frame is one of element of using always and is applied to multiple encapsulating products.Type with lead frame, quad flat package (Quad Flat Package, QFP) can be divided into I type pin quad flat package (quad flatpackage with " I " lead, QFI), the quad flat Chip Packaging of J type pin (quad flat packagewith " J " lead, QFJ) and square flat non-pin (Quad Flat Non-leaded, QFN) encapsulation.The pin of the lead frame of square flat non-pin encapsulation does not exceed the edge of encapsulating structure, so it has smaller volume.In addition, the square flat non-pin encapsulation has short signaling path and reaches signal transmission speed faster, therefore is one of main flow of low pin position (low pin count) structure dress kenel always.
Generally speaking, in the manufacture process of square flat non-pin encapsulation, can be on lead frame with a plurality of chip configuration, wherein lead frame comprises a plurality of interconnective pin set, and each chip by pin set institute around.Each chip sees through the routing processing procedure and is electrically connected at a pin set.Then, formation is in order to a packing colloid of coated wire frame, chip and bonding wire.At last, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation.
Summary of the invention
The invention provides a kind of square flat non-pin encapsulation, it has less thickness.
The present invention proposes the encapsulation of a kind of square flat non-pin, comprises a patterned conductive layer, one first welding cover layer, a chip, many bonding wires and a packing colloid.Patterned conductive layer has a surface.First welding cover layer is disposed at the surface, and wherein first welding cover layer exposes part surface.Chip configuration is in first welding cover layer, and wherein first welding cover layer is between patterned conductive layer and chip.Bonding wire is electrically connected at the patterned conductive layer that chip and first welding cover layer expose.Packing colloid coats patterned conductive layer, first welding cover layer, chip and bonding wire.
In one embodiment of this invention, above-mentioned chip has a back side on an active surface, active relatively surface and is disposed at a plurality of weld pads on active surface, and the back side of chip contacts with first welding cover layer.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation more comprises an adhesion coating, is disposed between first welding cover layer and the chip.
The present invention proposes the encapsulation of a kind of square flat non-pin, comprises a patterned conductive layer, one first weldering cover, a chip, many bonding wires and a packing colloid.Patterned conductive layer has a surface.First welding cover layer is disposed at the surface, and wherein first welding cover layer exposes part surface.The part surface that chip configuration exposes in first welding cover layer.Bonding wire is electrically connected at the patterned conductive layer that chip and first welding cover layer expose.Packing colloid coats patterned conductive layer, first welding cover layer, chip and bonding wire.
In one embodiment of this invention, above-mentioned patterned conductive layer comprises that a chip carrier reaches a plurality of pins around chip carrier.
In one embodiment of this invention, above-mentioned first welding cover layer extends to the zone between chip carrier and the pin from the surface of patterned conductive layer.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation more comprises one second welding cover layer, is disposed between chip carrier and the pin.
In one embodiment of this invention, the second above-mentioned welding cover layer does not contact with first welding cover layer.
In one embodiment of this invention, above-mentioned chip has a back side on an active surface, active relatively surface and is disposed at a plurality of weld pads on active surface, and the back side of chip contacts with the first surface of patterned conductive layer.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation more comprises an adhesion coating, is disposed between patterned conductive layer and the chip.
In one embodiment of this invention, above-mentioned adhesion coating comprises a B rank adhesion coating.
Based on above-mentioned, square flat non-pin encapsulation of the present invention has in order to strengthen the welding cover layer of its structural strength, so that patterned conductive layer can have less thickness.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A to Fig. 1 G is that the processing procedure of the square flat non-pin encapsulation of first embodiment of the invention is analysed and observe flow chart.
Fig. 2 A to Fig. 2 H is that the processing procedure of the square flat non-pin encapsulation of second embodiment of the invention is analysed and observe flow chart.
Fig. 3 A to Fig. 3 F is that the processing procedure of the square flat non-pin encapsulation of third embodiment of the invention is analysed and observe flow chart.
The main element symbol description:
100,200,300: the square flat non-pin encapsulation
110,210,310: conductive layer
110 ', 210 ', 310 ': patterned conductive layer
110a, 210a, 310a: chip carrier
110b, 210b, 310b: pin
112,212,312: first surface
114,214,314: second surface
118,216,316: the first weld pads
120,230,320: the first welding cover layers
122,232,322: the first openings
124,234: the second openings
130,240,330: chip
132,242,332: active surface
134,244,334: the back side
136,246,336: the second weld pads
140,250,340: adhesion coating
150,260,350: bonding wire
160,270: packing colloid
220: the second welding cover layers
R: groove
Embodiment
First embodiment
Figure 1A to Fig. 1 G is that the processing procedure of the square flat non-pin encapsulation of first embodiment of the invention is analysed and observe flow chart.Please refer to Figure 1A, the conductive layer 110 with a first surface 112 and a second surface 114 is provided.Then, partly remove the conductive layer 110 that is positioned at presumptive area, on the first surface 112 of conductive layer 110, to form a plurality of recess R.In the present embodiment, be to see through to etch partially (half-etching) processing procedure formation recess R.
Please refer to Figure 1B, form the first surface 112 of one first welding cover layer 120, filled up by first welding cover layer 120 so that be formed at the recess R of the first surface 112 of conductive layer 110 to cover conductive layer 110 fully.In a preferred embodiment, more can carry out brown (brown oxidation) processing or melanism (black oxidation) on conductive layer 110 handles, with the surface roughness of increase conductive layer 110, and then the adhesion between the lifting conductive layer 110 and first welding cover layer 120.
Then, please refer to Fig. 1 C, first welding cover layer 120 is carried out patterning to form a plurality of first openings 122, wherein first opening 122 exposes part first surface 112.In other words, first welding cover layer 120 that is formed at part first surface 112 defines a plurality of first weld pads 118.
In the present embodiment, first welding cover layer 120 can be a solid-state shape weldering cover film, and first opening 122 was formed before or after first welding cover layer 120 is attached at conductive layer 110.In an alternate embodiments, a liquid weldering overcoat layer can be coated on the first surface 112 of conductive layer 110, and with its curing and patterning to form first welding cover layer 120.In the present embodiment, first welding cover layer 120 for example is a sensitization B rank film (photosensitive B-staged film).
In addition, in a preferred embodiment, can see through plating (plating) processing procedure and on first weld pad 118, form an electroplated conductive layer (not illustrating).Electroplated conductive layer can be nickel gold lamination or other metal level that is suitable for.It should be noted that and before or after first welding cover layer 120 is formed at conductive layer 110, to form electroplated conductive layer.
Please refer to Fig. 1 D, a plurality of chips 130 are adhered to first welding cover layer 120, then and form many bonding wires 150 to electrically connect chip 130 and conductive layer 110, wherein each chip 130 has an active surperficial back side 134 of 132, active relatively surperficial 132 and is disposed at a plurality of second weld pads 136 of active surperficial 132.Each chip 130 sees through the adhesion coating 140 between chip 130 and conductive layer 110 and is adhered to first welding cover layer 120, so that first welding cover layer 120 is between conductive layer 110 and each chip 130.
In the present embodiment, can see through routing (wire bonding) processing procedure and form bonding wire 150, so that each bonding wire 150 is electrically connected between one first weld pad 118 and one second weld pad 136.Bonding wire 150 for example is a gold thread.
In this enforcement, adhesion coating 140 for example is a B rank adhesion coating (B-staged adhesive layer).B rank adhesion coating 140 can be ABLESTIK 8008,8008HT, 6200,6201,6202C or HITACHI Chemical CO., the SA-200-6 that Ltd. provides, SA-200-10.In one embodiment of this invention, B rank adhesion coating 140 is the back side that is formed on a wafer.After cut crystal, can obtain having a plurality of chips 130 of the adhesion coating 140 that is positioned at the back side 134.Therefore, B rank adhesion coating 140 is suitable for a large amount of productions.In addition, can see through spin coating, printing or other processing procedure that is suitable for to form B rank adhesion coating 140.Adhesion coating 140 is the back side 134 that is formed on chip 130 in advance.Specifically, can provide a wafer earlier with a plurality of chips 130 of arranging in array.Then, form a second order adhesion coating at the back side 134 of chip 130, and it is partly solidified with it to see through heating (heating) or ultraviolet irradiation (UV irradiation), to form B rank adhesion coating 140.In addition, also can before being attached at first welding cover layer 120, chip 130 on first welding cover layer 120, form B rank adhesion coating 140.
In the present embodiment, B rank adhesion coating 140 is full solidification after chip 130 is attached at first welding cover layer 120, or after see through the back and solidify (post curing) and handle and full solidification, or after packed colloid 160 coats full solidification.
Please refer to Fig. 1 E, form a packing colloid 160 of coated with conductive layer 110, first welding cover layer 120, chip 130 and bonding wire 150.The material of packing colloid 160 for example is epoxy resin (epoxy resin).
Please refer to Fig. 1 F, the second surface 114 of conductive layer 110 is carried out etching (etching) to form a patterned conductive layer 110 ', wherein patterned conductive layer 110 ' comprises a chip carrier 110a and around a plurality of pin 110b of chip carrier 110a.Then, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation 100.It should be noted that to be to form on the conductive layer 110 in first welding cover layer 120 any fabrication steps afterwards, partially conductive layer 110 is removed from second surface 114.The method that partially conductive layer 110 is removed from second surface 114 for example is back of the body etching (back-side etching) processing procedure.
Illustrate as Fig. 1 F, square flat non-pin of the present invention encapsulation 100 mainly comprises a patterned conductive layer 110 ', one first welding cover layer 120, a chip 130, many bonding wires 150 and a packing colloid 160.Patterned conductive layer 110 ' has a first surface 112, wherein patterned conductive layer 110 ' comprises a chip carrier 110a and around a plurality of pin 110b of chip carrier 110a, and first welding cover layer 120 extends to zone between chip carrier 110a and the pin 110b from the first surface 112 of patterned conductive layer 110 '.First welding cover layer 120 is disposed at first surface 112, and wherein first welding cover layer 120 exposes part first surface 112.Chip 130 is disposed at first welding cover layer 120, and wherein first welding cover layer 120 is positioned between patterned conductive layer 110 ' and the chip 130.Bonding wire 150 is electrically connected at the patterned conductive layer 110 ' that chip 130 and first welding cover layer 120 expose.Packing colloid 160 coats patterned conductive layer 110 ', first welding cover layer 120, chip 130 and bonding wire 150.
Please refer to Fig. 1 G, in an alternate embodiments, can form a plurality of second openings 124,, and be adhered on the first surface 112 that is exposed by first welding cover layer 120 so that each chip 130 is configured in one second opening 124 at first welding cover layer 120.
Second embodiment
Fig. 2 A to Fig. 2 H is that the processing procedure of the square flat non-pin encapsulation of second embodiment of the invention is analysed and observe flow chart.Please refer to Fig. 2 A, the conductive layer 210 with a first surface 212 and a second surface 214 is provided, and partly remove the conductive layer 210 that is positioned at presumptive area, on the second surface 214 of conductive layer 210, to form a plurality of recess R.In the present embodiment, be to see through to etch partially (half-etching) processing procedure formation recess R.
Please refer to Fig. 2 B, the recess R region on the second surface 214 of conductive layer 210 forms one second welding cover layer 220, so that recess R is filled up by second welding cover layer 220.Then, please refer to Fig. 2 C, form one first welding cover layer 230 with a plurality of first openings 232 at the first surface 212 of conductive layer 210, wherein each first opening 232 is corresponding to a recess R, and first opening 232 exposes part first surface 212.
Please refer to Fig. 2 D, the conductive layer 210 that is exposed by first opening 232 is carried out etching, to form a patterned conductive layer 210 ', wherein patterned conductive layer 210 ' comprises that a chip carrier 210a reaches a plurality of pin 210b around chip carrier 210a.Please refer to Fig. 2 E, first welding cover layer 230 is carried out patterning to form a plurality of second openings 234, wherein second opening 234 exposes part first surface 212.In other words, first welding cover layer 230 that is formed at part first surface 212 defines a plurality of first weld pads 216.
In the present embodiment, first welding cover layer 230 can be solid-state shape weldering cover film, and first opening 232 and second opening 234 are to be formed before or after first welding cover layer 230 is attached at conductive layer 210.In an alternate embodiments, a liquid weldering overcoat layer can be coated on the first surface 212 of conductive layer 210, and with its curing and patterning to form first welding cover layer 230.In the present embodiment, first welding cover layer 230 for example is a sensitization B rank film.
In addition, in a preferred embodiment, can see through electroplating process and on first weld pad 216, form an electroplated conductive layer (not illustrating).Electroplated conductive layer can be nickel gold lamination or other metal level that is suitable for.It should be noted that and to be to form electroplated conductive layer before or after formation first welding cover layer 230 on the conductive layer 210.
Please refer to Fig. 2 F, a plurality of chips 240 are adhered to first welding cover layer 230, and then form many bonding wires 260 to electrically connect chip 240 and patterned conductive layer 210 ', wherein each chip 240 has an active surperficial back side 244 of 242, active relatively surperficial 242 and is disposed at a plurality of second weld pads 246 of active surperficial 242.Each chip 240 is adhered on first welding cover layer 230 through being positioned at the adhesion coating 250 between chip 240 and the patterned conductive layer 210 ', so that first welding cover layer 230 is positioned between patterned conductive layer 210 ' and each chip 240.
In the present embodiment, bonding wire 260 is to see through the routing processing procedure to be formed, so that each bonding wire 260 is electrically connected between one first weld pad 216 and one second weld pad 246.
Please refer to Fig. 2 G, form a packing colloid 270 that coats patterned conductive layer 210 ', first welding cover layer 230, second welding cover layer 220, chip 240 and bonding wire 260.Please refer to Fig. 2 H, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation 200.
Compared to the square flat non-pin encapsulation 100 of Fig. 1 F, the square flat non-pin encapsulation 200 of Fig. 2 H more comprises one second welding cover layer 220 that is disposed between chip carrier 210a and the pin 210b and does not contact with first welding cover layer 230.
In an alternate embodiments, can form a plurality of the 3rd openings (not illustrating) at first welding cover layer 230, so that each chip 240 is disposed at one the 3rd opening and is adhered to the first surface 212 that is exposed by first welding cover layer 230.
The 3rd embodiment
Fig. 3 A to Fig. 3 F is that the processing procedure of the square flat non-pin encapsulation of third embodiment of the invention is analysed and observe flow chart.Please refer to Fig. 3 A, one first welding cover layer 320 is provided and has a first surface 312 and a conductive layer 310 of a second surface 314, and first welding cover layer 320 is to see through model (molding) or printing (printing) and be formed at first surface 312.
Then, please refer to Fig. 3 B, see through little shadow (photolithography) etch process and form a patterned conductive layer 310 ', wherein patterned conductive layer 310 ' comprises that a chip carrier 310a reaches a plurality of pin 310b around chip carrier 310a.
Then, please refer to Fig. 3 C, first welding cover layer 320 is carried out patterning to form a plurality of first openings 322.In other words, first welding cover layer 320 that is formed at part first surface 312 defines a plurality of first weld pads 316.It should be noted that the present invention does not limit the order in order to the patterning process of first opening 322 that forms the patterned conductive layer 310 ' and first welding cover layer 320.
In the present embodiment, first welding cover layer 320 can be a solid-state shape weldering cover film, and first opening 322 was formed before or after first welding cover layer 320 is attached at conductive layer 310.In an alternate embodiments, a liquid weldering overcoat layer can be coated on the first surface 312 of conductive layer 310, and with its curing and patterning to form first welding cover layer 320.In the present embodiment, first welding cover layer 320 for example is a sensitization B rank film.
In addition, in a preferred embodiment, can see through electroplating process and on first weld pad 316, form an electroplated conductive layer (not illustrating).Electroplated conductive layer can be nickel gold lamination or other metal level that is suitable for.It should be noted that and to be to form electroplated conductive layer before or after formation first welding cover layer 320 on the conductive layer 310.
Please refer to Fig. 3 D, a plurality of chips 330 are adhered to first welding cover layer 320, and then form many bonding wires 350 to electrically connect chip 330 and patterned conductive layer 310 ', wherein each chip 330 has an active surperficial back side 334 of 332, active relatively surperficial 332 and is disposed at a plurality of second weld pads 336 on active surperficial 332.Each chip 330 is adhered to first welding cover layer 320 through being positioned at the adhesion coating 340 between chip 330 and the patterned conductive layer 310 ', so that first welding cover layer 320 is positioned between each chip 330 and the patterned conductive layer 310 '.
In the present embodiment, bonding wire 350 is to see through the routing processing procedure to be formed, so that each bonding wire 350 is electrically connected between one first weld pad 316 and one second weld pad 336.
Please refer to Fig. 3 E, form a packing colloid 360 that coats patterned conductive layer 310 ', first welding cover layer 320, chip 330 and bonding wire 350.Please refer to Fig. 3 F, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation 300.
Square flat non-pin encapsulation 100 compared to Fig. 1, the square flat non-pin of Fig. 3 F encapsulation 300 does not extend to zone between chip carrier 310a and the pin 310b from the first surface 312 of patterned conductive layer 310 ', and the regional packed colloid 360 between chip carrier 310a and the pin 310b fills up.
In an alternate embodiments, can form a plurality of second openings (not illustrating) at first welding cover layer 320, so that each chip 330 is disposed at one second opening and is adhered to the first surface 312 that is exposed by first welding cover layer 320.
In sum, compared to traditional square flat non-pin encapsulation, square flat non-pin encapsulation of the present invention has in order to strengthen the welding cover layer of its structural strength, so that patterned conductive layer can have less thickness.In addition, the square flat non-pin encapsulation has less integral thickness and lower manufacturing cost, so that production capacity (throughput) obtains to promote.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/201,236 US7851896B2 (en) | 2005-07-14 | 2008-08-29 | Quad flat non-leaded chip package |
| US12/201,236 | 2008-08-29 |
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| Publication Number | Publication Date |
|---|---|
| CN101661918A CN101661918A (en) | 2010-03-03 |
| CN101661918B true CN101661918B (en) | 2011-10-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100044085A Expired - Fee Related CN101661918B (en) | 2008-08-29 | 2009-02-12 | Quad Flat No Lead Package |
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| Country | Link |
|---|---|
| CN (1) | CN101661918B (en) |
| TW (1) | TWI462252B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201348A (en) * | 2010-03-26 | 2011-09-28 | 力成科技股份有限公司 | Array Dicing Quad Flat No Leads Packaging Method |
| CN103050415A (en) * | 2012-12-10 | 2013-04-17 | 华天科技（西安）有限公司 | Sequential browning and green paint brushing-based flat package manufacturing process |
| TWI556359B (en) * | 2015-03-31 | 2016-11-01 | 南茂科技股份有限公司 | Quad flat non-leaded package structure and leadframe thereof |
| TWI688057B (en) * | 2018-12-11 | 2020-03-11 | 南茂科技股份有限公司 | Semiconductor package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
| TWI283471B (en) * | 2002-05-23 | 2007-07-01 | Hitachi Ltd | Semiconductor device and electronic apparatus |
| TWI236721B (en) * | 2004-06-29 | 2005-07-21 | Advanced Semiconductor Eng | Leadframe for leadless flip-chip package and method for manufacturing the same |
-
2009
- 2009-01-15 TW TW098101388A patent/TWI462252B/en not_active IP Right Cessation
- 2009-02-12 CN CN2009100044085A patent/CN101661918B/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| TWI462252B (en) | 2014-11-21 |
| TW201010035A (en) | 2010-03-01 |
| CN101661918A (en) | 2010-03-03 |
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