TWI556359B - Quad flat non-leaded package structure and leadframe thereof - Google Patents

Description

Quad flat no-lead package structure and quad flat no-lead package leadframe structure

This invention relates to a semiconductor package structure, and more particularly to a quad flat no-lead (QFN) package structure.

Semiconductor packaging technology includes many package types, and the quad flat no-lead package of the quad flat package series has a short signal transmission path and a relatively fast signal transmission speed, and thus is one of the mainstream of the package type. In general, when the wafer is bonded to the lead frame, such as wire bonding or flip chip bonding, a backside tape is disposed at the bottom of the lead frame to enable The lead frame can be fixed in position by vacuum adsorption to ensure smooth bonding of the wire bonding or flip chip bonding process, thereby improving the yield rate of the wafer and lead frame bonding process.

However, after the wafer and leadframe bonding process is completed, the aforementioned adhesive film is usually removed for subsequent processing, and the removal of the adhesive film requires an additional process, which generally increases manufacturing costs and man-hours. In addition, the wafer and lead frame are electrically Removing the film after the sexual connection may cause the lead frame, the bonding wire and the bump to be pulled, which may cause an abnormal connection between the wafer and the lead frame, which may reduce the package yield.

The invention provides a quad flat no-lead package structure, which can simplify the process and improve the yield by the configuration of the dielectric film.

The present invention provides a quad flat no-lead leadframe structure that simplifies the process and improves yield.

The invention provides a quad flat no-lead package structure comprising a lead frame, a dielectric film, a wafer, a plurality of bonding wires and an encapsulant. The leadframe includes multiple pins. The dielectric film is disposed on the lead frame. The dielectric film has a plurality of openings, and each of the openings is located above each corresponding pin. The wafer is disposed on a dielectric film. Each of the bonding wires is connected between the wafer and a pin exposed by the corresponding opening. The package is coated with a lead frame, a dielectric film, a wafer, and a bonding wire.

In an embodiment of the invention, the pins extend from below the wafer to the edge of the encapsulant.

In an embodiment of the invention, the lead frame further includes a wafer holder, wherein the wafer holder is located under the wafer, and the lead surrounds the wafer holder.

In an embodiment of the invention, the distribution range of the dielectric film described above covers between pins.

In an embodiment of the invention, the edge of the dielectric film and the encapsulant are The edges of the body are aligned.

In an embodiment of the invention, the maximum aperture of each of the openings is not beyond the outer contour of the corresponding pin.

In an embodiment of the invention, the dielectric film is located between the wafer and the lead frame.

The present invention provides another quad flat no-lead flip chip package structure comprising a lead frame, a dielectric film, a wafer and an encapsulant. The leadframe includes multiple pins. The dielectric film is disposed on the lead frame. The dielectric film has a plurality of openings, and each of the openings is located above the corresponding pin. The wafer is disposed on a dielectric film. The wafer has an active surface and a plurality of conductive bumps are disposed on the active surface. Each of the conductive bumps is connected between the wafer and a pin exposed by the corresponding opening. The encapsulant encapsulates the leadframe, the dielectric film, the wafer, and the conductive bumps.

In an embodiment of the invention, the maximum aperture of each of the openings is not beyond the outer contour of the corresponding pin.

The invention provides a quad flat no-lead leadframe structure comprising a lead frame and a dielectric film. The leadframe includes a plurality of pins with at least one spacing between adjacent pins. The dielectric film is placed on the pin and covers the entire distance between the pin and the adjacent pin. The dielectric film has a plurality of openings corresponding to the pins, and the maximum aperture of each of the openings does not exceed the outer contour of the corresponding pins.

Based on the above, since the present invention is provided with a dielectric film on the lead frame to cover the range distribution between the leads of the lead frame, when the wafer is bonded to the lead frame (ie, the bonding process is performed), the lead frame can be used Fix the position by vacuum adsorption Set to ensure that the wire bonding or flip chip bonding process can proceed smoothly. In addition, since the dielectric film is located between the wafer and the lead frame, the dielectric film can be further removed after the bonding process is completed, and the subsequent process can be continued. The quad flat no-lead package structure provided by the invention simplifies process complexity and improves yield.

The above described features and advantages of the invention will be apparent from the following description.

10, 20, 30, 40‧‧‧ square flat leadless package structure

100, 110‧‧‧ lead frame

102‧‧‧ pin

114‧‧‧ Wafer holder

200‧‧‧ dielectric film

202‧‧‧Opening

300, 310‧‧‧ wafer

302‧‧‧ solder pads

312‧‧‧Electrical bumps

400‧‧‧multiple bonding wires

500‧‧‧Package colloid

600‧‧‧Adhesive layer

A‧‧‧ active face

G‧‧‧ spacing

I-I', II-II', III-III', IV-IV'‧‧‧

L‧‧‧ lead frame structure

S‧‧‧ Space

1A is a top view of a quad flat no-lead package structure in accordance with an embodiment of the present invention.

1B is a cross-sectional view of the quad flat no-lead package structure of FIG. 1A taken along line I-I'.

2A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention.

2B is a cross-sectional view of the quad flat no-lead package structure of FIG. 2A taken along line II-II'.

3A is a top view of a quad flat no-lead package structure in accordance with yet another embodiment of the present invention.

3B is a cross-sectional view of the quad flat no-lead package structure of FIG. 3A taken along line III-III'.

4A is a diagram of a quad flat no-lead package structure according to still another embodiment of the present invention; Top view.

4B is a cross-sectional view of the quad flat no-lead package structure of FIG. 4A taken along line IV-IV'.

1A is a top view of a quad flat no-lead package structure in accordance with an embodiment of the present invention. 1B is a cross-sectional view of the quad flat no-lead package structure of FIG. 1A taken along line I-I'. Referring to FIG. 1A and FIG. 1B simultaneously, in the embodiment, the quad flat no-lead package structure 10 includes a lead frame 100, a dielectric film 200, a wafer 300, a plurality of bonding wires 400, and an encapsulant 500. To clearly illustrate the invention, the distribution of encapsulation 500 will be indicated by dashed lines and dielectric film 200 will be indicated by diagonal lines. In the following, for convenience of explanation, the lead frame 100 drawn in the drawing of the present invention is only one of the units on the entire lead frame. In practice, the dielectric film 200 is a film formed corresponding to the size of the entire lead frame. The material for the dielectric film 200 may be, for example, a die attach film (DAF) or a material similar thereto.

In particular, leadframe 100 can have a plurality of pins 102 from which a plurality of leads 102 of leadframe 100 extend from the bottom of wafer 300 to the edge of encapsulant 500. In detail, as shown in FIG. 1A, a plurality of pins 102 are distributed around the periphery of the wafer 300, and adjacent pins 102 are at least spaced apart from each other by a distance G. Generally, the range of the pitch G is approximately Around 120 um, and each pin 102 extends from below the wafer 300 to the edge of the encapsulant 500.

On the other hand, the dielectric film 200 is disposed on the lead frame 100. The dielectric film 200 has a plurality of openings 202, and the openings 202 are respectively located on the corresponding pins 102. In the present embodiment, the opening 202 can be formed by etching or laser removing the dielectric film 200, and the opening 202 can be formed before or after the dielectric film 200 is disposed on the lead frame 100. The distribution of the dielectric film 200 covers the area between the pins 102, and the edge of the dielectric film 200 is, for example, aligned with the edge of the encapsulant 500, and the maximum aperture of each opening 202 of the dielectric film 200 does not exceed each other. The outer contour of the corresponding pin 102, in other words, the opening 202 in the dielectric film 200 can be matched with the pin 102 of the lead frame 100 to form a hermetic structure, so that the lead frame 100 with the surface of the dielectric film 200 attached thereto Can be vacuum absorbed. In detail, the minimum aperture range of the aperture of the dielectric film 200 opening 202 is to expose the bonding area of the bonding wire 400 and the pin 102, and the maximum aperture range is the upper surface of the entire pin 102 without exceeding the outer contour of the pin 102. (not shown). Here, the lead frame 100 and the dielectric film 200 may constitute a lead frame structure L. As shown in FIG. 1B, the wafer 300 is disposed on the dielectric film 200 such that the dielectric film 200 is located between the wafer 300 and the lead frame 100, and the wafer 300 may have a plurality of pads 302, and the wafer 300 and the corresponding opening The exposed pins 102 of the 202 can be electrically connected by the bonding wires 400.

In the present embodiment, the bonding wires 400 are formed in a wire bonding process, and the pads 302 are electrically connected to the leads 102 exposed by the corresponding openings 202 by the bonding wires 400. Here, the material of the bonding wire 400 is, for example, gold, copper, silver alloy or other suitable electrically conductive material.

It is worth noting that due to the dielectric film 200 and the lead frame 100 The arrangement can form an airtight structure. Therefore, when the bonding process of the wafer 300, the bonding wire 400 and the lead frame 100 is performed, the lead frame 100 can be fixed by vacuum suction to ensure that the bonding process can be smoothly performed.

In order to protect the wafer 300 and the bonding wires 400 and to ensure the reliability of the quad flat no-lead package structure 10, the encapsulant 500 covers the leadframe 100, the dielectric film 200, the wafer 300, and the bonding wires 400. As shown in FIG. 1B, the encapsulant 500 can be distributed on both sides of the lead frame 100. In addition to covering the dielectric film 200, the wafer 300, and the bonding wire 400, the encapsulant 500 can be filled in the space S on the other side of the lead frame. In other words, the encapsulant 500 can be filled between any two adjacent pins 102 to cover all of the pins 102. Of course, the end of the pin 102 is exposed outside the encapsulant 500 to facilitate electrical connection with an external device such as a circuit board.

In addition to the above, the embodiment further includes an adhesive layer 600 disposed between the wafer 300 and the dielectric film 200 for bonding the wafer 300 to the dielectric film 200.

When the wafer 300 is bonded to the lead frame 100, since the dielectric film 200 and the lead frame 100 together form an airtight structure, the lead frame 100 can be fixed by vacuum suction, thereby achieving the engagement of the lead frame 100. The effect of offset is not easy to occur during the process. In detail, when the wire bonding process is performed, the process temperature needs to be increased to facilitate bonding of the bonding wires 400 to the corresponding pins 112. At this time, the pins 112 of the lead frame 100 are affected by high temperature and bonding pressure. Therefore, it is easy to cause deformation displacement. In the present embodiment, the airtight structure formed by the dielectric film 200 and the lead frame 100 allows the lead frame 100 to be completely vacuumed. Attached to the machine table, the dielectric film 200 can be used as a support for the auxiliary lead frame 100. This ensures that the bonding process of the wafer 300, the bonding wire 400 and the lead frame 100 can be smoothly performed. Moreover, since the dielectric film 200 is located between the wafer 300 and the lead frame 100, the dielectric film 200 does not interfere with the electrical connection between the wafer 300 and the lead frame 100, and the dielectric film 200 is on the wafer 300 and the lead frame. After the 100 electrical connection is completed, it is not necessary to be removed, so the use of the dielectric film 200 can achieve the purpose of simplifying the process and improving the yield.

2A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention. 2B is a cross-sectional view of the quad flat no-lead package structure of FIG. 2A taken along line II-II'. Referring to FIG. 2A and FIG. 2B simultaneously, the quad flat no-lead package structure 20 of the present embodiment is similar to the quad flat no-lead package structure 10 of the previous embodiment, and the main difference between the two is: the embodiment In the quad flat no-lead package structure 20, in addition to having a plurality of pins 112, the leadframe 110 further includes a wafer holder 114.

As shown in FIGS. 2A and 2B, the wafer 300 is disposed corresponding to the wafer holder 114 of the lead frame 110. Here, the wafer holder 114 has a function of, for example, heat dissipation and/or grounding.

3A is a top plan view of a quad flat no-lead package structure in accordance with an embodiment of the present invention. 3B is a cross-sectional view of the quad flat no-lead package structure of FIG. 3A taken along line III-III'. Referring to FIG. 3A and FIG. 3B simultaneously, the quad flat no-lead package structure 30 of the present embodiment is similar to the quad flat no-lead package structure 10 of the previous embodiment. The main difference between the two is: the quad flat of the embodiment. Leadless seal The mounting structure 30 is a quad flat no-lead flip chip package structure.

As shown in FIG. 3A and FIG. 3B , the quad flat no-lead flip chip package structure 30 of the present embodiment includes a lead frame 100 , a dielectric film 200 , a wafer 310 , and an encapsulant 500 . In particular, leadframe 100 can have a plurality of pins 102 from which a plurality of leads 102 extend from below wafer 310 to the edge of encapsulant 500. In detail, as shown in FIG. 3A, the plurality of pins 102 are distributed around the periphery of the wafer 310, the adjacent pins 102 are at least spaced apart from each other by a distance G, and each of the pins 102 is from the wafer 310. The lower portion extends to the edge of the encapsulant 500.

On the other hand, the dielectric film 200 is disposed on the lead frame 100. The dielectric film 200 has a plurality of openings 202, and the openings 202 are respectively located above the corresponding pins 102. In the present embodiment, the opening 202 can be formed by etching or laser removing the dielectric film 200. The distribution of the dielectric film 200 covers the area between the pins 102, and the edge of the dielectric film 200 is, for example, aligned with the edge of the encapsulant 500, and the maximum aperture of each opening 202 of the dielectric film 200 does not exceed each other. The outer contour of the corresponding pin 102, in other words, the opening 202 in the dielectric film 200 can be matched with the pin 102 of the lead frame 100 to form a hermetic structure, so that the lead frame 100 with the surface of the dielectric film 200 attached thereto Can be vacuum absorbed. Here, the lead frame 100 and the dielectric film 200 may constitute a lead frame structure L. As shown in FIG. 3B, the wafer 310 is disposed on the dielectric film 200 such that the dielectric film 200 is located between the wafer 310 and the lead frame 100, and the wafer 310 has an active surface A, and may have a plurality of sides on the active surface A side. The pad 302 is disposed, and the conductive bumps 312 are disposed on the pads 302 of the active surface A. The pads 310 and the leads 102 corresponding to the corresponding openings 202 are electrically connected by the conductive bumps 312.

In this embodiment, the wafer 310 is disposed on the dielectric film 200 with the active surface A facing the dielectric film 200, and the opening 202 of the dielectric film 200 is covered by the wafer 310 for the flip chip bonding process. . Each of the pads 302 on the wafer 310 is electrically connected to the leads 102 exposed by the corresponding openings 202 by the respective conductive bumps 312. Here, the material of the conductive bump 312 is, for example, gold, copper, silver alloy or other suitable conductive material.

It should be noted that since the combination of the dielectric film 200 and the lead frame 100 can constitute an airtight structure, and the dielectric film 200 serves as a support for the auxiliary lead frame 100, the wafer 310, the pad 302 and the lead frame are performed. During the 100 bonding process, the lead frame 100 can be fixed in position by vacuum adsorption, and the displacement of the lead frame 100 during the bonding process can be avoided, thereby improving the precision of bonding the wafer 310 to the lead frame 100. Further, the minimum aperture range of the opening 202 of the dielectric film 200 is to expose the bonding region of the conductive bump 312 and the pin 102, and the maximum aperture range is the upper surface of the entire pin 102 without exceeding the outer contour of the pin 102. (not shown).

In order to protect the wafer 310 and the conductive bumps 312 and to ensure the reliability of the quad flat no-lead package structure 30, the encapsulant 500 covers the leadframe 100, the dielectric film 200, the wafer 310, and the bonding wires 400. As shown in FIG. 3B, the encapsulant 500 can be distributed on both sides of the lead frame 100. In addition to covering the dielectric film 200, the wafer 310, and the bonding wire 400, the encapsulant 500 can be filled in the space S on the other side of the lead frame. In other words, the encapsulant 500 can be filled between any two adjacent pins 102 to wrap all of the pins 102. Of course, the end of the pin 102 will be exposed to the encapsulant 500 to facilitate electrical connection with an external device such as a circuit board.

4A is a top view of a quad flat no-lead package structure in accordance with another embodiment of the present invention. 4B is a cross-sectional view of the quad flat no-lead package structure of FIG. 4A taken along line IV-IV'. Referring to FIG. 4A and FIG. 4B simultaneously, the quad flat no-lead package structure 40 of the present embodiment is similar to the quad flat no-lead package structure 30 of the previous embodiment, and the main difference between the two is: the embodiment In the quad flat no-lead package structure 40, the lead frame 110 includes a wafer holder 114 in addition to the plurality of pins 112.

As shown in FIGS. 4A and 4B, the wafer 310 is disposed corresponding to the wafer holder 114 of the lead frame 100. Here, the wafer holder 114 has a function of, for example, heat dissipation and/or grounding.

In summary, the quad flat no-lead lead frame structure and the quad flat no-lead package structure of the present invention have a dielectric film disposed on the lead of the lead frame and completely cover the pin and the adjacent pin. The spacing, when the wafer, the bonding wire and the lead frame are soldered to a bonding process or the wafer, the bonding pad and the lead frame are subjected to a flip chip bonding process (ie, a bonding process), the lead frame can be fixed by vacuum adsorption, and The dielectric film can assist the support of the leadframe, thereby ensuring that the wire bond or flip chip bonding process can proceed smoothly. Moreover, since the dielectric film is located between the wafer and the lead frame, the use of the dielectric film can achieve the purpose of simplifying the process and improving the yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Quad Flat No-Lead Package Structure

100‧‧‧ lead frame

102‧‧‧ pin

200‧‧‧ dielectric film

202‧‧‧Opening

300‧‧‧ wafer

302‧‧‧ solder pads

400‧‧‧welding line

500‧‧‧Package colloid

600‧‧‧Adhesive layer

I-I’‧‧‧ cut line

L‧‧‧ lead frame structure

S‧‧‧ Space

Claims (10)

A quad flat no-lead package structure comprising: a lead frame comprising a plurality of pins, wherein the pins define a space, and the space is gradually expanded away from an upper surface of the pins; An electric film is disposed on the lead frame, wherein the dielectric film has a plurality of openings, and each of the openings is located above each of the corresponding pins, and the openings and the space are located opposite to the lead frame a side, and are hermetically separated from each other; a wafer disposed on the dielectric film; a plurality of bonding wires, each of the bonding wires being respectively connected between the wafer and a pin exposed by the corresponding opening; And an encapsulant covering the lead frame, the dielectric film, the wafer, and the bonding wires. The quad flat no-lead package structure of claim 1, wherein the pins extend from below the wafer to an edge of the encapsulant. The quad flat no-lead package structure of claim 1, wherein the lead frame further comprises: a wafer holder under the wafer, wherein the pins surround the wafer holder. The quad flat no-lead package structure according to claim 1, wherein the distribution range of the dielectric film covers between the pins. The quad flat no-lead package structure of claim 1, wherein an edge of the dielectric film is aligned with an edge of the encapsulant. The quad flat no-lead package structure as described in claim 1 of the patent application, The maximum aperture of each of the openings does not exceed the outer contour of the corresponding pin. The quad flat no-lead package structure of claim 1, wherein the dielectric film is located between the wafer and the lead frame. A quad flat no-lead flip chip package structure comprising: a lead frame comprising a plurality of pins, wherein the pins define a space, and the space is gradually expanded away from an upper surface of the pins; a dielectric film disposed on the lead frame, wherein the dielectric film has a plurality of openings, and each of the openings is located above a corresponding pin, and the openings and the space are located opposite to the lead frame Sides, and are hermetically separated from each other; a wafer is disposed on the dielectric film, the wafer has an active surface, and a plurality of conductive bumps are disposed on the active surface, and the conductive bumps are respectively connected Between the wafer and a pin exposed by the corresponding opening; and an encapsulant covering the lead frame, the dielectric film, the wafer, and the conductive bumps. The quad flat no-lead flip chip package structure according to claim 8 , wherein the maximum aperture of each of the openings does not exceed the outer contour of the corresponding pin. A quad flat no-lead leadframe structure includes: a leadframe comprising a plurality of pins, the adjacent pins having at least one spacing therebetween, wherein the pins define a space and the space is far away The upper surface of the pins is gradually diverged; and a dielectric film is disposed on the pins and completely covers the pins and the distance between the adjacent pins, wherein the dielectric film An opening having a plurality of corresponding pins, The maximum aperture of each of the openings does not exceed the outer contour of the corresponding pin, and the openings and the space are located on opposite sides of the lead frame and are hermetically separated from each other.