CN101625987B - Fabricating process of a chip package structure - Google Patents
Fabricating process of a chip package structure Download PDFInfo
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- CN101625987B CN101625987B CN 200810214684 CN200810214684A CN101625987B CN 101625987 B CN101625987 B CN 101625987B CN 200810214684 CN200810214684 CN 200810214684 CN 200810214684 A CN200810214684 A CN 200810214684A CN 101625987 B CN101625987 B CN 101625987B
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- 238000000576 coating method Methods 0.000 claims description 170
- 239000011248 coating agent Substances 0.000 claims description 169
- 238000004806 packaging method and process Methods 0.000 claims description 70
- 238000012545 processing Methods 0.000 claims description 27
- 230000009477 glass transition Effects 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 abstract 6
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- 229910052802 copper Inorganic materials 0.000 description 6
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- 229920001187 thermosetting polymer Polymers 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- LOUPRKONTZGTKE-WZBLMQSHSA-N Quinine Chemical compound C([C@H]([C@H](C1)C=C)C2)C[N@@]1[C@@H]2[C@H](O)C1=CC=NC2=CC=C(OC)C=C21 LOUPRKONTZGTKE-WZBLMQSHSA-N 0.000 description 2
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- 238000013461 design Methods 0.000 description 2
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- LOUPRKONTZGTKE-UHFFFAOYSA-N cinchonine Natural products C1C(C(C2)C=C)CCN2C1C(O)C1=CC=NC2=CC=C(OC)C=C21 LOUPRKONTZGTKE-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
Description
Technical field
The invention relates to a kind of chip-packaging structure processing procedure, and particularly relevant for the chip-packaging structure processing procedure of a kind of utilization at least two B rank adhesion coatings with the combination base material.
Background technology
Along with increasing of the I/O contact of integrated circuit, it is more and more diversified that chip encapsulation technology becomes.This is owing to the fact of covering crystalline substance (Flip Chip) interconnection technique minimization Chip Packaging size and reducing signal transmission path etc.The most frequently used chip-packaging structure that brilliant interconnection technique is covered in application comprises such as covering geode grid array (Flip Chip Ball Grid Array) and covering brilliant stitch grid array chip-packaging structures such as (Flip Chip Pin Grid Array).
Cover brilliant interconnection technique and adopt a kind of like this method,, and on these weld pads, form a plurality of projections respectively, come the delimited area array promptly through on the active surface of chip, a plurality of weld pads being set.Then, chip is overturned, with the soldering projection that connects chip respectively be arranged on such as a plurality of contact mats on the carrier of circuit substrate.Therefore, chip electrically connects and is mechanically attached to carrier through projection.In addition, chip can be electrically connected to external electronic through the internal circuit of carrier.Usually, projection has some types, for example solder projection, golden projection, copper bump, conducting polymer projection, macromolecular convex etc.
Fig. 1 is the generalized section with chip-packaging structure of macromolecular convex.Please refer to Fig. 1, chip-packaging structure 100 comprises first substrate 110, a plurality of macromolecular convex 120, chip 130 and scolder 140.First substrate 110 has surperficial 110a, and surperficial 110a is provided with a plurality of contact mats 112.Chip 130 has active surperficial 130a, and active surperficial 130a is provided with a plurality of weld pads 132.The macromolecular convex of being processed by the macromolecular material with conductive characteristic 120 is separately positioned between contact mat 112 and the weld pad 132, to electrically connect substrate 110 and chip 130.Because macromolecular convex 120 also is not attached to contact mat 112, therefore need scolder 140 that macromolecular convex 120 is fixed on the substrate 110.The surfaces A of scolder 140 is attached to contact mat 112, and its surperficial B is attached to macromolecular convex 120.Therefore, when the time spent of doing that chip-packaging structure receives external force or thermal stress (not shown), scolder 140 meetings are by disengaging on the contact mat 112, and macromolecular convex 120 will no longer be electrically connected to contact mat 112.Apparently, the reliability of chip-packaging structure 100 is lower.
Summary of the invention
The present invention provides a kind of reliability to obtain the chip-packaging structure processing procedure that promotes.
The present invention proposes a kind of chip-packaging structure processing procedure.At first, provide one have a plurality of first weld pads first substrate and have second substrate of a plurality of second weld pads, and on these first weld pads of first substrate, form a plurality of projections.Form one first second order adhesion coating on first substrate or on second substrate and with its B rankization to form one the one B rank adhesion coating.On a B rank adhesion coating, form one second second order adhesion coating and with its B rankization to form one the 2nd B rank adhesion coating.Then, see through a B rank adhesion coating and combine first substrate and second substrate with the 2nd B rank adhesion coating, a projection electrically connects with the second corresponding weld pad so that each first weld pad sees through wherein respectively.The method of the B rankization first second order adhesion coating and the second second order adhesion coating comprises heating (hot curing) or ultraviolet curing.
In one embodiment of this invention, above-mentioned first substrate and second substrate are all chip.
In one embodiment of this invention, the first above-mentioned substrate is that a carrier and second substrate are a chip.
In one embodiment of this invention, the first above-mentioned substrate is that a chip and second substrate are a carrier.
In one embodiment of this invention, above-mentioned projection is tie lines projection that is formed by the routing processing procedure or the plated bumps that is formed by electroplating process.These projections are golden projection, copper bump or solder bump.
In one embodiment of this invention, the method that forms a B rank adhesion coating is included on these first weld pads or forms a plurality of first second orders adhesion pieces on these second weld pads, and these first second orders adhesion pieces of B rankization are to form a plurality of B rank pieces of adhering.
In one embodiment of this invention, the method that forms the 2nd B rank adhesion coating is included in and forms a plurality of second second order adhesion pieces on these B rank adhesion pieces, and these second second order adhesion pieces of B rankization are to form a plurality of the 2nd B rank adhesion pieces.
In one embodiment of this invention, an above-mentioned B rank adhesion coating fully covers first substrate and the 2nd B rank adhesion coating comprises a plurality of the 2nd B rank adhesion pieces.In addition, the glass transition temperature (Tg) of a B rank adhesion coating for example is the glass transition temperature that is higher than, is equal to or less than the 2nd B rank adhesion coating.
In chip-packaging structure processing procedure of the present invention, a B rank adhesion coating and the 2nd B rank adhesion coating all are formed on first substrate or second substrate, so that the projection that is arranged between first substrate and second substrate can be coated.When an external force or thermal stress acted on chip-packaging structure, a B rank adhesion coating and the 2nd B rank adhesion coating can provide support respectively and protect, and prevented that projection from damaging, so that the reliability of chip-packaging structure obtains further to improve.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 is the generalized section with chip-packaging structure of macromolecular convex.
Fig. 2 A and Fig. 2 B are the generalized section of the chip-packaging structure of one embodiment of the invention.
Fig. 3 A to Fig. 3 D is the generalized section of the chip-packaging structure of another embodiment of the present invention.
Fig. 4 is the generalized section of the stack chip packaging structure of one embodiment of the invention.
Fig. 5 to Fig. 7 is the generalized section of the stack chip packaging structure of a plurality of embodiment of the present invention.
Fig. 8 A to Fig. 8 F is a kind of generalized section of chip-packaging structure processing procedure.
Fig. 9 A to Fig. 9 C is the generalized section of the chip-packaging structure of a plurality of embodiment of the present invention.
Figure 10 is the generalized section of the stack chip packaging structure of another embodiment of the present invention.
Figure 11 A to Figure 11 C is the generalized section of the stack chip packaging structure 400 ' processing procedure of Figure 10.
The main element symbol description:
100: chip-packaging structure
110: the first substrates
110a: surface
112: contact mat
120: macromolecular convex
130: chip
130a: active surface
132: weld pad
140: scolder
200: chip-packaging structure
200 ': chip-packaging structure
200 ": chip-packaging structure
200 " ': chip-packaging structure
210: the first substrates
210 ': the first chip
212: the first weld pads
214: the line weld pad
220: the second substrates
220 ': the second chip
222: the second weld pads
230: projection
230a: tie lines projection
230b: plated bumps
240: sticky material
240a: a B rank adhesion coating
240a ': B rank adhesion piece
240b: the 2nd B rank adhesion coating
240b ': the 2nd B rank adhesion piece
310: substrate
312: weld pad
320: projection
320a: tie lines projection
330: sticky material
330a: thermosetting adhesion piece
340: adhesion piece with B rank characteristic
400: stack chip packaging structure
400 ': stack chip packaging structure
400b: stack chip packaging structure
400c: stack chip packaging structure
410: carrier
420: bonding wire
430: adhesion coating
A: surface
B: surface
D1: size
D2: size
S1: surface
S2: surface
X1: the first second order adhesion coating
X2: the second second order adhesion coating
Embodiment
Fig. 2 A and Fig. 2 B are the generalized section of the chip-packaging structure of one embodiment of the invention.Please refer to Fig. 2 A and Fig. 2 B, chip-packaging structure 200 of the present invention comprises one first substrate 210, one second substrate 220, a plurality of projection 230a (being illustrated in Fig. 2 A) or 230b (being illustrated in Fig. 2 B), one the one B rank adhesion coating 240a and one the 2nd B rank adhesion coating 240b.First substrate 210 has a plurality of first weld pads 212.Second substrate 220 has the top that a plurality of second weld pads 222 and second substrate 220 are arranged at first substrate 210.Projection 230a, 230b are arranged between first substrate 210 and second substrate 220, and wherein each first weld pad 212 sees through wherein a projection 230a, 230b and corresponding second weld pad, 222 electric connections respectively.The one B rank adhesion coating 240a is adhered on first substrate 210.The 2nd B rank adhesion coating 240b is adhered between a B rank adhesion coating 240a and second substrate 220, and wherein a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b coat projection 230a, 230b.In addition, the composition of a B rank adhesion coating 240a can be equal to the composition of the 2nd B rank adhesion coating 240b in fact.Shown in Fig. 2 A and Fig. 2 B, the surperficial S1 that a B rank adhesion coating 240a is adhered to first substrate 210 goes up and the 2nd B rank adhesion coating 240b is adhered on the surperficial S2 of second substrate 220.It should be noted that; The present invention utilizes a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b to strengthen the adherence between first substrate 210 and second substrate 220; And can provide support respectively and protect, damage to prevent projection, make the reliability of chip-packaging structure to be enhanced.
Shown in Fig. 2 A and Fig. 2 B, in the present embodiment, the thickness of a B rank adhesion coating 240a equals the thickness of the 2nd B rank adhesion coating 240b in fact.Yet based on the actual design demand, the thickness of a B rank adhesion coating 240a also can be different from the thickness of the 2nd B rank adhesion coating 240b.
In the present embodiment, projection is tie lines projection 230a (shown in Fig. 2 A), and tie lines projection 230a can be golden tie lines projection or copper tie lines projection.In another embodiment of the present invention, projection can be plated bumps 230b (shown in Fig. 2 B).Each tie lines projection 230a or each plated bumps 230b are coated by an adhesion piece 240a '.Plated bumps 230b can be golden projection, copper bump, solder bump or other conductive projections.
According to present embodiment; The one B rank adhesion coating 240a comprises a plurality of B rank adhesion piece 240a '; And the 2nd B rank adhesion coating 240b comprises a plurality of the 2nd B rank adhesion piece 240b ', and wherein B rank adhesion piece 240a ' the surperficial S1 that is adhered to first substrate 210 goes up and the 2nd B rank adhesion piece 240b ' is adhered on the surperficial S2 of second substrate 210.In the present embodiment, 240a ' is conduction or non-conductive when the 2nd B rank adhesion piece, and B rank adhesion piece 240a ' is conduction or non-conductive.Because B rank adhesions piece 240a ' is each other for being electrically insulated and piece 240b ' is adhered each other for being electrically insulated in the 2nd B rank; Even, still can prevent the short circuit between projection 230a, the 230b so B rank adhesion piece 240a ' is all conduction with the 2nd B rank adhesion piece 240b '.
In the present embodiment, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b can be 8008 or the 8008HT of ABLESTIK, and its glass transition temperature is approximately between 80 degree Celsius and 300 degree Celsius.In addition; The one B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b can be ABLESTIK 6200,6201,6202C or HITACHI Chemical CO.; Ltd. the SA-200-6 that provides, SA-200-10, and its glass transition temperature is approximately between negative 40 degree Celsius and 150 degree Celsius.The glass transition temperature of the one B rank adhesion coating 240a can greater than, be equal to or less than the glass transition temperature of the 2nd B rank adhesion coating 240b.In addition, for example can some conducting particless (like silver particles, copper particle and gold particle) be doped among a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b to increase conductivity.
Fig. 3 A to Fig. 3 D is the generalized section of the chip-packaging structure of another embodiment of the present invention.Please refer to Fig. 3 A and Fig. 3 B, except a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b fully fill up the space between the projection 230, the chip-packaging structure 200 ' of present embodiment is similar with the chip-packaging structure 200 of Fig. 2 A and Fig. 2 B.Specifically, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b are all non-conductive to prevent the short circuit between the projection 230.
Please refer to Fig. 3 C, except the dimension D of the dimension D 1 of a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b 2 is different, the chip-packaging structure 200 of present embodiment " be similar with the chip-packaging structure 200 ' of Fig. 3 A.Shown in Fig. 3 C, the dimension D 1 of a B rank adhesion coating 240a is less than the dimension D 2 of the 2nd B rank adhesion coating 240b, so that outside the area of first substrate, 210 parts can not cover and be exposed to by a B rank adhesion coating 240a.Except the shared area of projection 230, the 2nd B rank adhesion coating 240b fully covers the surperficial S2 of second substrate 220, and a B rank adhesion coating 240a makes outside the surperficial S1 (zone on every side) of first substrate 210 is exposed to.
Please refer to Fig. 3 D, except a B rank adhesion coating 240a comprises a plurality of B rank adhesion piece 240a ', the chip-packaging structure 200 of present embodiment " ' with the chip-packaging structure 200 of Fig. 3 C " be similar.
Fig. 4 is the generalized section of the stack chip packaging structure of one embodiment of the invention.Please refer to Fig. 4, stack chip packaging structure 400 comprises a carrier 410, first chip 210 ', second chip 220 ', a plurality of projection 230, one the one B rank adhesion coating 240a, one the 2nd B rank adhesion coating 240b and many bonding wires 420.The arrangement mode of first chip 210, second chip 220, projection 230 and sticky material 240 can identical with aforesaid embodiment (shown in Fig. 2 A and Fig. 2 B).In the present embodiment, first chip 210 ' combines with carrier 410 and sees through bonding wire 420 to electrically connect with carrier 410 by an adhesion coating 430 (like epoxy resin, elargol, sticking brilliant glued membrane (DAF) or the like).Specifically, first chip 210 ' has the line weld pad 214 that electrically connects through bonding wire 420 and carrier 410.
Fig. 5 to Fig. 7 is the generalized section of the stack chip packaging structure of a plurality of embodiment of the present invention.Please refer to Fig. 5, stack chip packaging structure 400a comprises a carrier 410, one first chip 210 ', one second chip 220 ', a plurality of projection 230, one the one B rank adhesion coating 240a, one the 2nd B rank adhesion coating 240b and many bonding wires 420.The arrangement mode with Fig. 3 A or Fig. 3 B is identical in fact for the arrangement mode of first chip 210 ', second chip 220 ', projection 230, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b.First chip 210 ' combines with carrier 410 and sees through bonding wire 420 to electrically connect with carrier 410 by an adhesion coating 430 (like epoxy resin, elargol, sticking brilliant glued membrane or the like).Specifically, first chip 210 ' has the line weld pad 214 that electrically connects through bonding wire 420 and carrier 410.An end that is connected in the bonding wire 420 of line weld pad 214 is coated by a B rank adhesion coating 240a.Distance (stand-off) between first chip 210 ' and second chip 220 ' is kept by a B rank adhesion coating 240a and the 2nd B rank one of them person of adhesion coating 240b, so that bonding wire 420 can be avoided by protection damaging.
Please refer to Fig. 6 and Fig. 7; In stack chip packaging structure 400b and 400c, the arrangement mode of first chip 210 ', second chip 220 ', projection 230, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b also can be same or similar with the previous embodiment of Fig. 3 C and Fig. 3 D.Like Fig. 6 and shown in Figure 7; Outside the line weld pad 214 of first chip 210 ' can not covered and is exposed to by B rank adhesion coating 240a (as shown in Figure 6) or B rank adhesion piece 240a ' (as shown in Figure 7), so that bonding wire 420 can not coated by B rank adhesion coating 240a (as shown in Figure 6) or B rank adhesion piece 240a ' (as shown in Figure 7).
The processing procedure of the chip-packaging structure 200 of following key diagram 2A.The processing procedure of chip-packaging structure 200 ' that it should be noted that Fig. 3 A and Fig. 3 B is similar in appearance to the processing procedure that in Fig. 8 A to Fig. 8 D, is disclosed.Therefore, omission is relevant for the explanation of the processing procedure of the chip-packaging structure 200 ' shown in Fig. 3 A and Fig. 3 B.
The generalized section of Fig. 8 A to Fig. 8 F chip-packaging structure processing procedure.Please refer to Fig. 8 A, provide one have a plurality of first weld pads 212 first substrate 210 and have second substrate 220 of a plurality of second weld pads 222, and on first weld pad 212 of first substrate 210, form a plurality of projections 230.In the present embodiment, projection 230 is the tie lines projection that formed by the routing processing procedure and similar in appearance to the projection 230a shown in Fig. 2 A.In another embodiment, projection 230 is the plated bumps that formed by electroplating process and similar in appearance to the projection 230b shown in Fig. 2 B.
In the present embodiment, first substrate 210 is a carrier, and like a printed circuit board (PCB), and second substrate 220 is a chip, and wherein printed circuit board (PCB) can be FR4, FR5, BT, PI circuit substrate.In another embodiment of the present invention, first substrate 210 can be a carrier, and second substrate 220 can be a chip.In another embodiment of the present invention, first substrate 210 can be a chip, and second substrate 220 can be a carrier.
Please refer to Fig. 8 B and Fig. 8 C, on second substrate 220, form one first second order adhesion coating X1 and its B rankization (like precuring or partly solidified) are comprised the adhere B rank adhesion coating 240a of piece 240a ' of a plurality of B rank to form one.
Please refer to Fig. 8 D and Fig. 8 E, go up at a B rank adhesion coating 240a (B rank adhesion piece 240a ') and form one second second order adhesion coating X2 and its B rankization are comprised adhere the 2nd B rank adhesion coating 240b of piece 240b ' of a plurality of the 2nd B rank to form one.Specifically; Because the first second order adhesion coating X1 and the second second order adhesion coating X2 are formed by the thermosetting sticky material manufacturing with second order (A rank and B rank) character, so a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b formation after the first second order adhesion coating X1 and the second second order adhesion coating X2 are by the B rankization.In the present embodiment, the hot curing sticky material that has second order character can be policapram, gathers quinine, benzocyclobutene or like that.Specifically, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b can be 8008 or the 8008HT of ABLESTIK, and its glass transition temperature is approximately between 80 degree Celsius and 300 degree Celsius.In addition; The one B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b can be ABLESTIK 6200,6201,6202C or HITACHIChemical CO.; Ltd. the SA-200-6 that provides, SA-200-10, and its glass transition temperature is approximately between negative 40 degree Celsius and 150 degree Celsius.The glass transition temperature of the one B rank adhesion coating 240a is preferably the glass transition temperature that is higher than, is equal to or less than the 2nd B rank adhesion coating 240b.In addition, for example can some conducting particless (like silver particles, copper particle and gold particle) be doped among a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b to increase conductivity.In addition, the thermosetting sticky material with second order character can be conduction or non-conductive, and it can be formed by screen printing, brushing, spraying, spin coating or dipping.In the step shown in Fig. 8 D and Fig. 8 E, the thermosetting sticky material with second order character can be liquid state or colloid and is dispersed on second substrate 220 being easy to.The present invention does not limit the type of thermosetting sticky material.
Please refer to Fig. 8 F; After forming a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b; First substrate 210 sees through the 2nd B rank adhesion coating 240b with second substrate 220 and combines, and a projection 230 electrically connects with the second corresponding weld pad 222 so that each first weld pad 212 sees through wherein respectively.Specifically, the 2nd B rank adhesion coating 240b is borrowing a B rank adhesion coating 240a to combine with the surperficial S1 of first substrate 210 with solidifying again of the 2nd B rank adhesion coating 240b.After a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b full solidification, if necessity is then carried out a back program curing.
In order to ensure the electric connection between first substrate 210 and second substrate 220; Should control the gross thickness of thickness and the 2nd B rank adhesion coating 240b of a B rank adhesion coating 240a modestly, so that projection 230 can pass a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b and be connected in second weld pad 222 of second substrate 220.In the present embodiment, the thickness of a B rank adhesion coating 240a equals the thickness of the 2nd B rank adhesion coating 240b in fact.Yet based on the actual design demand, the thickness of a B rank adhesion coating 240a also can be different from the thickness of the 2nd B rank adhesion coating 240b.
According to present embodiment, the method that forms a B rank adhesion coating 240a is included in and forms a plurality of first second orders adhesion pieces and B rankization first second order adhesion piece on first weld pad 212 or ground two weld pads 222 to form a plurality of B rank adhesion piece 240a '.In addition, the method that forms the 2nd B rank adhesion coating 240b is included in B rank adhesion piece 240a ' and goes up and form a plurality of second second orders adhesion pieces and B rankization second second order adhesion piece to form a plurality of the 2nd B rank adhesion piece 240b '.
The present invention does not limit the configuration mode of a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b, and the configuration mode shown in Fig. 8 A to Fig. 8 F only is in order to explanation.Below cooperate the configuration mode that illustrates other B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b.
Fig. 9 A to Fig. 9 C is the generalized section of the chip-packaging structure of a plurality of embodiment of the present invention.Please refer to Fig. 9 A; In one embodiment of this invention; The one B rank adhesion coating 240a forms and is covered on the surperficial S2 of second substrate 220, and comprises that the 2nd B rank adhesion coating 240b of a plurality of the 2nd B rank adhesion piece 240b ' is formed at a B rank adhesion coating 240a upward (shown in Fig. 9 A).In another embodiment shown in Fig. 9 B; A B rank adhesion coating 240a who comprises B rank adhesion piece 240a ' is formed on the surperficial S1 of first substrate 210, and comprises that the 2nd B rank adhesion coating 240b of the 2nd B rank adhesion piece 240b ' is formed on the B rank adhesion piece 240a '.In the another embodiment shown in Fig. 9 C, a B rank adhesion coating 240a forms and is covered in fully on the surperficial S1 of first substrate 210, and comprises that the 2nd B rank adhesion coating 240b of the 2nd B rank adhesion piece 240b ' is formed on the B rank adhesion piece 240a '.
Figure 10 is the generalized section of the stack chip packaging structure of another embodiment of the present invention.The stack chip packaging structure of Figure 10 comprises the chip-packaging structure 200 ' of Fig. 3 A or Fig. 3 B.Please refer to Figure 10; In stack chip packaging structure 400 '; The non-active surface of second substrate 220 (inactive surface) sees through an adhesion coating 430 (like epoxy resin, elargol, sticking brilliant glued membrane (DAF) or the like) and combines with carrier 410, and bonding wire 420 is electrically connected between line weld pad 224 and the carrier 410.Specifically, when the chip-packaging structure 200 ' of Fig. 3 A or Fig. 3 B combined with carrier 410 through adhesion coating 430, each bonding wire 420 was coated by a B rank adhesion coating 240a ' near an end of line weld pad 224.In addition; The one B rank adhesion coating 240a with under the situation that bonding wire 420 contacts be not arranged on the 2nd B rank adhesion coating 240b; So that bonding wire 420 in the cohesive process of a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b, is protected by the 2nd B rank adhesion coating 240b.The details of stack chip packaging structure 400 ' processing procedure below will be described.
Figure 11 A to Figure 11 C is the generalized section of the stack chip packaging structure 400 ' processing procedure of Figure 10.Please refer to Figure 11 A, a carrier 410 is provided, second substrate 220 that then will have a plurality of second weld pads 222 and a plurality of line weld pads 224 sees through an adhesion coating and is incorporated into carrier 410.Form many bonding wires 420 then to electrically connect line weld pad 224 and carrier 410.
Please refer to Figure 11 B and Figure 11 C, after forming bonding wire 420, provide one have a plurality of first weld pads 212 first substrate 210 and projection 230.Then, on the surperficial S1 of first substrate 210, one after the other form one the one B rank adhesion coating 240a and one the 2nd B rank adhesion coating 240b.At last, first substrate 210 is pressed on second substrate 220, so that be electrically connected at second weld pad 222 by the projection 230 of a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b coating.It should be noted that because the 2nd B rank adhesion coating 240b has enough flexibilities, so bonding wire 420 can pass the 2nd B rank adhesion coating 240b.Among cohesive process (combining between first substrate 210 and second substrate 220) or afterwards, a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b see through heat or ultraviolet ray is solidified again.At a B rank adhesion coating 240a with after the 2nd B rank adhesion coating 240b combines, if necessity is then carried out a back program curing.
Shown in Figure 11 B and Figure 11 C, a B rank adhesion coating 240a, the 2nd B rank adhesion coating 240b and projection 230 all are formed on the surperficial S1 of first substrate 210.In another embodiment of the present invention, when the surperficial S1 that is formed at first substrate 210 as a B rank adhesion coating 240a and the 2nd B rank adhesion coating 240b went up, projection 230 can be formed on second weld pad 222.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little modification and perfect, so protection scope of the present invention is when being as the criterion with what claims defined.
Claims (10)
1. chip-packaging structure processing procedure comprises:
Provide one have a plurality of first weld pads first substrate;
Provide one have a plurality of second weld pads second substrate;
On this first weld pad that this first substrate has, form a plurality of projections;
In forming one first second order adhesion coating on this first substrate or on this second substrate;
This first second order adhesion coating of B rankization is to form one the one B rank adhesion coating;
On a B rank adhesion coating, form one second second order adhesion coating;
This second second order adhesion coating of B rankization is to form one the 2nd B rank adhesion coating; And
See through a B rank adhesion coating and combine this first substrate and this second substrate with the 2nd B rank adhesion coating, a projection electrically connects with the second corresponding weld pad so that each those first weld pad sees through wherein respectively,
Wherein the 2nd B rank adhesion coating is to combine this first substrate and this second substrate to be formed on the B rank adhesion coating before.
2. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, this first substrate and this second substrate are all chip.
3. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, this first substrate is that a carrier and this second substrate are a chip.
4. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, this first substrate is that a chip and this second substrate are a carrier.
5. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, this projection is tie lines projection that is formed by wire bonder or the plated bumps that is formed by electroplating process.
6. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, the method that forms a B rank adhesion coating comprises:
On the surface of this first substrate or this second substrate, form a plurality of first second order adhesion pieces; And
Those first second order adhesion pieces of B rankization are to form a plurality of B rank adhesion pieces.
7. chip-packaging structure processing procedure as claimed in claim 6 is characterized in that, the method that forms the 2nd B rank adhesion coating comprises:
On those B rank adhesion pieces, form a plurality of second second order adhesion pieces; And
Those second second order adhesion pieces of B rankization are to form a plurality of the 2nd B rank adhesion pieces.
8. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, a B rank adhesion coating fully covers this first substrate, and the 2nd B rank adhesion coating comprises a plurality of the 2nd B rank adhesion pieces.
9. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, the glass transition temperature of a B rank adhesion coating is higher than or equals the glass transition temperature of the 2nd B rank adhesion coating.
10. chip-packaging structure processing procedure as claimed in claim 1 is characterized in that, the method for this first second order adhesion coating of B rankization and this second second order adhesion coating comprises and being heating and curing or ultraviolet curing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/169,132 | 2008-07-08 | ||
| US12/169,132 US7960214B2 (en) | 2005-09-22 | 2008-07-08 | Chip package |
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| CN101625987A CN101625987A (en) | 2010-01-13 |
| CN101625987B true CN101625987B (en) | 2012-02-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168972B1 (en) * | 1998-12-22 | 2001-01-02 | Fujitsu Limited | Flip chip pre-assembly underfill process |
| US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
| CN1581452A (en) * | 2004-05-20 | 2005-02-16 | 威盛电子股份有限公司 | Crystal-cladded package preparing process |
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2008
- 2008-08-29 CN CN 200810214684 patent/CN101625987B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168972B1 (en) * | 1998-12-22 | 2001-01-02 | Fujitsu Limited | Flip chip pre-assembly underfill process |
| US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
| CN1581452A (en) * | 2004-05-20 | 2005-02-16 | 威盛电子股份有限公司 | Crystal-cladded package preparing process |
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| CN101625987A (en) | 2010-01-13 |
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