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CN101471329B - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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CN101471329B
CN101471329B CN2007101256636A CN200710125663A CN101471329B CN 101471329 B CN101471329 B CN 101471329B CN 2007101256636 A CN2007101256636 A CN 2007101256636A CN 200710125663 A CN200710125663 A CN 200710125663A CN 101471329 B CN101471329 B CN 101471329B
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package part
semiconductor package
carbon nano
semiconductor
tube
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CN101471329A (zh
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陈文华
冯正和
庄品洋
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Abstract

一种半导体封装件，其包括：一基板，且该基板的第一表面设置有多个导电迹线；至少一半导体预封装件设置于该基板上，该半导体预封装件与所述多个导电迹线设置于该基板上的同一表面，且与该多个导电迹线电连接；至少一电磁屏蔽层设置于所述至少一半导体预封装件上；一保护层覆盖于该至少一电磁屏蔽层上，其中，所述的电磁屏蔽层包括一碳纳米管薄膜结构。

Description

半导体封装件
技术领域
本发明涉及一种半导体封装件，尤其涉及一基于碳纳米管的半导体封装件。
背景技术
随着电子工业的进步与数字时代的到来，消费者对于电子产品的功能要求也日渐提高。因此，如何提高半导体制造与集成电路设计的技术，制造功能更强大的高频芯片，已成为目前研究的重要课题。对于采用高频芯片的半导体封装件而言，其运行过程中会产生极为严重的电磁波问题(请参见，Application of a Model-free Algorithm for the Packing Irregular Shaped Objectsin Semiconductor Manufacture，International Conference on Robtics &Automation，P1545-1550，(2000))。这是由于高频芯片运算与传输时产生的很强的电磁波往往会通过半导体封装件传到外界，造成周围电子装置的电磁干扰(EMI，Electro Magnetic Interference)问题。同时，也会降低半导体封装件的电性品质与散热效能，成为采用高频芯片的半导体封装件的一大问题。
请参阅图1，现有技术提供一种半导体封装件10，其包括：一基板102，且该基板102上设置有多个导电迹线(图中未显示)以及与该导电迹线相连的多个引脚116；一半导体芯片104设置于该基板102上，且该半导体芯片104包括多个焊垫(图中未显示)设置于该半导体芯片104上；多个焊线106，且该多个焊线106将半导体芯片104的焊垫与基板102上对应的导电迹线电性连接；一封装胶层108包覆于该半导体芯片104及多个焊线106上；一电磁屏蔽层110设置于封装胶层108外，并将整个封装胶层108覆盖；一保护层112设置于电磁屏蔽层110外，并将整个电磁屏蔽层110覆盖。将该电磁屏蔽层110接地，通过该电磁屏蔽层110可以隔绝电磁波，从而阻止半导体芯片104运行时产生的电磁波传到外界，起到电磁屏蔽功效。
传统的半导体封装件10中，电磁屏蔽层110通常为一金属层(如：铜层、铁层)、合金层(如：镍铁合金、铁钴合金等)或填充有多孔性金属粒子的有机材料层。该有机材料可以是与所述封装胶层108的材料相同或不同的树脂材料。
然而，采用金属或合金制备的电磁屏蔽层110虽然可以阻止半导体芯片104运行时产生的电磁波传到外界，但是，无法吸收电磁波。所以，会出现电磁波在半导体封装件10内不断反射的现象。这些电磁波不但会影响半导体芯片104与焊线106的电性传输品质，而且随着电磁波能量的衰减，会在半导体封装件10内产生大量的热能，从而增加了该半导体封装件10的散热负担。另外，采用金属或合金层作为电磁屏蔽层110制备半导体封装件10，重量较沉，使用不便。
采用填充有多孔性金属粒子的有机材料制备的半导体封装件10的电磁屏蔽层110通常采用印刷技术制备形成，所以受制备工艺限制，其厚度不能太薄。另外，采用填充有多孔性金属粒子的有机材料制备的电磁屏蔽层110，导电性与散热性能较差，而且重量较沉，使用不便。
有鉴于此，确有必要提供一种能够有效吸收电磁波，且散热性能优良，重量轻，使用方便的半导体封装件。
发明内容
一种半导体封装件，其包括：一基板，且该基板的第一表面设置有多个导电迹线；至少一半导体预封装件设置于该基板上，该半导体预封装件与所述多个导电迹线设置于该基板上的同一表面，且与该多个导电迹线电连接；至少一电磁屏蔽层设置于所述至少一半导体预封装件上；一保护层覆盖于该至少一电磁屏蔽层上，其中，所述的电磁屏蔽层包括一碳纳米管薄膜结构。
相交于现有技术，本技术方案提供的半导体封装件采用碳纳米管薄膜结构制备电磁屏蔽层，能够有效吸收电磁波，且导电性与散热性能优良，重量轻，使用方便。
附图说明
图1为现有技术中的半导体封装件的结构示意图。
图2为本技术方案第一实施例的半导体封装件的结构示意图。
图3为本技术方案第二实施例的半导体封装件的结构示意图。
图4为本技术方案第三实施例的半导体封装件的结构示意图。
具体实施方式
下面将结合附图对本技术方案作进一步的详细说明。
请参阅图2，本技术方案第一实施例提供一种半导体封装件20，其包括：一基板202，且该基板202上设置有多个导电迹线(图中未显示)以及与该导电迹线相连的多个引脚216；一半导体预封装件218设置于该基板202上；一电磁屏蔽层210设置于半导体预封装件218上，并将整个半导体预封装件218覆盖；一保护层212覆盖于该至少一电磁屏蔽层210上。其中，所述半导体预封装件218包括：一半导体芯片204，且该半导体芯片204包括多个焊垫(图中未显示)设置于该半导体芯片204上；多个焊线206，且该多个焊线206将半导体芯片204的焊垫与基板202上对应的导电迹线(图中未显示)电性连接；一封装胶层208包覆于该半导体芯片204及多个焊线206上。
所述基板202为一覆铜层压板，其厚度与大小不限，可以根据实际情况选择。在基板202的第一表面形成有按照预定规律排列的多个导电迹线。在基板202上与第一表面相对的第二表面设置有多个引脚216。所述导电迹线通过引脚216将上述半导体芯片204与外电路连接。
所述半导体芯片204可以为任意半导体芯片，如：RAM、DRAM等的存储器件或其它类型的集成电路(IC)。该半导体芯片204还可以是功率晶体管的分立器件。所述半导体芯片204的尺寸大小不限，可以根据实际情况选择。
所述焊线206为一般的导线，如：金属丝等。本实施例中优选为金丝或铂丝。
所述封装胶层208的材料为一树脂材料，如：环氧树脂。该封装胶层208的厚度不限，可以根据实际情况制备。该封装胶层208采用印刷技术形成于基板202上，并将该半导体芯片204及多个焊线206包覆。
所述电磁屏蔽层210包括一碳纳米管薄膜结构。所述碳纳米管薄膜结构可以为任意形式的碳纳米管薄膜构成的碳纳米管薄膜结构。本实施例中，碳纳米管薄膜结构包括一碳纳米管层或至少两个平行且重叠铺设的碳纳米管层，且相邻两个碳纳米管层之间通过范德华力紧密连接。每个碳纳米管层包括一碳纳米管薄膜或至少两个平行且无间隙排列的碳纳米管薄膜，且相邻两个碳纳米管薄膜之间通过范德华力紧密连接。碳纳米管薄膜结构的面积与厚度不限，可根据实际需求制备。可以理解，通过将多个碳纳米管薄膜平行且无间隙铺设或/和重叠铺设，可以制备不同面积与厚度的碳纳米管薄膜结构。可以理解，碳纳米管薄膜结构的面积取决于每层碳纳米管层中碳纳米管薄膜的个数，而厚度取决于碳纳米管薄膜结构中碳纳米管层的层数。所述每个碳纳米管薄膜包括多个首尾相连且择优取向排列的碳纳米管束，该碳纳米管束之间通过范德华力紧密连接，且每个碳纳米管束的长度基本相同。所述每个碳纳米管束包括多个具有相同长度且相互平行排列的碳纳米管。所述每个碳纳米管薄膜中的碳纳米管具有相同的排列方向。可以理解，在由多个碳纳米管层组成的碳纳米管薄膜结构中，相邻两个碳纳米管层中的碳纳米管的排列方向有一夹角α，且0°≤α≤90°，相邻两个碳纳米管层中的碳纳米管束之间存在多个微孔结构，该微孔结构均匀且规则分布于碳纳米管薄膜结构中，其中微孔直径为1纳米～0.5微米。
所述碳纳米管薄膜的厚度为0.01～100微米。该碳纳米管薄膜中的碳纳米管为单壁碳纳米管、双壁碳纳米管及多壁碳纳米管中的一种。该碳纳米管的长度为200～400微米。当该碳纳米管薄膜中的碳纳米管为单壁碳纳米管时，该单壁碳纳米管的直径为0.5纳米～50纳米。当该碳纳米管薄膜中的碳纳米管为双壁碳纳米管时，该双壁碳纳米管的直径为1.0纳米～50纳米。当该碳纳米管薄膜中的碳纳米管为多壁碳纳米管时，该多壁碳纳米管的直径为1.5纳米～50纳米。采用碳纳米管薄膜结构制备电磁屏蔽层，能够有效吸收电磁波，且导电性与散热性能优良。
可以理解，本实施例中提供的电磁屏蔽层210，还可以进一步包括设置于所述碳纳米管薄膜结构中的金属填充颗粒220。所述金属填充颗粒220均匀分散于碳纳米管薄膜结构中的微孔中或夹在相邻两个碳纳米管层之间。该金属填充颗粒220包括一多孔性金属颗粒或合金颗粒，其材料为铜、铁、镍、钴中的一种或几种的合金。所述金属填充颗粒220的平均粒径小于1微米。本实施例中，金属填充颗粒220优选为铁颗粒。由于该金属填充颗粒220可以有效吸收电磁波，所以会提高电磁屏蔽层210对电磁波的屏蔽效果。
所述保护层212的材料可以是与封装胶层208材料相同或不同的树脂材料，或者金属材料等其他保护材料。所述保护层212可以保护电磁屏蔽层210不被外力破坏。
可以理解，本实施例中，还可以进一步包括一散热片214设置于保护层212上，用来将电磁屏蔽层210中转换的热量快速传导出去。所述散热片214的材料为金属或合金，本实施例中，散热片214优选为一铜片或铝片。
可以理解，本实施例中，还可以进一步将多个上述半导体预封装件218封装在同一基板202上，且每个半导体预封装件218外包覆一电磁屏蔽层210，每个电磁屏蔽层210外包覆一保护层212，每个保护层212上设置一散热片214。
请参阅图3，本技术方案第二实施例提供一种半导体封装件30，其包括：一基板302，且该基板302上设置有多个导电迹线(图中未显示)以及与该导电迹线相连的多个引脚316；至少两个半导体预封装件318设置于该基板302上，且相邻两个半导体预封装件318之间可以填充有封装胶；一电磁屏蔽层310设置于所述至少两个半导体预封装件318上，并将整个半导体预封装件318覆盖；一保护层312覆盖于该至少一电磁屏蔽层310上。所述每个半导体预封装件318包括：一半导体芯片304，且该半导体芯片304包括多个焊垫(图中未显示)设置于该半导体芯片304上；多个焊线306，且该多个焊线306将半导体芯片304的焊垫与基板302上对应的导电迹线电性连接；一封装胶层308包覆于该半导体芯片304及多个焊线306上。
所述电磁屏蔽层310包括一碳纳米管薄膜结构。可以理解，电磁屏蔽层310还可以进一步包括设置于碳纳米管薄膜结构中的金属填充颗粒320。其中，所述碳纳米管薄膜结构以及金属填充颗粒320与本技术方案第一实施例提供的碳纳米管薄膜结构以及金属填充颗粒220相同。
可以理解，本实施例中的半导体封装件30还可以进一步包括一散热片314设置于保护层312上，且所述散热片314的材料与本技术方案第一实施例提供的散热片214的材料相同。
请参阅图4，本技术方案第三实施例提供一种半导体封装件40，其包括：一基板402，且该基板402上设置有多个导电迹线(图中未显示)以及与该导电迹线相连的多个引脚416；至少两个半导体预封装件418设置于该基板402上，且相邻两个半导体预封装件418间隔设置；至少两个电磁屏蔽层410分别设置于所述至少两个半导体预封装件418上，且每一个电磁屏蔽层410将一半导体预封装件418整个覆盖；一保护层412覆盖于该至少一电磁屏蔽层410上。所述半导体预封装件418包括：一半导体芯片404，且该半导体芯片404包括多个焊垫(图中未显示)设置于该半导体芯片404上；多个焊线406，且该多个焊线406将半导体芯片404的焊垫与基板402上对应的导电迹线电性连接；一封装胶层408包覆于该半导体芯片404及多个焊线406上。
所述电磁屏蔽层410包括一碳纳米管薄膜结构。可以理解，电磁屏蔽层410还可以进一步包括设置于碳纳米管薄膜结构中的金属填充颗粒420。其中，所述碳纳米管薄膜结构以及金属填充颗粒420与本技术方案第一实施例提供的碳纳米管薄膜结构以及金属填充颗粒220相同。
可以理解，本实施例中的半导体封装件40还可以进一步包括一散热片414设置于保护层412上，且所述散热片414的材料与本技术方案第一实施例提供的散热片214的材料相同。
本实施例中提供的半导体封装件工作时，将所述电磁屏蔽层接地，通过该电磁屏蔽层中的碳纳米管薄膜结构以及设置于该碳纳米管薄膜结构中的金属填充颗粒可以吸收或反射电磁波，从而阻止半导体芯片运行时产生的电磁波传到外界，起到电磁屏蔽功效。
本技术方案实施例提供的半导体封装件，采用碳纳米管薄膜结构制备电磁屏蔽层，能够有效吸收电磁波，且导电性与散热性能优良，重量轻，使用方便。
另外，本领域技术人员还可在本发明精神内做其他变化，当然，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围之内。

Claims (20)

1.一种半导体封装件，其包括：一基板，且该基板的第一表面设置有多个导电迹线；至少一半导体预封装件设置于该基板上，该半导体预封装件与所述多个导电迹线设置于该基板上的同一表面，且与该多个导电迹线电连接；至少一电磁屏蔽层设置于所述至少一半导体预封装件上，并将该至少一半导体预封装件的顶面以及侧面均覆盖；一保护层覆盖于该至少一电磁屏蔽层上，其特征在于，所述的电磁屏蔽层包括一碳纳米管薄膜结构。
2.如权利要求1所述的半导体封装件，其特征在于，所述的碳纳米管薄膜结构包括至少一个碳纳米管层，且该碳纳米管层中的碳纳米管沿同一方向择优取向排列。
3.如权利要求2所述的半导体封装件，其特征在于，所述的碳纳米管薄膜结构包括至少两个重叠设置的碳纳米管层，相邻两个碳纳米管层之间通过范德华力紧密连接，且相邻两个碳纳米管层中的碳纳米管的排列方向形成一夹角α，0°≤α≤90°。
4.如权利要求2所述的半导体封装件，其特征在于，所述碳纳米管层包括一碳纳米管薄膜或至少两个平行且无间隙排列的碳纳米管薄膜，且相邻两个碳纳米管薄膜之间通过范德华力紧密连接。
5.如权利要求4所述的半导体封装件，其特征在于，所述碳纳米管薄膜的厚度为0.01微米～100微米。
6.如权利要求4所述的半导体封装件，其特征在于，所述的碳纳米管薄膜包括多个首尾相连且择优取向排列的碳纳米管束，且所述的碳纳米管束之间通过范德华力紧密连接。
7.如权利要求6所述的半导体封装件，其特征在于，所述的碳纳米管束包括多个具有相同长度且相互平行排列的碳纳米管。
8.如权利要求7所述的半导体封装件，其特征在于，所述的碳纳米管为单壁碳纳米管、双壁碳纳米管及多壁碳纳米管中的一种。
9.如权利要求7所述的半导体封装件，其特征在于，所述的碳纳米管的长度为200微米～400微米，直径小于50纳米。
10.如权利要求3所述的半导体封装件，其特征在于，所述的碳纳米管薄膜结构中包括均匀且规则分布的微孔结构，且该微孔的直径为1纳米～0.5微米。
11.如权利要求10所述的半导体封装件，其特征在于，所述的电磁屏蔽层进一步包括金属填充颗粒设置于该碳纳米管薄膜结构中。
12.如权利要求11所述的半导体封装件，其特征在于，所述的金属填充颗粒均匀分散于碳纳米管薄膜结构中的微孔中或夹在相邻两个碳纳米管层之间。
13.如权利要求11所述的半导体封装件，其特征在于，所述的金属填充颗粒的平均粒径小于1微米。
14.如权利要求11所述的半导体封装件，其特征在于，所述的金属填充颗粒包括一多孔性金属颗粒或多孔性合金颗粒。
15.如权利要求1所述的半导体封装件，其特征在于，所述的半导体预封装件包括一半导体芯片，且该半导体芯片包括多个焊垫设置于该半导体芯片上；多个焊线，且该多个焊线将半导体芯片的焊垫与基板上对应的导电迹线电性连接；一封装胶层包覆于该半导体芯片及多个焊线上。
16.如权利要求15所述的半导体封装件，其特征在于，所述的封装胶层的材料为一树脂材料。
17.如权利要求1所述的半导体封装件，其特征在于，所述的半导体封装件包括一个电磁屏蔽层及多个半导体预封装件，且该电磁屏蔽层将该多个半导体预封装件覆盖。
18.如权利要求1所述的半导体封装件，其特征在于，所述的半导体封装件包括多个电磁屏蔽层及多个半导体预封装件，且每一个电磁屏蔽层将一个对应的半导体预封装件覆盖。
19.如权利要求1所述的半导体封装件，其特征在于，所述的基板进一步包括多个引脚设置于基板上与第一表面相对的第二表面上，且该多个引脚与所述多个导电迹线对应电连接。
20.如权利要求1所述的半导体封装件，其特征在于，所述的半导体封装件进一步包括一散热片设置于保护层上。
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