CN101369615B - Packaging method for low-thermal resistance high-power light-emitting diode - Google Patents
Packaging method for low-thermal resistance high-power light-emitting diode Download PDFInfo
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- CN101369615B CN101369615B CN2007100449650A CN200710044965A CN101369615B CN 101369615 B CN101369615 B CN 101369615B CN 2007100449650 A CN2007100449650 A CN 2007100449650A CN 200710044965 A CN200710044965 A CN 200710044965A CN 101369615 B CN101369615 B CN 101369615B
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- thermal resistance
- emitting diode
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- power light
- resistance high
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention discloses a packaging method of a low thermal resistance and high power light emitting diode (LED). The LED mainly comprises a light emitting chip, electrodes, wire leads, a metal substrate and colloidal silica with fluorescent powder. The invention is characterized in that the metal substrate is deposited on the bottom surface of the light emitting chip through a plating technique. The invention has the advantages that the packaging thermal resistance is effectively reduced and the packaging heat-sinking capability of the high power LED because the light emitting chip is directly positioned on the metal substrate and no middle bonding layer such as a solder is in the middle, and the packaging method can realize batch manufacture of LED array packaging modules, has high reliability and low cost.
Description
Technical field
The present invention relates to a kind of large-power light-emitting diodes, particularly a kind of method for packing of low-thermal resistance high-power light-emitting diode.
Background technology
It is little that LED has power consumption, the luminous efficiency height, and advantage such as the response time is short, and volume is little, and is in light weight, photochromic pure, and the life-span is long is thought the main direction in lighting source market to have powerful market potential by industry.For LED, its failure cause mainly comprises current overload, temperature too high (overheated) and encapsulation inefficacy etc.Because the input electric energy has only 10%-20% to be converted into light, all the other all are converted into heat, and therefore, chip cooling is that the LED encapsulation must the primary problem that solves.Because the bad pn junction temperature that causes of heat radiation raises, and will badly influence emission wavelength, light intensity, light efficiency and useful life.Good cooling system can obtain lower working temperature under equal input power, prolong the useful life of LED; Or in same temperature limited region, increase input power or chip density, thereby increase the brightness of LED lamp.
For low-power LED (as common
5mmLED, its power only are tens milliwatts), heating problem and not serious, even thermal resistance higher (generally be higher than 100 ℃/W), adopt common encapsulating structure to get final product.And the high-brightness white-light LED that semiconductor lighting is used generally adopts high-power LED chip, and its input power is 1W or higher, and chip area is about 1 * 1mm
2, so density of heat flow rate is up to 100W/cm
2More than.In addition, for high-power LED encapsulation, for improving luminous flux, the general array module mode that adopts, owing to the high density of luminescence chip is integrated, the temperature on the heat-radiating substrate is very high, must adopt higher baseplate material of thermal conductivity and suitable packaging technology, to reduce packaging thermal resistance.
For the LED packaging, thermal resistance mainly comprises material (heat-radiating substrate and heat sink structure) internal thermal resistance and interface resistance.The effect of heat-radiating substrate is exactly to absorb the heat that chip produces, and be transmitted to heat sink on, realize and extraneous heat exchange.The most frequently used heat-radiating substrate material is metal core circuit board (MCPCB) at present, because insulating barrier thermal conductivity lower (0.2-3.0W/mK) in the middle of it makes the thermal resistance of whole base plate bigger.In addition, metal (as aluminium, copper), pottery are (as Al
2O
3, AlN, SiC) and composite material etc. also can be used on the LED base plate for packaging.U.S. Lamina company has developed the LED encapsulation technology based on LTCC metal substrate (LTCC-M).This technology is at first prepared high-power LED chip and the corresponding ceramic substrate that is suitable for the eutectic weldering, then led chip and ceramic substrate is directly welded together.Because this ceramic material thermal conductivity height (170-210W/mK), and package interface is few, has improved heat-sinking capability greatly, for the high-power LED array encapsulation has proposed solution.In addition, German Curmilk company has developed the ceramic copper-clad plate of high-termal conductivity, by ceramic substrate (AlN or Al
2O
3) and metallic copper (Cu) sintering under HTHP form, do not use adhesive, so good heat conductivity (greater than 160W/mK), and thermal coefficient of expansion (4.0 * 10
-6/ ℃) suitable with silicon, thereby reduced the encapsulation thermal stress.
Studies show that package interface is also very big to the thermal resistance influence, if can not correctly handle the interface, just is difficult to obtain better heat radiating effect.For example, at high temperature may there be interfacial gap in the contact good interface under the room temperature, and the warpage of substrate also may influence bonding and local heat radiation.The key of improving the LED encapsulation is to reduce interface and interface contact heat resistance, strengthens heat radiation.Therefore, the thermal interfacial material between chip and heat-radiating substrate (TIM) is selected very important.LED encapsulation TIM commonly used is a conductive silver glue, because thermal conductivity is lower, is generally 0.5-2.5W/m.K, causes interface resistance very high.In recent years, the trend that gradually adopts high heat-conductivity conducting glue, soldering paste or eutectic solder is arranged,,, be easy to generate residual thermal stress in hot setting, backflow or the eutectic weldering process, influence package reliability because material thermal expansion coefficient does not match though its thermal resistance is lower.
Summary of the invention
The objective of the invention is provides a kind of method for packing of low-thermal resistance high-power light-emitting diode at the defective that exists in the prior art.The present invention mainly comprises: luminescence chip, electrode, lead-in wire, metal substrate and contain the colloidal silica of fluorescent material is characterized in that described metal substrate directly is deposited on the luminescence chip bottom surface through electroplating technology.This method for packing comprises following step:
A brushes or spin coating one deck epoxy glue at smooth glass surface;
B is mounted on luminescence chip and electrode slice composition array left-hand thread on the epoxy adhesive layer;
C adopts evaporation or sputtering technology in chip bottom planar depositions layer of metal Seed Layer;
D adopts electroplating technology at metal seed layer surface deposition substrate metal layer;
Sheet glass integral body after E will electroplate is immersed in the acetone soln, and sheet glass and epoxy adhesive layer are broken away from;
F adopts routing, coating technique, finishes that low-thermal resistance high-power light-emitting diode is encapsulated.
Advantage of the present invention is that luminescence chip is located immediately on the metal substrate, intermediate adhesive layer such as open, heat-conducting glue, reduced hot interface number, reduced thermal resistance effectively, improved the high-power LED encapsulation heat-sinking capability, and belong to a kind of low temperature process owing to electroplate, the LED thermal stress after the encapsulation is little, the reliability height.By the choose reasonable inter-chip pitch, can realize batch manufacturing to the led array package module, reduce the high-power LED encapsulation cost.
Description of drawings
The structure of Fig. 1 a PI film;
The structure of Fig. 1 b electrode slice;
Fig. 2 a electroplating technology prepares the packaged substrate technology flow chart;
Fig. 2 b electroplating technology prepares the packaged substrate technology flow chart;
Fig. 2 c electroplating technology prepares the packaged substrate technology flow chart;
Fig. 2 d electroplating technology prepares the packaged substrate technology flow chart;
Fig. 2 e electroplating technology prepares the packaged substrate technology flow chart;
LED structure chart after Fig. 3 encapsulation;
Fig. 4 a PI membrane structure with holes figure;
Fig. 4 b PI film with holes sectional structure chart;
Fig. 5 a electroplating technology prepares the packaged substrate technology flow chart;
Fig. 5 b electroplating technology prepares the packaged substrate technology flow chart;
Fig. 5 c electroplating technology prepares the packaged substrate technology flow chart;
Fig. 5 d electroplating technology prepares the packaged substrate technology flow chart;
Fig. 5 e electroplating technology prepares the packaged substrate technology flow chart;
LED structure chart after Fig. 6 encapsulation.
11 metal levels, 12 insulating barriers, electrode slice after 13 shearings, 21 sheet glass, 22 epoxy adhesive layers, 23 luminescence chips, 24 electrode slices, 25 metal seed layers (nickel), 26 metallic coppers, 27 acetone solns, 31 luminescence chips, 32 metal seed layers (nickel), 33 electrodes, 34 copper sheets, 35 gold threads, 36 packing colloids, 41 electrode structures, the 42PI film, 43 chip hole, 51 sheet glass, 52 epoxy adhesive layers, 53 luminescence chips, 54 metallic nickel films, 55 metallic coppers, 56 acetone solns, 61 luminescence chips, 62 copper bases, 63PI film preformed hole, the 64PI film, 65 gold threads, 66 packing colloids
Embodiment
Embodiment 1
Further specify embodiments of the invention below in conjunction with accompanying drawing:
Referring to Fig. 1 a, adopt soft board PCB technology to make the PI film that contains insulating barrier 12 and metal level 11, then the PI film is cut into electrode slice 13, referring to Fig. 1 b;
The concrete steps that the employing electroplating technology prepares base plate for packaging are as follows:
Steps A referring to Fig. 2 a, is brushed or spin coating one deck epoxy glue 22 on smooth sheet glass 21 surfaces, and thickness is (greater than chip thickness) about 1mm, requires the glue-line surfacing;
Step B is mounted on 24 one-tenth array left-hand threads of luminescence chip 23 and electrode slice on the epoxy adhesive layer 22, flattens (making chip, electrode slice bottom be in same plane), and cured epoxy glue, referring to Fig. 2 b;
Step C, adopt evaporation or sputtering technology at chip bottom planar depositions layer of metal nickel 25 (as plating seed layer, thickness is 50-100nm, select the reason of nickel to be that it is effective ion diffusion barrier layer, and CTE coupling with copper, control thickness is that its thermal conductivity is low, reduces thermal resistance) referring to Fig. 2 c; Adopt electroplating technology at nickel 25 surface deposition metallic coppers 26 (thickness is 0.3mm-3mm) referring to Fig. 2 d;
Step D is immersed in the sheet glass integral body after the copper facing in the acetone soln 27, and sheet glass and epoxy adhesive layer are broken away from, and chip becomes array to be mounted on the base plate for packaging (copper sheet), referring to Fig. 2 e with electrode slice.
Step e adopts routing, coating technique, finishes the encapsulation to LED, referring to Fig. 3.
Embodiment 2
Embodiment 2 is identical with embodiment 1, and different is to adopt soft board PCB technology to make PI film 42, and surface deposition has the led circuit and the electrode structure 41 of copper facing/gold, and the chip hole 43 of pre-retained array distribution, referring to Fig. 4 a, Fig. 4 b.
The concrete steps that electroplating technology prepares base plate for packaging are identical with embodiment 1, different is to adopt cementation process PI film 64 to be mounted on the surface of base plate for packaging 62, (preformed hole is corresponding with luminescence chip 61 on the PI film) adopts silica gel 66 to encapsulate, referring to Fig. 6 then.
In the respective embodiments described above, the base plate for packaging material of described plating preparation can also be copper alloy, nickel or nickel alloy.
Claims (4)
1. the method for packing of a low-thermal resistance high-power light-emitting diode, mainly comprise: luminescence chip, electrode, lead-in wire, metal substrate and contain the colloidal silica of fluorescent material, it is characterized in that described metal substrate directly is deposited on the luminescence chip bottom surface through electroplating technology, this method for packing comprises following step:
A brushes or spin coating one deck epoxy glue at smooth glass surface;
B is mounted on luminescence chip and electrode slice composition array left-hand thread on the epoxy adhesive layer, flattens, and makes chip, electrode slice bottom be in same plane, and cured epoxy glue, and wherein said electrode slice is made up of metal level and insulating barrier;
C adopts evaporation or sputtering technology in chip bottom planar depositions layer of metal Seed Layer;
D adopts electroplating technology at metal seed layer surface deposition substrate metal layer;
Sheet glass integral body after E will electroplate is immersed in the acetone soln, and sheet glass and epoxy adhesive layer are broken away from;
F adopts routing, coating technique, finishes that low-thermal resistance high-power light-emitting diode is encapsulated.
2. the method for packing of low-thermal resistance high-power light-emitting diode according to claim 1 is characterized in that described metal substrate material is copper or copper alloy, aluminum or aluminum alloy.
3. the method for packing of low-thermal resistance high-power light-emitting diode according to claim 1 is characterized in that described metal substrate thickness is 0.3-3.0mm.
4. the method for packing of low-thermal resistance high-power light-emitting diode according to claim 1 is characterized in that described seed metallization layer material is nickel, chromium, gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100449650A CN101369615B (en) | 2007-08-17 | 2007-08-17 | Packaging method for low-thermal resistance high-power light-emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100449650A CN101369615B (en) | 2007-08-17 | 2007-08-17 | Packaging method for low-thermal resistance high-power light-emitting diode |
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| Publication Number | Publication Date |
|---|---|
| CN101369615A CN101369615A (en) | 2009-02-18 |
| CN101369615B true CN101369615B (en) | 2010-11-10 |
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| CN2007100449650A Active CN101369615B (en) | 2007-08-17 | 2007-08-17 | Packaging method for low-thermal resistance high-power light-emitting diode |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5741439B2 (en) * | 2009-10-01 | 2015-07-01 | 日亜化学工業株式会社 | Light emitting device |
| CN102487063A (en) * | 2010-12-03 | 2012-06-06 | 刘胜 | LED (Light-Emitting Diode) array packaging structure with microstructure silica-gel lens |
| US9324905B2 (en) | 2011-03-15 | 2016-04-26 | Micron Technology, Inc. | Solid state optoelectronic device with preformed metal support substrate |
| CN103378275A (en) * | 2012-04-27 | 2013-10-30 | 展晶科技(深圳)有限公司 | Light emitting diode encapsulating structure |
| CN103050155B (en) * | 2012-11-06 | 2015-12-02 | 国家核电技术有限公司 | Accident mitigation device and manufacture method, nuclear plant pressure vessels, accident mitigation method |
| CN103337586B (en) * | 2013-05-31 | 2016-03-30 | 江阴长电先进封装有限公司 | Silicon-free wafer-level LED packaging method |
| JP6333302B2 (en) * | 2016-03-30 | 2018-05-30 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing apparatus, and program |
| CN106229401A (en) * | 2016-08-24 | 2016-12-14 | 电子科技大学 | Fluorescence LED array of packages |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2413390Y (en) * | 2000-02-24 | 2001-01-03 | 台湾光宝电子股份有限公司 | Light-emitting diode device |
| CN1839470A (en) * | 2003-09-19 | 2006-09-27 | 霆激科技股份有限公司 | Fabrication of conductive metal layer on semiconductor devices |
-
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- 2007-08-17 CN CN2007100449650A patent/CN101369615B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2413390Y (en) * | 2000-02-24 | 2001-01-03 | 台湾光宝电子股份有限公司 | Light-emitting diode device |
| CN1839470A (en) * | 2003-09-19 | 2006-09-27 | 霆激科技股份有限公司 | Fabrication of conductive metal layer on semiconductor devices |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2003-347590A 2003.12.05 |
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Assignee: Hunan Yiyuan Photoelectric Technology Co., Ltd. Assignor: Guangdong Shaoxin Opto-electrical Technology Co., Ltd. Contract record no.: 2011430000048 Denomination of invention: Packaging method for low-thermal resistance high-power light-emitting diode Granted publication date: 20101110 License type: Exclusive License Open date: 20090218 Record date: 20110421 |
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Effective date of registration: 20210813 Address after: 528200 unit 601, floor 6, block a, Jingu Zhichuang industrial community, No. 2, Yong'an North Road, Dawei community, Guicheng Street, Nanhai District, Foshan City, Guangdong Province Patentee after: GUANGDONG REAL FAITH LIGHTING TECHNOLOGY Co.,Ltd. Address before: Pingzhou shaweiqiao industrial West Zone, Nanhai District, Foshan City Patentee before: GUANGDONG REAL FAITH OPTO-ELECTRONIC Co.,Ltd. |
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