CN101364583A - Capacitor embedded semi-conductor package substrate construction and preparation thereof - Google Patents
Capacitor embedded semi-conductor package substrate construction and preparation thereof Download PDFInfo
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- CN101364583A CN101364583A CN 200710140835 CN200710140835A CN101364583A CN 101364583 A CN101364583 A CN 101364583A CN 200710140835 CN200710140835 CN 200710140835 CN 200710140835 A CN200710140835 A CN 200710140835A CN 101364583 A CN101364583 A CN 101364583A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
The invention relates to a semiconductor encapsulated baseplate structure, in which a capacitance component is embedded. The structure comprises an inner layer circuit board, a dielectric layer and an outer circuit layer, wherein, the dielectric layer is disposed on both sides of the inner layer circuit board and provided with a first conductive blind hole which is communicated with the inner layer circuit board through a thin metal layer, a capacitance material, an electrode layer and an adhesive layer in sequence; the external circuit layer is disposed on the surface of the dielectric layer; and herein, the thin metal layer, the capacitance material and the electrode layer are taken as a capacitance component. The invention further provides a method for manufacturing the semiconductor encapsulated baseplate structure. Compared with the capacitance material formed by compressing the whole piece of high-dielectric material, the capacitance component embedded in the semiconductor encapsulated baseplate has the advantages of saving material, solving the pore-filling problem and avoiding creepage of the capacitance between circuits.
Description
Technical field
The present invention relates to a kind of capacitor embedded semi-conductor package substrate construction and preparation method thereof, refer to that especially a kind of being applicable to improve the capacitance material leaky and produce hole and capacitor embedded semi-conductor package substrate construction of phenomenons such as uneven thickness and preparation method thereof.
Background technology
Because the progress of manufacture of semiconductor, and the continuous lifting of semiconductor core on-chip circuit function make the development of semiconductor device move towards the height productive setization.But the productive setization of semiconductor device, the pin number of packaging structure be also along with increase, and because pin number and increasing that circuit is laid cause also increase thereupon of noise.Therefore, be generally and eliminate noise or do electrically compensation, in semiconductor package, increase passive device, as resistive element, capacitance material and inductance element, to eliminate noise and stabilizing circuit, so that packaged semiconductor chip meets the requirement of electric characteristics.
In traditional method, mainly capacity cell is utilized surface adhering technology (SurfaceMount Technology; SMT) place substrate surface, the mode that many research and utilization pressings are arranged at present is pressed on the copper interlayer with high dielectric material and makes circuit again to form capacity cell.As shown in Figure 1, for utilizing the pressing mode to form the structure cutaway view of capacity cell at present.It mainly provides an inner layer circuit board 11, a high dielectric material layer 12, an outer-layer circuit layer 13, to electroplate via (Plated Through Hole; PTH) 14, one welding resisting layer 15 and a solder system ball 16.Wherein, this inner layer circuit board 11 has an internal layer circuit layer 11a.High dielectric material layer 12 is pressed on the internal layer circuit layer 11a, then forms an outer-layer circuit layer 13 in high dielectric material layer 12 surfaces again, therefore forms a capacity cell.But electroplate the circuit of these substrate both sides of via 14 conductings.Then proceed follow-up processing procedure again and form welding resisting layer 15 and solder system ball 16.
Yet this kind method is utilized the suitable height of cost of full wafer high dielectric material pressing, iff using the minority area can cause waste of material.In addition, have the problem of filling perforation, because the full wafer high dielectric material, its gummosis is very poor, so be easy to have the phenomenon generation that hole (void) produced and had uneven thickness.In addition, this kind method still has another problem, promptly has the electric leakage problem of capacitive phenomena between circuit, and because of leaky (current leakage) easily takes place for the high dielectric material of full wafer, especially the application on high frequency is even more serious.
Summary of the invention
Shortcoming in view of above-mentioned prior art, the objective of the invention is to overcome the deficiencies in the prior art and defective, propose a kind of being applicable to and improve the capacitance material leaky and produce capacitor embedded semi-conductor package substrate construction of phenomenons such as hole and uneven thickness and preparation method thereof.
For reaching above-mentioned purpose, the invention provides a kind of capacitor embedded semi-conductor package substrate construction, this structure comprises an inner layer circuit board, a dielectric layer and an outer-layer circuit layer.In inner layer circuit board, can have an internal layer circuit layer.Configurable in the both sides of inner layer circuit board in dielectric layer, and have a plurality of first conductive blind holes in the dielectric layer, and first conductive blind hole can be in regular turn via a thin metal layer, a capacitance material, an electrode layer and an adhesion coating and the conducting of internal layer circuit layer.Then configurable as for the outer-layer circuit layer in the dielectric layer surface.Wherein, this capacitance material and electrode layer can be used as a capacity cell.This kind is embedded in the capacity cell in the conductor package substrate, can save material, no filling perforation problem and not have the electric leakage problem of the capacitive phenomena between circuit.
In the present invention, also can comprise at least one second conductive blind hole in the dielectric layer, itself and the conducting of internal layer circuit layer.
And in dielectric layer of the present invention, also can comprise an outside via of electroplating, its conducting is disposed at the outer-layer circuit layer on the dielectric layer surface of inner layer circuit board both sides.
According to the conductor package substrate with flush type selectivity capacity cell of the invention described above, for example can make by step following but that be not limited thereto.
Be and reach above-mentioned purpose, the present invention also provides a kind of manufacture method of capacitor embedded semi-conductor package substrate construction, and its step comprises: at first, provide a metal support plate, form a plurality of capacitance materials in its surface, and the capacitance material surface forms an electrode layer.Then, form an adhesion coating in electrode layer surface.Again an inner layer circuit board is connected with the metal support plate via adhesion coating.Then, with this metal support plate reduced thickness.Then, remove the metal support plate that is not connected with capacitance material, and the metal support plate that is connected with capacitance material then can form a thin metal layer, therefore this thin metal layer, capacitance material and electrode layer can form a capacity cell.Distinguish pressing one dielectric layer in both sides, inner layer circuit board surface again, and form a plurality of first blind holes in this dielectric layer, this first blind hole can be corresponding to the thin metal layer that is formed by the metal support plate.Can form one first conductive blind hole and an outer-layer circuit layer respectively in first blind hole and dielectric layer surface at last.
In the present invention, behind the pressing dielectric layer, also can form at least one second blind hole in this dielectric layer, it is corresponding to the circuit of inner layer circuit board, and forms one second conductive blind hole at least one second blind hole.
Also comprise in addition forming at least one through hole (through hole) in this dielectric layer, this through hole runs through the dielectric layer of inner layer circuit board and both sides thereof, and forms an outside via of electroplating in through hole.
In the present invention, inner layer circuit board also comprises and can form an internal electroplated via.This internal electroplated via can be via copper, tin, nickel, chromium, titanium, copper-evanohm or the tin-lead alloy circuit with conducting inner layer circuit board both sides.Preferably can use the copper metal.In addition, this electroplates in the via and more can comprise an insulating resin, for example epoxy resin.
According to the invention described above, can be in first conductive blind hole and second conductive blind hole for filling up or do not fill up electric conducting material, described electric conducting material can be copper, tin, nickel, chromium, titanium, copper-evanohm or tin-lead alloy, preferably can be the copper metal.This first conductive blind hole and second conductive blind hole can form electric conducting material via the mode of electroplating respectively in first blind hole and second blind hole.
According to the invention described above, can be any sheet metal by the metal support plate and by the formed thin metal layer of metal support plate, for example be copper, aluminium or its associated alloys.Preferably can be copper.
Capacitance material used in the present invention, its material are high dielectric constant materials, preferably can be constituted by the macromolecule of macromolecular material, ceramic material, ceramic powder filled or the mixture of its analog.One of them that can be more preferably that barium titanate (Barium-tianate), zirconia titanate lead (Lead-Zirconate-tianate) and amorphous hydrogenated carbon (Amorphous hydrogenatedcarbon) constitutes group intersperses among in the binding agent (Binder) and forms.And the dielectric coefficient of this capacitance material is at least more than 40, preferable can be between 40～300.Simultaneously, can utilize and spatter the mode of crossing, printing or being coated with and form making capacitance material, more preferably, can utilize the mode of printing to form.
The present invention's employed material in electrode layer preferably can be copper cream or silver paste.And can utilize and spatter the mode of crossing, printing or being coated with and form, more preferably, the mode that can print forms.
The material that adhesion coating of the present invention uses is preferable to can be one of group that is formed in copper, tin, nickel, chromium, titanium, copper-evanohm and the tin-lead alloy, more preferably can use the tin cream made from tin material.The main function of this adhesion coating is as the effect that is connected with inner layer circuit board.Simultaneously, can use the mode of screen painting (screen printing) to form this adhesion coating in electrode layer surface.
In addition, the dielectric layer that the present invention uses can be selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber sensitization or non-sensitization organic resins such as (Aramide), but or also one of group of being formed of material such as blending epoxy and glass fibre.
Moreover, the mode that through hole of the present invention forms can be utilized machine drilling or laser drill, make to connect the dielectric layer of inner layer circuit board and both sides thereof, electroplate via and form an outside, this is outside electroplate via can conducting in the line layer on the dielectric layer surface of inner layer circuit board both sides, and more comprise an insulating resin in this outside plating in the via, for example epoxy resin.
In the invention described above, the material that line layer uses preferably can be one of group that is formed in copper, tin, nickel, chromium, titanium, copper-evanohm and the tin-lead alloy.More preferably, then can use copper as line layer.
In conductor package substrate provided by the present invention, can directly form a welding resisting layer (solder mask) and form a solder system ball to be connected with chip in superficies.Simultaneously also can form a layer reinforced structure in its both sides,, be connected with chip to continue making successive process as a core board.
The present invention can promote the laying quantity of passive device in the conductor package substrate, and increases the flexibility of base plate line layout, can effectively promote the substrate surface usable floor area, to reach the compact target of semiconductor device.
In addition, the selectivity capacity cell is made in utilization of the present invention on the metal support plate, in the mode of conductive blind hole or through hole conducting, not only can save material again, and does not have the problem of hole and uneven thickness.Same, can solve the electric leakage problem of capacitive phenomena between circuit.And it is can simplify processing procedure, and more accurate in the operation.
Description of drawings
Fig. 1 is the conductor package substrate construction cutaway view of existing laminated type capacity cell;
Fig. 2 and Fig. 3 are the capacitor embedded semi-conductor package substrate construction cutaway view of preferred embodiment of the present invention;
Fig. 4 A to 4H ' is that the capacitor embedded semi-conductor package substrate construction of a preferred embodiment of the present invention is made the flow process cutaway view;
Fig. 4 I and 4I ' are the conductor package substrate construction cutaway view that is connected with chip of a preferred embodiment of the present invention.
Symbol description among the figure
11,25 inner layer circuit board 11a, 25a internal layer circuit layer
12 high dielectric material layers, 13 outer-layer circuit layers
14 vias, 15,41 welding resisting layers
16 solder system ball 20a, the 20b conductor package substrate construction
21 metal support plate 21a thin metal layers
22 capacitance materials, 23 electrode layers
The internal electroplated via of 24 adhesion coating 25b
25c, 29 insulating resin 26a, first blind hole
The 26b second blind hole 26c through hole
27 conductive layers, 28 metal levels
30 outer-layer circuit layer 31a, first conductive blind hole
The 31b second conductive blind hole 32 outside vias of electroplating
43 chips, 42 projections
51 resistance layers, 52 openings
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this specification also can be carried out various modifications and change based on different viewpoints and application under not departing from spirit of the present invention.
The graphic schematic diagram that is simplification described in the embodiments of the invention.Described icon only shows the element relevant with the present invention, the aspect that its each shown element is non-when being actual enforcement, and component number, the shape equal proportion during its actual enforcement is an optionally design, and its component placement kenel may be more complicated.
Embodiment 1
Please refer to Fig. 2, be capacitor embedded semi-conductor package substrate construction cutaway view of the present invention.As shown in Figure 2, comprise an inner layer circuit board 25, a dielectric layer 26 and an outer-layer circuit layer 30.In inner layer circuit board 25, have an internal layer circuit layer 25a, this internal layer circuit layer 25a is a bronze medal layer, and this inner layer circuit board 25 also can include an internal electroplated via 25b, this internal electroplated via 25b comprises an insulating resin 25c again, and the material of inwall is a copper, with the internal layer circuit layer 25a of conducting in inner layer circuit board 25 both sides.26 of dielectric layers are disposed at inner layer circuit board 25 both sides, its employed material can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber sensitization or non-sensitization organic resins such as (Aramide), but or also the group that formed of material such as blending epoxy and glass fibre one of them, present embodiment then uses ABF.Have the first conductive blind hole 31a and the second conductive blind hole 31b in the dielectric layer 26 in addition, the first conductive blind hole 31a is in regular turn via a thin metal layer 21a, a capacitance material 22, an electrode layer 23 and an adhesion coating 24 and internal layer circuit layer 25a conducting.The second conductive blind hole 31b and internal layer circuit layer 25a conducting.At this, the material that the first conductive blind hole 31a and the second conductive blind hole 31b use is copper, tin, nickel, chromium, titanium, copper-evanohm or tin-lead alloy, and present embodiment then uses the copper metal, and is not filled among the first conductive blind hole 31a and the second conductive blind hole 31b.The operable material of thin metal layer 21a for example is copper, aluminium or its associated alloys, and present embodiment then uses copper.Capacitance material 22 then uses ceramic material in the present embodiment.23 of electrode layers use copper cream or silver paste.24 uses of adhesion coating are with the tin cream of tin as material.Again, capacitance material 22 can form a passive device, i.e. capacity cell with electrode layer 23.
Then, dielectric layer 26 surface is configurable an outer-layer circuit layer 30, and also configurable one outsidely electroplates via 32 in this structure, but its conducting is disposed at the outer-layer circuit layer 30 on dielectric layer 26 surfaces of inner layer circuit board 25 both sides.Wherein, outer-layer circuit layer 30 can be copper, tin, nickel, chromium, titanium, copper-evanohm or tin-lead alloy with the outside material of electroplating via 32 required conductings, and present embodiment then uses the copper metal.
Embodiment 2
Please refer to Fig. 3, be capacitor embedded semi-conductor package substrate construction cutaway view of the present invention.As shown in Figure 3, the structure of its structure and embodiment 2 is roughly the same, but different be that the first conductive blind hole 31c and the second conductive blind hole 31d of present embodiment fill up material, promptly fill up the copper metal.
Embodiment 3
The material that present embodiment uses can be identical as the material of embodiment 1.Present embodiment mainly is the method for making to please refer to Fig. 4 A to 4H ', is the cutaway view of the manufacture method of conductor package substrate with flush type selectivity capacity cell.
Shown in Fig. 4 A, at first, one metal support plate 21 is provided, the material that this metal support plate 21 uses can be copper coin, utilize the mode of coating or printing to form a plurality of capacitance materials 22 in its surface selectivity ground, form an electrode layer 23 in the same way in these capacitance material 22 surfaces again, can form a capacity cell through behind the high temperature sintering.
Then, shown in Fig. 4 B, on electrode layer 23, utilize screen painting to form the adhesion coating 24 of a fusible metal.For another example shown in Fig. 4 C, through adhesion coating 24 thus and with the capacity cell reflow to the internal layer circuit layer 25a of inner layer circuit board 25.
Then, shown in Fig. 4 D, utilize etched mode with metal support plate 21 attenuates.Continue shown in Fig. 4 E, the metal support plate 21 that utilizes etched mode not to be connected with capacitance material 22 removes again, the promptly only remaining part that is connected with capacitance material 22, thereby form a thin metal layer 21a.
For another example shown in Fig. 4 F, in this inner layer circuit board 25 both sides difference pressing one dielectric layer 26 or gum Copper Foil (Resign coated copper, icon not), in dielectric layer or gum Copper Foil, utilize laser drill and form the first blind hole 26a and the second blind hole 26b, directly run through dielectric layer 26 (or gum Copper Foil) and inner layer circuit board 25 via laser drill or machine drilling, and form a through hole 26c.Then, in this body structure surface, and the inwall of the first blind hole 26a, the second blind hole 26b and through hole 26c, utilize the mode of electroless-plating to form a conductive layer (seed layer) 27, this conductive layer 27 is mainly as the required current conduction path of successive process.The material of its use for example can be copper.
Then, shown in Fig. 4 G, in the surface of aforementioned structure, promptly the mode that can electroplate on conductive layer 27 forms a metal level 28, and inserts insulating resin 29 and obtain an outside via 32 of electroplating in the through hole 26c with metal level 28.Wherein, electroplate the usefulness that via 32 is mainly the circuit on conducting dielectric layer 26 surfaces.Shown in Fig. 4 H, the metal level 28 in dielectric layer 26 surfaces utilizes etched mode to make it form a line layer 30 for another example.
In addition, also can use semi-additive process, shown in Fig. 4 G ', form the resistance layer 51 of a patterning in conductive layer 27 surfaces, this resistance layer can be dry film or liquid photoresistance and has a plurality of openings 52 and also manifest through hole 26c, the first blind hole 26a and the second blind hole 26b, in opening 52, form metal level 28 in the mode of electroplating, for another example shown in Fig. 4 H ', insert insulating resin 29 and obtain an outside via 32 of electroplating, the conductive layer 27 that removes resistance layer 51 and covered in through hole 26c with metal level 28.Promptly form line layer 30 in dielectric layer 26 surfaces.
At this, above-mentioned these two types of the only simple illustration of present embodiment.In fact, no matter be by the Direct Electroplating metal level 28 of Fig. 4 G or the metal level 28 that gets by using semi-additive process among Fig. 4 G ', all can in the first blind hole 26a and the second blind hole 26b, obtain the first conductive blind hole 31a that does not fill up metal level 28 and the second conductive blind hole 31b shown in Fig. 4 H, certainly, also can according to processing procedure need form as among Fig. 4 H ' for filling up the first conductive blind hole 31c and the second conductive blind hole 31d of metal level 28.
Therefore, can obtain capacitor embedded semi-conductor package substrate construction 20a of the present invention, 20b.
Moreover, shown in Fig. 4 I and 4I ', this conductor package substrate construction 20a, 20b can be in its surface-coated one deck welding resisting layer 41, and forms projection 42, and can be connected with chip 43 via projection 42.
In sum, owing in the general prior art, be with passive device, capacity cell etc. for example is placed on the substrate not by on the occupied unnecessary layout area of semiconductor chip.Yet this kind layout method needs the substrate of large-size to implement.Though also there is research capacity cell to be embedded into to substrate in the mode of pressing, yet, utilizing the pressing of full wafer high dielectric material, its cost is very high, as only using the minority area, can cause waste of material.Have the problem of hole and electric leakage simultaneously.Capacitor embedded semi-conductor package substrate construction of the present invention, utilization are made capacity cell and have been solved aforesaid problem in the mode of conductive blind hole or through hole conducting again on loading plate.Simultaneously, can promote the laying quantity of passive device in the semiconductor device, and increase the flexibility of base plate line layout, can effectively promote the substrate surface usable floor area, to reach the compact target of semiconductor device, promote the electrical functionality of electronic product, and unlikely its configuration that influences.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claims are described certainly, but not only limits to the foregoing description.
Claims (10)
1. a capacitor embedded semi-conductor package substrate construction is characterized in that, comprising:
One inner layer circuit board, it has an internal layer circuit layer;
One dielectric layer, it is disposed at this inner layer circuit board both sides, and has a plurality of first conductive blind holes in this dielectric layer, and described first conductive blind hole is in regular turn via a thin metal layer, a capacitance material, an electrode layer and an adhesion coating and this internal layer circuit layer conducting; And
One outer-layer circuit layer, it is disposed at this dielectric layer surface.
2. capacitor embedded semi-conductor package substrate construction as claimed in claim 1 wherein, also comprises at least one second conductive blind hole in this dielectric layer, itself and this internal layer circuit layer conducting.
3. capacitor embedded semi-conductor package substrate construction as claimed in claim 1 wherein, also comprises an outside via of electroplating, and its conducting is disposed at this outer-layer circuit layer on this dielectric layer surface of these inner layer circuit board both sides.
4. capacitor embedded semi-conductor package substrate construction as claimed in claim 1, wherein, this inner layer circuit board also comprises an internal electroplated via.
5. capacitor embedded semi-conductor package substrate construction as claimed in claim 1, wherein, the material that this capacitance material uses is constituted by the macromolecule of macromolecular material, ceramic material, ceramic powder filled or the mixture of its analog.
6. the manufacture method of a capacitor embedded semi-conductor package substrate construction is characterized in that, comprises step:
One metal support plate is provided, forms a plurality of capacitance materials, and described capacitance material surface forms an electrode layer in its surface;
Form an adhesion coating in this electrode layer surface;
One inner layer circuit board is connected with this metal support plate via this adhesion coating;
With this metal support plate reduced thickness;
Remove this metal support plate that is not connected, and this metal support plate that is connected with this capacitance material forms a thin metal layer with this capacitance material;
In this both sides, inner layer circuit board surface difference pressing one dielectric layer, and form a plurality of first blind holes in this dielectric layer, described first blind hole is corresponding to this thin metal layer; And
Form one first conductive blind hole and an outer-layer circuit layer respectively in described first blind hole and this dielectric layer surface.
7. the manufacture method of capacitor embedded semi-conductor package substrate construction as claimed in claim 6, wherein, also comprise in this dielectric layer forming at least one second blind hole, it is corresponding to the circuit of this inner layer circuit board, and forms one second conductive blind hole in this at least one second blind hole.
8. the manufacture method of capacitor embedded semi-conductor package substrate construction as claimed in claim 6, wherein, also comprise in this dielectric layer and form at least one through hole, this at least one through hole runs through the dielectric layer of this inner layer circuit board and both sides thereof, and forms an outside via of electroplating in this at least one through hole.
9. the manufacture method of capacitor embedded semi-conductor package substrate construction as claimed in claim 6, wherein, this inner layer circuit board also comprises an internal electroplated via.
10. the manufacture method of capacitor embedded semi-conductor package substrate construction as claimed in claim 6, wherein, described first blind hole forms in the mode of laser drill.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710140835 CN101364583A (en) | 2007-08-10 | 2007-08-10 | Capacitor embedded semi-conductor package substrate construction and preparation thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710140835 CN101364583A (en) | 2007-08-10 | 2007-08-10 | Capacitor embedded semi-conductor package substrate construction and preparation thereof |
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| CN101364583A true CN101364583A (en) | 2009-02-11 |
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| CN 200710140835 Pending CN101364583A (en) | 2007-08-10 | 2007-08-10 | Capacitor embedded semi-conductor package substrate construction and preparation thereof |
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| CN102169861A (en) * | 2011-02-01 | 2011-08-31 | 日月光半导体制造股份有限公司 | Semiconductor structure with passive component structure and manufacture method thereof |
| CN102256450A (en) * | 2010-05-20 | 2011-11-23 | 深南电路有限公司 | Embedded circuit board of passive device and manufacturing method thereof |
| CN102398886A (en) * | 2010-09-15 | 2012-04-04 | 矽品精密工业股份有限公司 | Packaging structure with micro-electromechanical element and manufacturing method thereof |
| CN105244348A (en) * | 2015-09-30 | 2016-01-13 | 日月光半导体(上海)有限公司 | Package substrate and manufacturing method thereof |
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- 2007-08-10 CN CN 200710140835 patent/CN101364583A/en active Pending
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| CN102256450A (en) * | 2010-05-20 | 2011-11-23 | 深南电路有限公司 | Embedded circuit board of passive device and manufacturing method thereof |
| CN102398886A (en) * | 2010-09-15 | 2012-04-04 | 矽品精密工业股份有限公司 | Packaging structure with micro-electromechanical element and manufacturing method thereof |
| CN102398886B (en) * | 2010-09-15 | 2014-07-23 | 矽品精密工业股份有限公司 | Packaged structure with micro-electromechanical device and manufacture method thereof |
| CN102169861A (en) * | 2011-02-01 | 2011-08-31 | 日月光半导体制造股份有限公司 | Semiconductor structure with passive component structure and manufacture method thereof |
| CN107546140A (en) * | 2012-10-19 | 2018-01-05 | 英飞凌科技股份有限公司 | Embedded chip encapsulates and the method for manufacturing embedded chip encapsulation |
| CN105244348A (en) * | 2015-09-30 | 2016-01-13 | 日月光半导体(上海)有限公司 | Package substrate and manufacturing method thereof |
| CN105244348B (en) * | 2015-09-30 | 2017-12-22 | 日月光半导体(上海)有限公司 | Package substrate and its manufacture method |
| CN110036699A (en) * | 2016-12-07 | 2019-07-19 | 凸版印刷株式会社 | Core substrate, multi-layered wiring board, semiconductor package body, the manufacturing method of semiconductor subassembly, copper-clad base plate and core substrate |
| CN111812483A (en) * | 2019-04-10 | 2020-10-23 | 联发科技股份有限公司 | Apparatus for testing chips or dies |
| TWI741319B (en) * | 2019-06-12 | 2021-10-01 | 大陸商宏啟勝精密電子（秦皇島）有限公司 | Packaging strucutre and method of manufacturing the same |
| CN113853069A (en) * | 2020-06-28 | 2021-12-28 | 庆鼎精密电子（淮安）有限公司 | Manufacturing method of circuit board intermediate, circuit board and manufacturing method thereof |
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