CN101315894B

CN101315894B - Method for raising puncture voltage between two polysilicons of groove type double-layer grid power MOS

Info

Publication number: CN101315894B
Application number: CN200710093843A
Authority: CN
Inventors: 马清杰; 金勤海; 缪进征
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-05-30
Filing date: 2007-05-30
Publication date: 2010-05-26
Anticipated expiration: 2027-05-30
Also published as: CN101315894A

Abstract

The invention discloses a method for improving the breakdown voltage between two layers of polysilicon of a trench type dual-layer gate power MOS, the method comprises that: (1) the etching of a trench adopts the 90-degree etching process; (2) the deposition and the etching process of a first layer of polysilicon are as follows: the non-doped polysilicon is firstly grown, then the polysilicon is doped, and the doped polysilicon is finally carried out the etching. The power MOS device prepared by the steps of the method of the invention can greatly improve the breakdown voltage between two layers of polysilicon, greatly improve the uniformity of the electrical performance of the device and be widely applied in the preparation of a trench type dual-layer gate power MOS device.

Description

Improve the method for groove type double-layer grid power MOS puncture voltage between two polysilicons

Technical field

The present invention relates to a kind of manufacture method of power MOS (Metal Oxide Semiconductor) device, particularly a kind of manufacture method that improves groove type double-layer grid power MOS device puncture voltage between two polysilicons.

Background technology

Power MOSFET (field-effect transistor of MOS structure) is a best device for power switching in the low pressure range, with its input impedance height, low-loss, switching speed are fast, no second breakdown, the safety operation area is wide, dynamic property good, the coupling of the Yi Yuqian utmost point realizes that characteristics such as big electric currentization, conversion efficiency height are used to handle electric energy, comprises frequency translation, Power Conversion and control, DC/DC conversion etc.Its production technology enters sub-micron, deep-submicron epoch, adopt small unit size the 5th generation power MOSFET and the groove gate power MOS FET suitability for industrialized production of the development of side wall (Spacer) technology, 4448.5 ten thousand of cellular density up to every square centimeter, its hand work and microelectronic circuit are suitable, new construction, new technology are also in constantly improving, and to aspects development such as high-voltage great-current, low pressure small-power, extremely low internal resistance, linear microwave power MOS devices.The product that adopts corrosion grooving technology to have groove on tube core is called groove type MOS field-effect transistor (Trench MOSFET), and the raceway groove of groove structure is vertical.Can make the grid of MOS at its sidewall, shared area is littler than lateral channel, further improve cellular density, can strengthen the avalanche breakdown ability of MOSFET on device performance, effectively reduces conducting resistance, reduce driving voltage, become the preferred texture of pursuing ultralow on-state drain-source resistance performance.

The groove type double-layer grid power MOS device has the puncture voltage height, and conducting resistance is low, and the characteristic that switching speed is fast has great application prospect.The double-deck grid structure of common groove type power MOS device (see figure 1), comprising: silicon chip substrate 11 is as the drain electrode of power MOS (Metal Oxide Semiconductor) device; The groove 12 of preparation on silicon epitaxy layer 10; The thick grating oxide layer 13 of the trenched side-wall of its ground floor polysilicon filling part; Ground floor polysilicon 14 in the groove; Deposit high-density plasma oxide-film 15 in the groove on it; Be second layer polysilicon 17 again; Its sidewall is filled thin gate oxide 18; Preparation channel body 19 and source electrode 20 on the silicon epitaxy layer 10 between the groove; Ground floor polysilicon reliable ground (not providing among the figure) wherein, second layer polysilicon 17 is as grid (gate).In existing preparation technology, after ground floor polysilicon 14 (DOPOS technical process) deposit of mixing simultaneously, have a slit in the middle of the groove, after the ground floor polysilicon anti-carves, slit in the middle of the groove can be deepened and be formed ground floor polysilicon wedge angle (Fig. 2) in the position near trenched side-wall, and this can the serious puncture voltage that reduces between the two-layer polysilicon.For fear of this problem, change into and adopted 88 degree grooves, and at the same time after the ground floor polysilicon deposit of Can Zaing, 900 ℃ have been increased, 30 minutes, annealing in process under the nitrogen, but this can cause again after the ground floor polysilicon anti-carves, the surface of ground floor polysilicon is very coarse, the non-constant of degree of depth uniformity from the ground floor polysilicon surface to trench top, also can cause the membranous more loose of next step high-density plasma oxide-film, remaining high-density plasma oxide thickness uniformity is very poor behind the wet etching, local location even do not have high-density plasma oxide-film residue has a strong impact on the uniformity of device electrical performance, and has reduced puncture voltage even short circuit between the two-layer polysilicon.Its reason be because DOPOS through 900 degree, 30 minutes n 2 annealings impel polysilicon grain to grow up to have worsened the surface smoothness after the ground floor polysilicon anti-carves.The real grid of groove type double-layer grid power MOS device is a second layer polysilicon, ground floor polysilicon and source ground play the effect that improves device electric breakdown strength, therefore the voltage that can add on the second layer polysilicon gate should be determined by real gate oxide, rather than the decision of the high-density plasma oxide-film between the two-layer polysilicon.But the voltage that can add on the second layer polysilicon gate in the existing technology seriously is lower than the magnitude of voltage that should be able to bear, its reason just is the puncture electric leakage that the high-density plasma oxide-film between the two-layer polysilicon causes, exactly because and the ground floor polysilicon of this deposit of mixing simultaneously anti-carves that the rear surface roughening causes.In addition, adopt 88 degree grooves, cause can't online accurate measurement groove the degree of depth.Because after 88 degree etching grooves, online measurement figure trench bottom surfaces out-of-flatness (claim black silicon phenomenon) can't online accurate measurement ditch depth, has limited the feasibility of technology.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method that improves the groove type double-layer grid power MOS puncture voltage between two polysilicons, and it can improve the puncture voltage between the two-layer polysilicon of groove type double-layer grid power MOS device and improve the electrical property uniformity of power MOS (Metal Oxide Semiconductor) device.

For solving the problems of the technologies described above, method of the present invention comprises: (1) etching 90 degree grooves; (2) deposit of ground floor polysilicon and etching technics are: at 620 ℃ of plain polysilicons of growing down, POCl is used in the back under 900 ℃ earlier ₃For doped source is mixed to this polysilicon, the polysilicon after last etching is mixed.

Owing to adopted the etching groove of 90 degree in the method for the present invention, realized the measurement of online ditch depth, be suitable for volume production.Simultaneously, the ground floor polycrystalline silicon deposition process that has mixed when having abandoned original 530 ℃ changes employing at 620 ℃ of plain ground floor polysilicons of following deposit, and the groove of 90 degree is filled, this ground floor polysilicon mixed the ground floor polysilicon after last etching is mixed thereafter.In the above-mentioned technology, because of deposit ground floor polysilicon under higher temperature, at first having solved original ground floor polysilicon that mixes simultaneously can't spend the problem that grooves are closely filled to 90; Secondly, ground floor polysilicon after the doping is after anti-carving, its surperficial roughness relatively with original technology in roughness behind the ground floor etching polysilicon improved significantly, and increased substantially and anti-carved the uniformity of back ground floor polysilicon surface to the trench top degree of depth, thereby the membranous of next step middle-high density plasma oxide film improved, tightr, finally improve the puncture voltage between two-layer polysilicon, and the uniformity of device electrical performance is also improved greatly.This invents after the described etching that ground floor polysilicon surface roughness is greatly improved is because very little and very even at 620 ℃ of plain ground floor polysilicon grains of following deposit, then by use POCl under 900 ℃ ₃Mix, because the effect of impurity, it is a lot of that polysilicon grain is increased, thereby improved the surface smoothness after the ground floor polysilicon anti-carves.

With gate oxide is that the groove type double-layer grid power MOS device of 450 dusts is an example, the puncture voltage of its gate oxide is designed to more than the 36V, but the power MOS (Metal Oxide Semiconductor) device puncture voltage of prior art for preparing is about 15V, and the power MOS (Metal Oxide Semiconductor) device puncture voltage that adopts method of the present invention preparation is between 36V to 40V, so the present invention can effectively improve the puncture voltage between two-layer polysilicon, makes it no longer become the bottleneck that the groove type MOS device further develops.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and specific implementation method:

Fig. 1 is a groove type double-layer grid power MOS device partial cross section structural representation;

Fig. 2 is after anti-carving the ground floor polysilicon in the existing technology, forms the schematic diagram of ground floor polysilicon wedge angle at trenched side-wall.

Specific implementation method:

The concrete technology of groove type double-layer grid power MOS device of the present invention manufacturing comprises:

The etching of (1) 90 degree groove;

Groove preparation technology is that elder generation exposes the position that needs etching groove with the photoetching of trench lithography version, etches 90 degree grooves again.

(2) growth of thick grating oxide layer (SHIELD GATE OXIDE);

Thick grating oxide layer comprises the thermal oxide layer of about 500 dusts and the high temperature oxide layer (HTO) of about 1100 dusts, and wherein high temperature oxide layer can adopt the high-temperature low-pressure chemical vapor deposition method.

(3) filling of plain ground floor polysilicon in groove; Adopt low-pressure chemical vapor deposition process, at 620 ℃ of plain ground floor polysilicons of following deposit.

(4) the ground floor polysilicon is carried out phosphorus doping;

Under 900 ℃, use POCl ₃Be doped source, this ground floor polysilicon mixed that doping time and concentration can be adjusted according to the electric property that this ground floor polysilicon requires.

(5) follow-up preparation technology can be according to the difference of specific embodiments and difference, the typical process that anti-carves for the ground floor polysilicon after mixing below;

Adopt polysilicon that oxide layer is selected than high etching condition, with the stop layer of thick grating oxide layer as etching, dry etching ground floor polysilicon is to groove.The concrete operations flow process is: the ground floor polysilicon (it is thick to can be 4000 dusts in concrete the enforcement) that former head's etching groove surface is above, the back is to look for the terminal point form to be etched to the thick grating oxide layer surface, next again with the identic process conditions over etching of terminal point groove in ground floor polysilicon (approximately to the following 0.6um in silicon plane place), at last with ground floor polysilicon in isotropic etching technics etching groove (approximately to the following 1um in silicon plane place), and scabble the uneven of polycrystalline surface.Here the ground floor polysilicon thickness that need etch away is decided by concrete technological requirement, waits by etch period and etch rate and controls.

(6) follow-up channel body, source electrode, contact hole, preparation technology is identical in the preparation technology of metal level and passivation layer etc. and the original technology.

Claims

1. method that improves the groove type double-layer grid power MOS puncture voltage between two polysilicons, this power MOS (Metal Oxide Semiconductor) device preparation technology comprise the growth of the deposit of the deposit of etching groove, ground floor polysilicon and etching, high-density plasma oxide-film and etching, gate oxide growth, second layer polysilicon and etching, and channel body, source region, contact hole, metal level, passivation layer form, it is characterized in that:

(1) described groove is 90 degree grooves;

(2) deposit of described ground floor polysilicon and etching technics are: earlier at 620 ℃ of plain polysilicons of following deposit, POCl is used in the back under 900 ℃ ₃For doped source is carried out phosphorus doping to described plain polysilicon, the polysilicon after last etching is mixed.