CN115810546A

CN115810546A - Manufacturing method of shielded gate trench MOSFET with high-k dielectric

Info

Publication number: CN115810546A
Application number: CN202211693751.7A
Authority: CN
Inventors: 麻泽众; 杨乐; 李铁生; 陈桥梁
Original assignee: Longteng Semiconductor Co ltd
Current assignee: Longteng Semiconductor Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-03-17

Abstract

The invention discloses a manufacturing method of a shielded gate trench MOSFET with a high-k dielectric, which comprises the following steps: growing an epitaxial layer over a substrate; forming a hard mask structure consisting of a first oxide layer, a silicon nitride dielectric layer and a second oxide layer which are sequentially stacked; forming a groove by photoetching; depositing a side wall oxide layer in the groove; depositing and etching back to form source electrode polycrystalline silicon; etching the side wall oxide layer to a target depth by a wet method; depositing a high-k dielectric layer to fill the groove and etching back to a target depth; depositing to generate an oxide layer to backfill the trench; removing the oxide layer above the silicon nitride, and etching the oxide layer by a wet method to form an isolation oxide layer; forming a grid oxide layer by adopting a thermal oxidation process; and forming gate polysilicon. The invention can enhance the charge coupling effect of the source polysilicon and the drift region by using the high-k dielectric, so that the longitudinal electric field distribution of the drift region is more uniform, the breakdown voltage of the device is further improved, and the better specific on-resistance and gate-to-drain charge are realized.

Description

Manufacturing method of shielded gate trench MOSFET with high-k dielectric

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to a manufacturing method of a shielded gate trench MOSFET with a high-k dielectric.

Background

In the field of medium and low voltage power devices, a shielded gate trench MOSFET (SGT MOSFET) utilizes a two-dimensional charge coupling effect to realize low on-resistance under the condition of high doped epitaxial layer concentration, and breaks through the silicon limit theory of the traditional power MOSFET. Meanwhile, the shielding grid structure has smaller grid-drain capacitance, the switching frequency of the device is improved, and the SGT MOSFET with excellent performance gradually becomes a mainstream device in the market.

Fig. 1 is a schematic diagram of a conventional SGT MOSFET structure in which a polysilicon layer is present deep into the trench and connected to a source electrode. The source polysilicon acts like an in-body field plate, depleting the drift region by a thicker trench sidewall oxide layer. This will introduce a new electric field peak near the trench bottom of the drift region, change the longitudinal electric field from triangular distribution to catenary distribution, i.e., there is an electric field valley in the middle of the drift region. The non-uniformity of the longitudinal electric field becomes more severe as the depth of the trench increases, resulting in the source polysilicon not achieving perfect charge coupling. Therefore, the conventional SGT MOSFET is only suitable for the voltage range within 200V, and its structural features obviously hinder its development.

Disclosure of Invention

In order to solve the problems, the invention provides a manufacturing method of an SGT MOSFET with a high-k medium, which can solve the problem of nonuniform longitudinal electric field distribution of a drift region. And depositing a side wall oxide layer in the deep trench, etching back to the middle position of the drift region, depositing a high-k insulating medium, etching back and keeping a certain length, depositing an oxide layer by adopting high-density plasma, and etching back the oxide layer to simultaneously form a side wall oxide layer and an isolation oxide layer near the top of the source electrode polycrystalline silicon. The trench sidewall insulating dielectric presents a sandwich structure of an oxide layer, a high-k dielectric layer and an oxide layer along the longitudinal direction.

The source polysilicon in the middle of the drift region can enhance charge coupling with the drift region through the high-k dielectric, and when the device is in an off state, more positively charged donor ions in the middle of the drift region terminate with induced negative charges of the source polysilicon, so that a valley electric field in the middle of the drift region is pulled high. By reasonably controlling the dielectric constant and the length of the high-k medium, the valley electric field and the peak electric field intensity at two ends of the drift region can be kept consistent, so that the overall longitudinal electric field distribution is more uniform, and the breakdown voltage of the device is improved.

Under the condition of ensuring that the breakdown voltage is not changed, the doping concentration of the epitaxial layer needs to be increased to be matched with stronger charge coupling, so that the on-resistance is further reduced. In addition, the high-k medium generates stronger charge coupling effect, which is equivalent to improving the charge shielding effect of the source polysilicon on the grid, and can reduce the parasitic capacitance C generated between the grid and the drain _gd 。

The manufacturing method of the SGT MOSFET with the high-k dielectric comprises the following steps:

the method comprises the following steps: growing an epitaxial layer on a silicon substrate;

step two: sequentially forming a hard mask layer consisting of a first oxide layer, a silicon nitride layer and a second oxide layer on the surface of the epitaxial layer;

step three: etching the hard mask layer and the epitaxy in sequence by adopting a photoetching process to form a groove;

step four: forming a side wall oxidation layer inside the groove by adopting a chemical vapor deposition process;

step five: depositing source electrode polycrystalline silicon, and etching the source electrode polycrystalline silicon to a target depth by a dry method;

step six: etching the side wall oxide layer to a target depth by a wet method;

step seven: depositing a high-k insulating medium to fill the groove, etching back the high-k medium and reserving a certain length;

step eight: removing the oxide layer above the silicon nitride layer by adopting high-density plasma chemical vapor deposition, removing the silicon nitride by adopting chemical mechanical polishing, and then etching back the oxide layer to simultaneously form a side wall oxide layer and an isolation oxide layer near the top of the source polysilicon;

step nine: forming a grid oxide layer by adopting a thermal oxidation process, depositing grid polycrystalline silicon and etching back to the position below the silicon surface;

step ten: respectively forming a P-type base region and an N-type source region through ion implantation and high-temperature annealing;

step eleven: forming an interlayer medium, a contact hole and a front metal layer, and carrying out imaging on the front metal layer to lead out a grid and a source;

and then, a passivation layer is required to be deposited, and the passivation layer is etched by adding the mask to form a metal lead region. And finally, thinning the substrate and carrying out a back gold process.

The invention can optimize the electric field distribution of the drift region by increasing the deposition and etching processes of the high-k dielectric, and has the advantages of simple process, less process steps and lower cost. And the on-resistance and the parasitic capacitance can be further improved, so that the performance is more excellent, and the application range of the capacitor is expanded.

Drawings

The invention is described in further detail below with reference to the accompanying drawings and specific embodiments:

fig. 1 is a schematic structural diagram of a conventional shielded gate trench MOSFET;

FIG. 2 is a schematic diagram of the structure of a shielded gate trench MOSFET with a high-k dielectric according to the present invention;

FIGS. 3-12 are schematic process flow diagrams of the fabrication of a shielded gate trench MOSFET with a high-k dielectric in accordance with the present invention;

fig. 13 is a graph comparing the longitudinal electric field of an embodiment of the present invention and a conventional shielded gate trench MOSFET.

Detailed Description

The insulating layers on the side walls of the trenches corresponding to fig. 1 and fig. 2 have uniform thickness, and the electric field distribution of the device can be further optimized by setting the insulating layer in the middle of the trench to be a high-k dielectric material with high dielectric constant, so that the breakdown voltage of the device can be further improved, and better specific on-resistance can be realized.

Preferably, the device structure is based on the voltage-resistant specification, and the selectable high-k dielectric material comprises silicon nitride, aluminum oxide, silicon oxynitride and the like.

As shown in fig. 3 to fig. 12, this embodiment provides a method for manufacturing a shielded gate trench MOSFET with a high k dielectric, where the device may be an N-type device or a P-type device, and the embodiment is described by taking an N-type device as an example. The manufacturing method comprises the following steps:

step one, as shown in fig. 3, a substrate is provided, and an epitaxial layer is grown on the upper surface of the substrate.

Step two, as shown in fig. 4, a first thin oxide layer is thermally grown on the surface of the epitaxial layer, a silicon nitride layer is deposited, and a second thick oxide layer is deposited to form a hard mask layer. The first oxide layer acts to relieve stress of the silicon nitride layer. The silicon nitride layer is a stop layer of a subsequent chemical mechanical polishing process.

And step three, as shown in fig. 5, etching the hard mask layer and the epitaxial layer in sequence by adopting a photoetching process to form a groove, wherein the bottom of the groove needs to be subjected to arc treatment.

And step four, as shown in fig. 6, forming a side wall oxide layer on the side surface and the bottom surface of the trench by adopting a deposition mode. The thickness of the side wall oxide layer is 2000-10000 angstroms.

Step five, as shown in fig. 7, polysilicon is filled in the trench, and source polysilicon is formed by etching back, with a depth of about 1 micron to 1.5 microns.

And step six, as shown in fig. 8, etching the side wall oxide layer inside the trench to a target depth by adopting wet etching, and simultaneously removing the thick oxide layer above the epitaxial layer.

Step seven, as shown in fig. 9, filling the high-k dielectric inside the trench, and etching back to the target depth. The high k dielectric has a length of about 0.5 to 5 microns.

Step eight, as shown in fig. 10, filling an oxide layer inside the trench by high-density plasma chemical vapor deposition, removing the oxide layer above the silicon nitride layer by chemical mechanical polishing, then removing the silicon nitride, and then etching back the oxide layer to simultaneously form a sidewall oxide layer and an isolation oxide layer near the top of the source polysilicon.

The step coverage of the high-density plasma chemical vapor deposition process is good, the groove can be filled well, and the generation of holes is prevented. The surface of the isolation oxide layer can be kept flat by combining the chemical mechanical polishing process.

Step nine, as shown in fig. 11, a gate oxide layer is formed by using a thermal oxidation process, and gate polysilicon is backfilled and etched below the silicon surface to form a gate of the device.

Step ten, as shown in fig. 12, a P-type base region and an N-type source region are respectively formed by ion implantation and high-temperature annealing. The P-type base region forms a channel region, and the surface of the channel region covered by the side face of the grid polycrystalline silicon is used for forming a channel. And the N-type epitaxial layer at the bottom of the channel region forms a drift region.

Step eleven, forming an interlayer medium, a contact hole and a front metal layer, carrying out imaging on the front metal layer to lead out a grid electrode and a source electrode, and finally forming a structure as shown in fig. 2.

In order to form a complete shielding grid power device, a passivation layer needs to be deposited subsequently, and the passivation layer is etched by adding a mask to form a metal lead region. And finally, carrying out substrate thinning and back gold process, and leading out the drain electrode from the back metal.

In addition, in practice, the outer side of the shielding grid power device cell structure further comprises a source electrode lead-out region and a gate electrode lead-out region. The source electrode lead-out area only has one piece of source electrode polycrystalline silicon, is connected with the source electrode polycrystalline silicon of the cellular area and is connected to source electrode metal through a contact hole above the groove of the source electrode lead-out area. The upper polycrystalline silicon and the lower polycrystalline silicon are arranged in the gate electrode lead-out area, and the upper gate polycrystalline silicon is connected with the gate polycrystalline silicon in the cell area and is connected to gate metal through a contact hole above the groove of the gate electrode lead-out area.

In the embodiment of the invention, the metal material filled in the contact hole is the same as the metal material of the front metal layer; or the metal material filled in the contact hole is different from the metal material of the front metal layer. The metal material of the front metal layer is aluminum, copper aluminum alloy or other metal materials.

In the embodiment of the invention, the gate oxide layer is a thermal oxide film grown in a dry oxygen mode, and the thickness of the gate oxide layer is 100-1000 angstroms. The sidewall oxide layer is formed by a deposition method, or a combination of a thermal oxide film and a deposited oxide film.

As shown in fig. 13, the longitudinal electric field of the device formed by the method of the embodiment of the present invention and the conventional shielded gate trench MOSFET has a curve varying with the position of the drift region, the variation direction is from the top to the bottom of the epitaxial layer, and the abscissa is the electric field strength. The area surrounded by the longitudinal electric field is larger, which shows that the breakdown voltage is larger, so that the doping concentration of the epitaxial layer can be increased to further reduce the on-resistance.

The above examples are provided to illustrate the present invention in detail, but are not to be construed as limiting the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. A method of fabricating a shielded gate trench MOSFET having a high k dielectric, comprising the steps of:

step four: forming a side wall oxide layer inside the groove by adopting a chemical vapor deposition process;

step five: depositing source electrode polycrystalline silicon, and etching to a target depth by a dry method;

step six: etching the side wall oxide layer to a target depth by a wet method;

step seven: depositing a high-k insulating medium to fill the groove, etching back the high-k insulating medium and reserving a certain length;

then, a passivation layer is deposited, and the passivation layer is etched by adding a mask to form a metal lead region; and finally, carrying out substrate thinning and back gold process.

2. The method of manufacturing a shielded gate trench MOSFET having a high-k dielectric as claimed in claim 1 wherein: and step three, etching the two sides of the groove at a certain angle, flattening the surface of the side wall, and performing arc treatment on the bottom of the groove.

3. The method of manufacturing a shielded gate trench MOSFET having a high k dielectric as claimed in claim 1 wherein: and seventhly, the high-k dielectric is positioned on two sides of the side wall of the middle groove, and the thickness of the high-k dielectric is consistent with that of the side wall oxide layer.

4. The method of claim 3 wherein said step of forming a shielded gate trench MOSFET with a high k dielectric comprises: the high k dielectric has a thickness of between 0.2 and 1 micron and a length of between 0.5 and 5 microns.

5. A method of fabricating a shielded gate trench MOSFET having a high-k dielectric as claimed in claim 1 or 3 wherein: the groove side wall insulating layer is composed of silicon oxide and silicon nitride, the isolation dielectric layer between the polycrystalline silicon is composed of silicon oxide formed in a deposition mode, and the gate dielectric layer is composed of silicon oxide grown in a dry oxygen mode.

6. The method of claim 5 wherein said step of forming a shielded gate trench MOSFET with a high-k dielectric comprises: the thickness of the isolation oxide layer is between 1000 angstroms and 5000 angstroms.

7. The method of manufacturing a shielded gate trench MOSFET having a high k dielectric as claimed in claim 1 wherein: the grid polycrystalline silicon is connected with the grid through a contact hole, and the source region is connected with the source electrode through the contact hole.

8. The method of manufacturing a shielded gate trench MOSFET having a high k dielectric as claimed in claim 7 wherein: the source polysilicon is connected to the source through the contact hole.