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CN101299908B - 用于制造具有嵌入式元件的印刷电路板的方法 - Google Patents

用于制造具有嵌入式元件的印刷电路板的方法 Download PDF

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Publication number
CN101299908B
CN101299908B CN2008100047958A CN200810004795A CN101299908B CN 101299908 B CN101299908 B CN 101299908B CN 2008100047958 A CN2008100047958 A CN 2008100047958A CN 200810004795 A CN200810004795 A CN 200810004795A CN 101299908 B CN101299908 B CN 101299908B
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China
Prior art keywords
circuit board
insulating barrier
electrode bumps
printed circuit
contact tab
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Expired - Fee Related
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CN2008100047958A
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CN101299908A (zh
Inventor
睦智秀
朴俊炯
金起换
金成容
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明公开了一种用于制造具有嵌入式元件的印刷电路板的方法。该方法包括:在基底基板的一侧上形成至少一个接触凸块和至少一个电极凸块;安装元件,使得电极凸块与元件的接触端子相对应;在基底基板的所述一侧上叠置其中形成有对应于元件的开口的绝缘层,使得接触凸块穿透绝缘层;将填充物填充到开口中;以及在绝缘层上叠置金属层。利用该方法,可以提高元件与电路图案之间的电路连接的可靠性,并且可以减少将元件嵌入到印刷电路板中的制造工序。

Description

用于制造具有嵌入式元件的印刷电路板的方法
相关申请交叉参考
本申请要求2007年4月30日向韩国知识产权局提交的第10-2007-0041983号韩国专利申请的权益,其公开内容整体结合于此作为参考。
技术领域
本发明涉及一种用于制造具有嵌入式元件的印刷电路板的方法。
背景技术
具有嵌入式元件的印刷电路板作为下一代多功能微型封装技术的一部分,其发展目前受到了关注。在提供了多功能性和微型尺寸这些优点的同时,具有嵌入式元件的印刷电路板由于其可在100MHz或更高的频率下使得布线距离最小化,因此还提供了更高的性能表现,并且在一些情况下,该印刷电路板可利用FC(倒装芯片)组件和BGA(球栅阵列)中所使用的引线接合或焊球来提高各部件(part)连接的可靠性。
图1A至图1G是示出了根据现有技术制造具有嵌入式元件的印刷电路板的方法的流程图的各横截面视图。为了根据现有技术制造具有嵌入式元件的印刷电路板,首先制造印刷电路板,在该印刷电路板中形成导通孔102以实现层之间的电连接,并且在印刷电路板的任一侧上形成电路图案104。之后,在将要嵌入元件110的位置穿孔形成空腔(cavity)106,并且在穿孔的空腔106的下表面上叠置第一绝缘体108,以通过空腔106而将元件110插入并固定在第一绝缘体108上。当元件110固定在印刷电路板中时,将第二绝缘体112叠置在印刷电路板上。
接着,在第一绝缘体108和第二绝缘体112中穿孔形成导通孔114以实现与元件的接触端子118的电连接,并且涂覆铜镀层116。这里,使得接触端子118面对印刷电路板的上表面,并且在叠置了第二绝缘体112之后,在与元件的接触端子118相对应的位置处形成导通孔114。
这样,根据现有技术制造具有嵌入式元件的印刷电路板的方法必然是非常复杂的制造工艺,其包括如下的过程,即,首先制造在两侧上具有电路图案且具有用于层间连接的导通孔的印刷电路板、穿孔形成空腔、嵌入元件、并形成导通孔以将元件的接触端子与电路图案电连接。
发明内容
本发明的一个方面在于提供一种用于制造具有嵌入式元件的印刷电路板的方法,该方法减少了制造工序并提高了电路连接的可靠性。
本发明的一个方面提供了一种用于制造具有嵌入式元件的印刷电路板的方法。该方法包括:在基底基板的一侧上形成至少一个接触凸块以及至少一个电极凸块;安装元件,使得电极凸块与元件的接触端子相对应;在基底基板的一侧上叠置具有对应于元件而形成的开口的绝缘层,使得接触凸块穿透绝缘层;将填充物填充到开口中;以及在绝缘层上叠置金属层。
用于制造具有嵌入式元件的印刷电路板的该方法可以进一步包括:通过选择性地去除金属层而形成电路图案。
而且,如果基底基板是金属板,则可以进一步包括通过选择性地去除金属板而形成电路图案的操作。
在安装了元件之后,可以进一步包括固化接触凸块和电极凸块的操作。
形成接触凸块和电极凸块的步骤可以包括在基底基板的一侧上叠置形成有多个通孔的掩模;在掩模上涂覆导电糊剂并进行刮压(squeegeeing);以及去除掩模。
所述多个通孔可以对应于接触凸块和电极凸块而形成,其中,对应于接触凸块的通孔可以大于对应于电极凸块的通孔。
掩模可以由不锈钢或铝(Al)制成。
导电糊剂可以包含选自由金、银、铂、镍、铜、及碳组成的组中的至少一种或多种元素。
基底基板可以是其中形成有电路图案的电路板。
本发明的其它方面和优点将在以下的描述中部分地得到阐明,并且从这些描述中将部分地变得显而易见,或者通过对本发明的实践而获知。
附图说明
图1A、图1B、图1C、图1D、图1E、图1F和图1G是示出了根据现有技术制造具有嵌入式元件的印刷电路板的方法的流程图的横截面视图。
图2是根据本发明实施例的制造具有嵌入式元件的印刷电路板的方法的流程图。
图3A、图3B、图3C、图3D、图3E、图3F和图3G是示出了根据本发明实施例的制造具有嵌入式元件的印刷电路板的方法的流程图的横截面视图。
图4是根据本发明另一实施例的具有嵌入式元件的印刷电路板的横截面视图。
具体实施方式
以下将参照附图更详细地描述根据本发明某些实施例的制造具有嵌入式元件的印刷电路板的方法,其中,与图号无关,相同或相对应的那些元件以相同的参考标号表示,并省略多余的描述。
图2是根据本发明实施例的制造具有嵌入式元件的印刷电路板的方法的流程图,图3A至图3G是示出了根据本发明实施例的制造具有嵌入式元件的印刷电路板的方法的流程图的横截面视图。在图3A至图3G中示出了通孔11、掩模12、金属板14、接触凸块16、电极凸块18、元件20、接触端子21、绝缘层22、填充物24、金属层26、以及电路图案28。
根据本实施例的制造具有嵌入式元件的印刷电路板的方法可以包括:在基底基板的一侧上形成接触凸块16和电极凸块18;安装元件20,使得元件20的电极和电极凸块18相对应;在基底基板的一侧上叠置具有对应于元件20而形成的开口的绝缘层22,使得接触凸块16穿透绝缘层22;用填充物24填充开口;以及在绝缘层22上叠置金属层26。可以使用该方法来减少将元件20嵌入到印刷电路板内部时的制造工序并提高元件20与电路图案28之间的电路连接的可靠性。
在根据本实施例的制造具有嵌入式元件的印刷电路板的方法中,首先,如图3B所示,可以在基底基板的一侧上形成接触凸块16和电极凸块18(S100)。基底基板可以是其中形成有电路图案的电路板或者可以是金属板14。即,可以将根据本实施例的具有嵌入式元件20的印刷电路板添加至已经具有电路图案的电路板上,以形成具有嵌入式元件20的多层印刷电路板。可替换地,可以在金属板14上安装元件20以制造具有嵌入式元件20的印刷电路板。
针对用于嵌入式元件20以制造印刷电路板的方法而描述本实施例,其中基底基板是金属板14。
金属板14可用来通过后续的选择性蚀刻工艺来形成电路图案28,并且可以通过将能够导电的金属加工成板状而制造该金属板。铜板可用于金属板14。
在随后叠置绝缘层22时,可以使接触凸块16穿透绝缘层22,并且在后续的处理中,可以使接触凸块16电连接形成于绝缘层22的一侧和另一侧上的电路图案28。
电极凸块18可用来在嵌入于印刷电路板中的元件20的接触端子21与电路图案28之间进行电连接,由此电极凸块18可以形成在与稍后安装的元件20的接触端子21对应的位置中。因此,电极凸块18可以形成为使得电极凸块18与元件20的接触端子21彼此面对。
在金属板14上形成接触凸块16和电极凸块18的方法可以包括:首先,如图3A所示,在金属板14的一侧上叠置具有多个通孔11的掩模12(S101)。当掩模12叠置在金属板14上时,多个通孔11可以形成在与接触凸块16和电极凸块18将形成在金属板14上的位置相对应的位置中。这里,用于形成接触凸块16的通孔11可以大于用于形成电极凸块18的通孔11。由于接触凸块16可以形成为穿透叠置在金属板14上的绝缘层22,而电极凸块18可以形成为与嵌入在绝缘层22中的元件20的接触端子21电连接,所以用来形成电极凸块18的通孔11可以小于用来形成接触凸块16的通孔11。
掩模12可以由具有低伸长率(elongation ratio)的诸如不锈钢和铝等的金属材料制成。
在将掩模12叠置在金属板14上之后,可以在掩模12上涂覆导电糊剂(未示出)并且可以进行刮压(S102)。刮压可以迫使导电糊剂进入到多个通孔11中。
可将导电糊剂制成为导电颗粒的混合物,其包括选自由金、银、铂、镍、铜、碳等组成的组中的至少一种或多种导电材料以及合成树脂或环氧树脂。合成树脂或环氧树脂可以用作用于粘结导电颗粒的粘结剂。这里,可以使用金属粘结剂以及有机粘结剂。铋(Bi)等可以用作金属粘结剂。当导电糊剂被置于高温和高压下时,导电颗粒可处于彼此接触的状态,因此提高了电传导或热传导。可以在通过金属扩散或固化施加热和压力的同时获得导电性质。
当通过刮压迫使导电糊剂进入所述多个通孔11时,可以从金属板14上去除掩模12,从而将导电糊剂转移到金属板14上,由此可以形成接触凸块16和电极凸块18(S103)。为了使导电糊剂可容易地与掩模12分离并转移到金属板14上,可以在涂覆导电糊剂之前向掩模12涂覆脱模材料。
接着,如图3C所示,可以将元件20安装到金属板14的电极凸块18上,使得形成在金属板14上的电极凸块18与元件20的接触端子21彼此对应(S200)。可以在印刷电路板中嵌入诸如电阻器、电容器、集成电路、半导体芯片等各种类型的元件20作为本实施例的元件20。
因此,通过将各种类型的元件20嵌入到印刷电路板中,可以减小电路板的面积,并且可以高密度地利用这些元件20,从而可以实现需要高速运行的电子设备,诸如移动终端和便携式电脑等。
接着,可以固化接触凸块16和电极凸块18(S300)。由于接触凸块16会在随后穿透绝缘层22,因此可以将接触凸块16固化至特定硬度以上,并且由于电极凸块18被设置成与元件20的接触端子21相对应,所以可以固化电极凸块18以增加电极凸块18与元件20的接触端子21之间的粘结。
接着,如图3D所示,可以在金属板14的安装有元件20的一侧上叠置绝缘层22,该绝缘层具有形成在对应于元件20的位置中的开口,从而接触凸块16穿透绝缘层22(S400)。这里,绝缘层22可以包含热塑树脂和玻璃环氧树脂中的至少一种,并且当被叠置时该绝缘层可以处于可软化状态。例如,通过将温度升高至高于热塑树脂或玻璃环氧树脂的软化温度,可以使绝缘层22可软化,之后可以叠置绝缘层22,使得接触凸块16穿透绝缘层22。还可以将半固化片用于绝缘层22,其中将玻璃纤维浸渍热固树脂中以提供半固化状态。
同时在绝缘层22的对应于元件20的位置中形成开口。由于元件20可以安装在金属板14上,所以可以将具有预先形成的开口的绝缘层22叠置在金属板14上,从而可以通过该开口露出元件20。绝缘层22可以形成得足够厚,使得安装在电极凸块18上的元件20可以在后来充入填充物24时被嵌入到绝缘层22中。
接着,如图3E所示,可以将填充物24填充到从中露出元件20的开口中(S500)。在嵌入了元件20之后,可以将填充物24填充到开口内剩余的空间中。诸如环氧树脂等的绝缘材料可用于填充物24。通过使用填充物24,可以牢固地固定元件20,并可以将元件嵌入到绝缘层22内。
接着,如图3F所示,可以在绝缘层22上叠置金属层26(S600)。叠置金属层26的方法可以包括附着金属面板或通过镀覆等沉积金属,以形成金属层26。稍后可以使用金属层26以通过选择性地蚀刻金属层26来形成电路图案28。
接着,如图3G所示,当金属层26叠置在绝缘层22上时,可以选择性地蚀刻形成在绝缘层22一侧上的金属板14以及形成在绝缘层22另一侧上的金属层26以形成电路图案28(S700)。
图4是根据本发明另一实施例的具有嵌入式元件的印刷电路板的横截面视图。图4中示出了接触凸块16、电极凸块18、元件20、电路图案28、以及电路板32。
在本实施例中,具有电路图案的电路板32可以用作基底基板,以形成一侧上嵌入有元件20的印刷电路板。
在电路板32上,可以形成包括焊盘(land)的电路图案,在焊盘上将形成接触凸块16和电极凸块18。接触凸块16和电极凸块18可利用掩模12而形成在这些焊盘上。在安装元件20以使电极凸块18与元件20的接触端子21相对应之后,可以在电路板32上叠置其中形成有开口的绝缘层22。当叠置绝缘层22时,可以将填充物24填充到开口中,并且可以将金属层26叠置在绝缘层22上。之后,可以选择性地蚀刻金属层26以形成电路图案28,从而制造出具有嵌入式元件20的印刷电路板。
虽然本实施例是针对两侧上形成有电路图案的电路板32而描述的,但是使用仅在一侧上形成有电路图案的电路板32也是可行的。也可以利用具有多层电路图案的多层电路板来根据上述方法制造具有嵌入式元件20的印刷电路板。
通过利用如上所述的本发明的某些实施例,可以提高元件与电路图案之间的电路连接的可靠性,并且可以减少将元件嵌入到印刷电路板中的制造工序。
而且,可以减小电路板的面积,并且可以高密度地利用这些元件,从而可以实现需要高速运行的电子设备,诸如移动终端和便携式电脑等。
虽然已经参照具体实施例详细地描述了本发明的精神,但是这些实施例仅为了示例目的,而不用来限制本发明。可以理解,在不背离本发明的范围和精神的前提下,本领域技术人员可以改变或更改这些实施例。

Claims (9)

1.一种用于制造具有嵌入式元件的印刷电路板的方法,所述方法包括:
在基底基板的一侧上形成至少一个接触凸块和至少一个电极凸块;
安装元件,使得所述电极凸块与所述元件的接触端子相对应;
在所述基底基板的所述一侧上叠置绝缘层,使得所述接触凸块穿透所述绝缘层,所述绝缘层中形成有对应于所述元件的开口;
将填充物填充到所述开口中;以及
在所述绝缘层上叠置金属层。
2.根据权利要求1所述的方法,进一步包括:
通过选择性地去除所述金属层而形成电路图案。
3.根据权利要求1所述的方法,其中,所述基底基板是金属板,并且所述方法进一步包括:
通过选择性去除所述金属板而形成电路图案。
4.根据权利要求1所述的方法,在安装所述元件之后进一步包括:
固化所述接触凸块和所述电极凸块。
5.根据权利要求1所述的方法,其中,形成所述接触凸块和所述电极凸块的步骤包括:
在所述基底基板的所述一侧上叠置掩模,所述掩模中形成有多个通孔;
在所述掩模上涂覆导电糊剂并进行刮压;以及
去除所述掩模。
6.根据权利要求5所述的方法,其中,所述多个通孔形成为与所述接触凸块和所述电极凸块相对应,并且其中,
与所述接触凸块相对应的通孔大于与所述电极凸块相对应的通孔。
7.根据权利要求5所述的方法,其中,所述掩模由不锈钢或铝(Al)制成。
8.根据权利要求5所述的方法,其中,所述导电糊剂包含选自由金、银、铂、镍、铜、及碳组成的组中的至少一种或多种元素。
9.根据权利要求1所述的方法,其中,所述基底基板是其中形成有电路图案的电路板。
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JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
KR100945285B1 (ko) * 2007-09-18 2010-03-03 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조 방법
TWI363585B (en) * 2008-04-02 2012-05-01 Advanced Semiconductor Eng Method for manufacturing a substrate having embedded component therein
WO2009147936A1 (ja) * 2008-06-02 2009-12-10 イビデン株式会社 多層プリント配線板の製造方法
US20120280023A1 (en) * 2008-07-10 2012-11-08 Lsi Corporation Soldering method and related device for improved resistance to brittle fracture
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
WO2010024233A1 (ja) * 2008-08-27 2010-03-04 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
US8067306B2 (en) * 2010-02-26 2011-11-29 Stats Chippac Ltd. Integrated circuit packaging system with exposed conductor and method of manufacture thereof
CN101930956B (zh) * 2009-06-22 2013-09-25 日月光半导体制造股份有限公司 芯片封装结构及其制造方法
KR20110037332A (ko) * 2009-10-06 2011-04-13 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR101095130B1 (ko) * 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101149036B1 (ko) * 2010-04-29 2012-05-24 엘지이노텍 주식회사 임베디드 인쇄회로기판용 전자부품 결합 부재 및 이를 이용한 임베디드 인쇄회로기판 및 임베디드 인쇄회로기판 제조 방법
KR101085733B1 (ko) * 2010-05-28 2011-11-21 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR20120026855A (ko) 2010-09-10 2012-03-20 삼성전기주식회사 임베디드 볼 그리드 어레이 기판 및 그 제조 방법
WO2012128269A1 (ja) * 2011-03-24 2012-09-27 株式会社村田製作所 配線基板
KR101231286B1 (ko) * 2011-06-01 2013-02-07 엘지이노텍 주식회사 부품 내장형 인쇄회로기판 및 그 제조 방법
US20130044448A1 (en) * 2011-08-18 2013-02-21 Biotronik Se & Co. Kg Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement
US9627351B2 (en) * 2012-10-22 2017-04-18 Sensor Electronic Technology, Inc. Device electrode formation using metal sheet
JPWO2014091624A1 (ja) * 2012-12-14 2017-01-05 株式会社メイコー 部品内蔵基板および部品内蔵基板の製造方法
KR101472672B1 (ko) * 2013-04-26 2014-12-12 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제조방법
CN103281875A (zh) * 2013-05-28 2013-09-04 中国电子科技集团公司第十研究所 嵌入式电子线路立体组装基板的方法
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR101442423B1 (ko) * 2013-08-14 2014-09-17 삼성전기주식회사 전자부품 내장기판 제조 방법 및 전자부품 내장기판
JP6256741B2 (ja) * 2013-09-18 2018-01-10 日立化成株式会社 半導体素子搭載用パッケージ基板
US20150197062A1 (en) * 2014-01-12 2015-07-16 Zohar SHINAR Method, device, and system of three-dimensional printing
KR102186148B1 (ko) * 2014-02-28 2020-12-03 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
CN105981484B (zh) * 2014-04-10 2018-11-09 株式会社村田制作所 元器件内置多层基板
KR101630435B1 (ko) * 2014-04-21 2016-06-15 주식회사 심텍 임베디드 인쇄회로기판 및 그 제조 방법
WO2016114400A1 (ja) * 2015-01-15 2016-07-21 コニカミノルタ株式会社 配線積層構造体及び配線積層構造体の形成方法
KR102568249B1 (ko) * 2016-01-21 2023-08-18 삼성전기주식회사 인쇄회로기판
WO2018003391A1 (ja) * 2016-06-29 2018-01-04 株式会社村田製作所 部品内蔵基板及びその製造方法、並びに高周波モジュール
DE102017211330A1 (de) * 2017-07-04 2019-01-10 Siemens Aktiengesellschaft Toleranzausgleichselement für Schaltbilder
EP3621107A1 (en) * 2018-09-10 2020-03-11 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component with dielectric layer for embedding in component carrier
CN113645556A (zh) * 2021-08-27 2021-11-12 歌尔微电子股份有限公司 Mems麦克风封装结构及封装方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1147150A (zh) * 1995-07-14 1997-04-09 松下电器产业株式会社 半导体器件的电极结构、形成方法及安装体和半导体器件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3560996B2 (ja) * 1993-12-22 2004-09-02 株式会社東芝 実装用配線板およびこれを用いた実装方法
JPH08264932A (ja) * 1995-03-23 1996-10-11 Hitachi Techno Eng Co Ltd はんだバンプ形成法
JP2003037205A (ja) 2001-07-23 2003-02-07 Sony Corp Icチップ内蔵多層基板及びその製造方法
JP4397152B2 (ja) * 2001-11-30 2010-01-13 クローバー電子工業株式会社 多層配線基板の製造方法
JP4378511B2 (ja) * 2002-07-25 2009-12-09 大日本印刷株式会社 電子部品内蔵配線基板
JP2004335641A (ja) 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
TWI221330B (en) * 2003-08-28 2004-09-21 Phoenix Prec Technology Corp Method for fabricating thermally enhanced semiconductor device
TW200611385A (en) * 2004-09-29 2006-04-01 Phoenix Prec Technology Corp Carried structure of integrated semiconductor element and method for fabricating the same
JP4597631B2 (ja) * 2004-10-13 2010-12-15 大日本印刷株式会社 部品内蔵配線板、部品内蔵配線板の製造方法
JP4792749B2 (ja) * 2005-01-14 2011-10-12 大日本印刷株式会社 電子部品内蔵プリント配線板の製造方法
JP4541187B2 (ja) * 2005-02-28 2010-09-08 大日本印刷株式会社 膜素子内蔵プリント配線板の製造方法、膜素子内蔵プリント配線板

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1147150A (zh) * 1995-07-14 1997-04-09 松下电器产业株式会社 半导体器件的电极结构、形成方法及安装体和半导体器件

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