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CN101278401A - 具有低电阻和电感的高电流半导体装置系统 - Google Patents

具有低电阻和电感的高电流半导体装置系统 Download PDF

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Publication number
CN101278401A
CN101278401A CNA2006800360547A CN200680036054A CN101278401A CN 101278401 A CN101278401 A CN 101278401A CN A2006800360547 A CNA2006800360547 A CN A2006800360547A CN 200680036054 A CN200680036054 A CN 200680036054A CN 101278401 A CN101278401 A CN 101278401A
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China
Prior art keywords
copper
wire
lead
circuit
substrate
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CNA2006800360547A
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English (en)
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安东尼·L·科伊尔
伯恩哈德·P·朗格
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN101278401A publication Critical patent/CN101278401A/zh
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Abstract

本发明涉及一种具有低电阻和低电感的高电流半导体装置(例如用于30A到70A的QFN)，所述高电流半导体装置由模制化合物(401，具有约0.9mm的高度402)加以囊封，使得第二引线表面(110b)保持未囊封。可使用导热性粘合剂(403)将铜散热嵌片(404)附接到芯片表面(101b)。由外涂层(103)保护的芯片表面(101a)具有敷金属迹线(102)。经铜填充的窗口接触所述迹线和平行于所述迹线的铜层(105)。铜凸块(108)以有序和重复的布置形成在每一线路上，使得一个线路的凸块大约定位在相邻线路的凸块之间的中间。衬底具有与所述线路以直角定向的延长引线(110)；所述引线连接交替线路的相应凸块。

Description

具有低电阻和电感的高电流半导体装置系统
技术领域
本发明大体涉及半导体装置和过程；且更具体而言，涉及高性能倒装芯片半导体装置，所述高性能倒装芯片半导体装置具有低电阻且可提供高功率、低噪声以及高速度。
背景技术
集成电路(IC)技术中的盛行趋势是装置朝着更高集成度(以缩减组件特征大小)及更高速度发展。另外，保持成本/性能比处于控制之下存在巨大压力，而这又常常转化成寻找较低成本解决方案的驱动力。更高水平的集成度包括需要更高数目的信号线和电力线，然而较小的特征大小使得保持清洁信号而不相互干扰越来越困难。
这些趋势和要求不仅支配并入IC的半导体芯片，而且支配容纳和保护IC芯片的封装。
与传统线接合组装相比，以下事实使得倒装芯片组装在硅集成电路(IC)装置的制造过程流程中越来越受欢迎。第一，当与传统线接合互连技术相关的寄生电感降低时，半导体装置的电性能通常可得到改进。第二，与线接合相比，倒装芯片组装通常在芯片与封装之间提供更高的互连密度。第三，在许多设计中，与线接合相比，倒装芯片组装消耗更少的硅“板面空地”，并因此有助于节约硅面积并降低装置成本。及第四，当采用同时群点接合技术而非连续的个别接合步骤时，常常可降低制造成本。
所述制造过程中的标准球接合方法使用焊料球、或凸块、及其回流技术。这些互连方法比线接合更昂贵。另外，在对附接有焊料球装置的某些应力和使用寿命测试中存在严重的可靠性问题。产品经理不仅需要更高性能的倒装芯片组装产品，而且其也需要更低成本和更高可靠性的线接合装置。
发明内容
申请者认识到，需要开发一种技术方法，所述技术方法考虑由半导体芯片、装置封装以及外部板组成的完整系统以提供包括低电阻和电感、高可靠性和低成本的卓越产品特性。最小电感和噪声是高速度的必要条件，且降低的电阻是高功率的必要条件。系统范围内的组装方法还应提供机械稳定性和高产品可靠性，尤其是在加速应力测试(温度循环、坠落测试等)中。制造方法应足够灵活，以应用于不同的半导体产品族(包括衬底和板)，以及较宽范围的设计和过程变化。
本发明的一个实施例是具有低电阻和低电感的高电流半导体装置。芯片具有带敷金属迹线的有源表面；有源芯片表面由绝缘外涂层保护。外涂层中的窗口暴露敷金属迹线的若干部分；所述窗口经铜填充以形成到达所述敷金属的触点。所述外涂层上的铜层形成平行于所述外涂层下面的迹线的线路；所述层与填充有金属的窗口接触。铜凸块以有序和重复的布置形成于每一线路上，使得一个线路的凸块大约定位在相邻线路的凸块之间的中间。具有第一和第二表面的衬底具有延长铜引线；所述引线与所述线路以直角定向。每一引线的第一表面使用焊料元件连接交替线路的相应凸块。模制化合物囊封已组装的装置和衬底，使得第二衬底表面的引线保持暴露。
在一些装置中，所述衬底是铜引线框架，在另一些装置中，是带状或块状绝缘体。在其它装置中，散热嵌片附接到芯片以帮助冷却高功率装置。所述铜层具有约10μm与15μm之间的厚度，且铜凸块具有约30μm与70μm之间的高度。根据本发明的装置可小于1mm厚；所述装置的低电阻使其能够处置15A与30A之间的电流，某些装置的目标是处置60A及更高的电流。低电感提供低电噪声。
本发明的另一实施例是具有低电阻和低电感的高电流电子系统。所述系统使用上述半导体装置，并采用具有平行于所述装置的铜衬底引线的铜接触垫的电路板。所述引线的暴露表面通过焊料层附接到所述板垫。
附图说明
图1是根据本发明的未囊封半导体装置的一部分的示意性剖面图。
图2是根据本发明的未囊封半导体装置的一部分的示意性透视三维图。
图3是供图1和图2中的装置使用的衬底(引线框架)的俯视图。
图4是附接有散热嵌片的经囊封高电流半导体装置的示意性剖面图。
图5是组装在电路板上的经囊封高电流半导体装置的示意性剖面图。
图6是组装在电路板上附接有散热嵌片的经囊封高电流半导体装置的示意性剖面图。
具体实施方式
图1示意性显示通常标示为100的高电流半导体装置，其具有低电阻和低电感。基于这些特征，一些实施例可处置约15A到30A的电流，其它实施例可处置高达60A及更高的电流。半导体芯片101具有有源表面101a和与所述有源表面相对的表面101b。芯片101含有多个敷金属层级。最靠近表面101a的金属层级被配置成迹线；在图1中，所述迹线中的一者标示为102；其垂直于纸面伸展。迹线102可由铝、铝合金、铜或铜合金组成；迹线102的厚度优选地在约0.5μm与1.0μm之间。整个有源表面101a由绝缘外涂层103覆盖，优选地在约0.5μm到1.0μm之间的厚度范围内。外涂层103的材料优选地选自由氮化硅、氮氧化硅、氧化硅、这些化合物中两种化合物的堆叠、或其它机械性较强并防湿的材料组成的群组。
沿金属迹线102是位于外涂层103中的多个窗口。图1图解说明宽度104的窗口。这些窗口暴露敷金属迹线102的若干部分。如图1所指示，用铜将诸如104等窗口填充到外涂层103的高度，以与敷金属102电接触。
在外涂层103上，且因此也在窗口104上，是铜/铜合金层，所述铜/铜合金层构造成平行于外涂层103下面的迹线102伸展的线路105。线路105具有在约10μm与15μm之间的厚度105a。线路105与填充有铜的窗口104接触。所有线路105嵌入层106中，而层106优选地由聚酰亚胺或类似聚合化合物制成，优选地为10μm到20μm之间厚。
在沿每一线路105规律间隔处是聚酰亚胺层106中的宽度107的窗口。选择特定线路105的窗口107，使得其大约位于每一侧上相邻线路的窗口的间隔之间的中间。铜/铜合金凸块108填充窗口107，并与铜线路105接触。凸块108具有高度108a和可焊接表面，所述高度优选地在约30μm与70μm之间。在这种图案的情况下，铜凸块108以规律间隔位于每一铜线路105上；一个特定线路的凸块大约位于每一侧上相邻线路的凸块的间隔中间的中间。使用这种交替序列，形成了两组多个凸块，其中一组多个凸块的凸块位置以预定节律与另一组多个凸块的凸块位置交替。
所述装置进一步包括具有延长铜引线的衬底。图1的实施例图解说明引线110，其具有第一表面110a和第二表面110b。作为实例，具有引线110的衬底可以是具有延长引线的金属引线框架，或包括延长铜引线的带状或块状绝缘体。在金属引线框架的实例中，铜引线通常具有在150μm与250μm之间的厚度110c。
引线110与线路105以直角定向。此外，第一引线表面110a附接到凸块108，使得引线110连接交替线路的相应凸块。所述连接由焊料元件109提供。优选地，焊料元件109的厚度109a在约10μm与25μm之间；为了增强导电性，优选为使厚度109a保持小。如图1所指示，焊料元件109可湿润凸块108的侧表面的至少一部分。焊料元件109含有锡；为容易湿润和可焊接性，其也可含有选自由银、铋、铟、锌、铜、镍、锑及铅组成的群组的金属中的一者或一者以上。
通过图2的透视三维图更为详细地图解说明铜层105、铜凸块108以及铜引线110的相对定位。采用相同的编号来指代图1中相同的物件。半导体芯片标示为101，其有源表面为101a，且所述有源表面上的保护外涂层为103。最接近表面的敷金属图案化成多个迹线102。
图2图解说明填充有铜的与敷金属迹线102相互交替连接的外涂层窗口104。这些交替的填充有铜的窗口由铜线路105连接。绝缘聚合物层106具有用于铜凸块的开口。铜凸块108置于每一位置上的铜线路105上，其中填充有铜的窗口104连接到敷金属102。
通过使用焊料元件109，将凸块108连接到衬底引线110的第一表面110a。引线110与线路105以直角定向。引线110的第二表面110b可用于附接到外部部件。
作为适用于能够应对大于30A的电流的电力装置的衬底的实例，图3呈现大致标示为300的金属四边扁平封装无引线(QFN)引线框架的俯视图。所述引线框架是由0.2mm厚的铜制成。引线301打算用于接地(漏极)，并具有0.5mm的宽度301a；在所述装置经囊封以后，这些引线的第二表面将保持暴露，以支持热装置性能。与引线301交替的是引线302，其打算用于电源(源极)，也为0.5mm宽且也被暴露。装置接触垫303具有0.5mm的间距304。芯片轮廓310尺寸为3.1×4.0mm，装置轮廓320尺寸为6.0×6.0mm。
图1、2及3中对从芯片敷金属到衬底引线的电流路径的说明所突出的是几乎所有使用的金属均是铜，而铜具有优良的导电性(0.596·106Ω-1cm-1)。基于特定电力装置中采用的几何结构，人们可计算所述电流路径所遇到的电阻并将其与所考虑的有源装置的导通电阻进行比较。计算显示对于在典型操作条件下的典型QFN电力装置来说，金属电阻占总电阻的约15％到17％之间，而在最差情况条件下，金属电阻将不会超过总装置电阻的25％。因此，即使是小尺寸的QFN也可应对超过30A的电流。
图1、2及3强调电路径的不足以及所有导体的直径相对较大(并具有高导电性)。这些条件不仅使电阻较低，而且也使电感较小。
图4图解说明囊封之后的已完成的电力装置。模制化合物401或另一囊封材料囊封图1的已组装装置和衬底，使得第二引线表面100b保持未囊封且因此可用于附接到外部部件。作为一实例，对于高功率QFN(大于30A电流)来说，总装置高度402可以是0.9mm。
在一个实施例中，与有源芯片表面101a相对的芯片表面101b由模制化合物覆盖。在另一实施例中，散热嵌片404使用导热性粘合剂403附接到芯片表面101b。在图4的装置中，散热嵌片404具有用于附接到芯片表面101b的第一表面404a、及出于冷却目的而暴露到周围环境的第二表面404b。在其它装置中，第二嵌片表面404b由一定量的囊封材料覆盖。优选地，散热嵌片由铜制成，因为铜具有良好的导热性(4.01W·cm-1·K-1)。针对额外的热增强，面向周围环境的嵌片表面可构造成增强对流，使得装置热量更有效地转移到作为最终散热器的周围环境；实例包括粗糙的嵌片表面及附接的鳍片或其它堡状物。
图5和图6中所图解说明的本发明的另一实施例是具有低电阻和低电感的高电流电子系统。所述系统包括通过薄焊料层焊接到电路板的半导体装置。在图5中，所述系统大致标示为500，半导体装置为501，电路板为520，且焊料层为530。所述焊料层优选地具有约10μm与20μm之间的厚度。
所述半导体装置包含具有敷金属迹线(图5中未示出)的芯片502。所述迹线通过平行于所述迹线的铜线路503进行接触。每一线路503具有呈有序和重复布置形式的铜凸块504，使得一个线路的凸块大约定位在相邻线路的相应凸块之间的中间。通过使用焊料元件505，交替线路的相应凸块通过衬底的延长铜引线506来接触；引线506与线路503以直角定向。模制化合物507囊封已组装装置和衬底，使得所述引线的一个表面保持未囊封。
电路板520具有平行于引线506的铜接触垫521。所述引线的未囊封表面通过焊料层530附接到板垫521。对于低电阻，焊料层530优选地保持薄，因为其导电性低于铜的导电性。如图5所指示，板520可具有位于其与装置附接表面相对的表面上的另一组接触垫522。这些额外的一组垫可用于施加压力或用作到达额外的外部部件的焊料触点。
图6描绘具有低电阻和低电感的高电流电子系统。所述系统(通常标示为600)包括半导体装置601，其具有附接到芯片604且并入到模制封装605中(进一步并入到电路板620)的散热嵌片603。所述装置通过焊料层630附接到板620。
尽管已参照说明性实施例对本发明进行了描述，但不应将磁说明理解为具有限定意义。在参照本说明后，所属技术领域的技术人员将明了所述说明性实施例的各种修改和组合以及本发明的其它实施例。

Claims (11)

1、一种具有低电阻和低电感的高电流半导体装置，其包含：
芯片，其具有带敷金属迹线的有源表面，所述有源芯片表面由绝缘外涂层来保护；
外涂层窗口，其暴露所述敷金属迹线的若干部分，所述窗口填充有铜以形成到达所述敷金属的触点；
铜层，其位于所述外涂层上，从而形成平行于所述外涂层下面的所述迹线的线路，所述层与所述填充有金属的窗口接触；
铜凸块，其以有序和重复的布置形成在每一线路上，使得一个线路的所述凸块大约定位在相邻线路的相应凸块之间的中间；
衬底，其具有带第一和第二表面的延长铜引线，所述引线与所述线路以直角定向，每一引线的所述第一表面使用焊料元件连接交替线路的相应凸块；及
模制化合物，其囊封所述已组装装置和所述衬底，使得所述第二引线表面保持未囊封。
2、如权利要求1所述的装置，其中所述衬底是具有第一和第二表面的铜引线框架，所述引线与所述线路以直角定向且间隔开，使得每一引线的所述第一表面通过焊料元件附接到交替线路的所述凸块。
3、如权利要求1所述的装置，其中所述衬底是具有带延长铜引线的第一和第二表面的带状或块状绝缘体。
4、如权利要求1所述的装置，其进一步包含具有第一和第二表面的散热嵌片，所述第一嵌片表面附接到与所述有源芯片表面相对的所述芯片表面。
5、如权利要求4所述的装置，其中所述第一嵌片表面附接到与所述有源芯片表面相对的所述芯片表面，使得所述第二嵌片表面不被模制化合物覆盖而是出于冷却目的保持暴露于周围环境。
6、如权利要求1所述的装置，其中所述铜层具有约10μm与15μm之间的厚度。
7、如权利要求1所述的装置，其中所述铜凸块具有约30μm与70μm之间的高度。
8、如权利要求1所述的装置，其中所述焊料元件具有约10μm的厚度。
9、如权利要求2所述的装置，其中所述引线框架由铜制成，且所述引线具有约150μm与250μm之间的厚度。
10、一种具有低电阻和低电感的高电流电子系统，其包含：
半导体装置，其包含：
芯片，其具有带敷金属迹线的有源表面，所述有源芯片表面由绝缘外涂层来保护；
外涂层窗口，其暴露所述敷金属迹线的若干部分，所述窗口填充有铜以形成到达所述敷金属的触点；
铜层，其位于所述外涂层上，从而形成平行于所述外涂层下面的所述迹线的线路，所述层与所述填充有金属的窗口接触；
铜凸块，其以有序和重复的布置形成在每一线路上，使得一个线路的所述凸块大约定位在相邻线路的相应凸块之间的中间；
衬底，其具有带第一和第二表面的延长铜引线，所述引线与所述线路以直角定向，每一引线的所述第一表面使用焊料元件连接交替线路的相应凸块；
模制化合物，其囊封所述已组装装置和所述衬底，使得所述第二引线表面保持未囊封；及
电路板，其具有平行于所述引线的铜接触垫，所述引线的所述第二表面通过焊料层附接到所述板垫。
11、如权利要求10所述的装置，其中所述焊料层具有约10μm与20μm之间的厚度。
CNA2006800360547A 2005-08-22 2006-08-16 具有低电阻和电感的高电流半导体装置系统 Pending CN101278401A (zh)

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