CN101221926A - LCD unit structure and manufacturing method thereof - Google Patents
LCD unit structure and manufacturing method thereof Download PDFInfo
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- CN101221926A CN101221926A CNA2008100010597A CN200810001059A CN101221926A CN 101221926 A CN101221926 A CN 101221926A CN A2008100010597 A CNA2008100010597 A CN A2008100010597A CN 200810001059 A CN200810001059 A CN 200810001059A CN 101221926 A CN101221926 A CN 101221926A
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Abstract
The invention discloses a LCD unit structure and a method for manufacturing the same, wherein, the method comprises following steps that: a patterned first metal layer comprising a first data lead wire segment and a lower grid cushion is formed on a substrate; a patterned dielectric layer is formed, a plurality of first openings are defined on the first data lead wire segment, and a second opening is defined on the lower grid cushion; a patterned second metal layer which comprises a share electrode wire, a second data lead wire segment and an upper grid cushion is formed, wherein, the upper grid cushion is electrically connected with the lower grid cushion through the first openings, and the second data lead wire segment is electrically connected with the first data lead wire segment through the first openings; a patterned protective layer is formed; and a patterned transparent conductive layer is formed. The problem generated by a parasitic capacitance Cpd effect can be prevented by adopting the invention with simple technology and low cost.
Description
Technical field
The present invention relates to a kind of method of making liquid crystal display; Relate in particular to a kind of method that is used for the manufacturing liquid crystal display of LCD.
Background technology
Thin Film Transistor-LCD luminance shortage and backlight power consumption height are the serious problems of making us dirty disease always.One of parameter that influences the LCD illumination effect is pixel aperture ratio, and pixel aperture ratio is defined as the glazed area of pixel and the ratio of elemental area.So the design of pixel aperture ratio directly influences the utilance of backlight, also influence the display brightness of display.Therefore improve pixel aperture ratio in recent years, meaning promptly increases pixel aperture ratio, is very important R﹠D direction.Industry also development new technologies upwards promotes in the hope of the aperture opening ratio that can make LCD, reaches the tool low power consumption but the purpose of the LCD of high brightness.
In the Thin Film Transistor-LCD design, in order to increase aperture opening ratio, one of method of prior art is (generally to be a transparency conductive electrode with pixel electrode (pixel electrode), Indium TinOxide for example) area increases, and overlap with grid circuit and source/drain polar circuit, so can be so that aperture opening ratio increases about 10～20%.But this measure will make pixel electrode be tending towards near data conductor (dataline).If both are too approaching, will further produce excessive parasitic capacitance (parasiticcapacitance) Cpd between the two.Below further specify the influence of parasitic capacitance Cpd.
In the middle of general thin-film transistor element, a dielectric medium with higher dielectric constant, for example SiNx film often are set between pixel electrode and data conductor.Higher dielectric constant will cause Cpd to increase.If the capacitance of parasitic capacitance Cpd is too high, fill full electric charge on the pixel electrode before next frame (frame) conversion with further causing, be subjected to the influence that data conductor transmits different voltages, and produce crosstalk effect (crosstalk).The electrical characteristic that crosstalk effect is derived may cause output error, and the ghost effect meeting that it produced simultaneously seriously influences the integrality of signal, causes tft liquid crystal to show mistake, influences the quality of liquid crystal display displays frame.
Industry is ground the mode that has many minimizing parasitic capacitance Cpd effects at present.Fig. 1 illustrates the one mode.Be provided with shared electrode wire (common line) 103, dielectric layer 105, data conductor 107, protective layer (passivation layer) 109 and pixel electrode 111 in a substrate 101.Wherein, 111 of shared electrode wire 103 and pixel electrodes form a storage capacitors Cs.There are a parasitic capacitance Cpd in 107 of pixel electrode 111 and data conductor.The protective layer 109 of this structure makes the distance of 111 of shared electrode wire 103 and pixel electrodes increase and has reduced the influence of parasitic capacitance Cpd.
Yet, the structure of Fig. 1 has also increased the distance of 111 of shared electrode wire 103 and pixel electrodes simultaneously, make the storage capacitors Cs of 111 of shared electrode wire 103 and pixel electrodes reduce, and further cause the electrode surface area relevant to strengthen with storage capacitors, to keep the value of total storage capacitors Cst.The surface area of this electrode increases, and the meaning aperture opening ratio reduces.In addition, owing to increase by a protective layer 109, make that technology must be complicated more, and cause production cost to increase.In a specific embodiment, the method will cause black matrix" (black matrix) (the scheming not shown) width of data conductor 107 tops to reach more than 20 microns (μ m).
Moreover also can between pixel electrode and data conductor, the shielding of one consistent electric field be set, to reduce the parasitic capacitance value of data conductor to pixel electrode.General shielding mode often utilizes a metallic shield with coated wire, produces metal electric field shielding effect.Right metallic shield and lead too near the time, the metallic shield meeting is subjected to field coupled (coupling) effect of lead and stored charge.Therefore, need to make it have shielding action simultaneously, and avoid the metallic shield stored charge additionally with metallic shield ground connection or conducting one burning voltage.
The utilizing the metallic shield tool and the structure of high aperture arranged of prior art, as shown in Figure 2.This structure in substrate 201 be provided with one first insulating barrier 203, second insulating barrier 205, data conductor 207, the 3rd insulating barrier 209, pixel electrode 211, with storage electrode (storage electrode) 213.Storage electrode 213 is arranged at 211 of data conductor 207 and pixel electrodes, and tool shares (common) current potential, to be used for the parasitic capacitance Cpd effect of 211 of shadow data lead 207 and pixel electrodes.The method is less for the influence of aperture opening ratio, and in a specific embodiment, the method can make black matrix" (the scheming not shown) width reduction to 10 micron (μ m) of data conductor 207 tops.The general dot structure of the method must additionally increase the electrode that an insulating barrier and a metal level are thought shielding usefulness.Yet this will cause process complications, and unfavorable production time and cost.
The mode that other reduces parasitic capacitance Cpd for example increases the size of storage capacitors, to reduce in the sub-pixel unit (sub-pixel) parasitic capacitance Cpd in total capacitance C
TotalIn the shared ratio that influences.Yet, if adopt the storage capacitors mode that increases, must increase the area of the light tight electrode relevant with storage capacitors, this also will influence aperture opening ratio.Another way also can be utilized through exposure moulding (photo-imaged) and SOG (spin on glass) mode and apply (coating) organic low dielectric constant dielectric film (organicinsulator film, K=2.7～3.5) in appropriate location, with the parasitic capacitance effect between reduction data conductor and pixel electrode, even pixel electrode can be overlapped with data conductor.So, if adopt the organic low dielectric constant dielectric film, because of this material easily has problems such as moisture absorption (water adsorption), yellow (yellowed) and interface tack (interface adhesion) be not good, may influence the technology yield (yield) and the speed of response (throughput).Or a mode again, draw when plain in design, the distance between pixel electrode and the data conductor is remained greater than certain value.Right this distance is big more, though parasitic capacitance Cpd effect is more little, causes pixel aperture ratio to reduce also.
Though aforesaid each method can reduce the problem that aforementioned parasitic capacitor C pd effect produces, but still has many shortcomings, for example influence aperture opening ratio, make process complications, unfavorable production time and cost etc.Parasitic capacitance Cpd effect problem between data conductor and pixel electrode is an industry problem demanding prompt solution for this reason still.In view of this, provide one to make the method for liquid crystal display, and can improve the parasitic capacitance Cpd effect problem ardent expectation person of industry institute for this reason.
Summary of the invention
Technical problem to be solved by this invention is to provide LCD unit structure and manufacture method thereof, and the problem that can avoid prior art parasitic capacitance Cpd effect to produce reaches to solving the shortcomings such as process complications, unfavorable production time and cost that this problem causes.
For achieving the above object, the invention provides a kind of method of manufacturing one LCD unit structure, comprise: form a patterning the first metal layer on a substrate, it comprises one first data conductor section and reaches gate pad; Form a pattern dielectric layer, on this first data conductor section, to define a plurality of first openings and definition one second opening on this time gate pad; Form a patterning second metal level, it comprises one and shares gate pad on electrode wires, the one second data conductor section and, wherein, should go up gate pad and be electric connection, and this second data conductor section is electric connection by those first openings and this first data conductor section by this first opening and this time gate pad; Form a patterning protective layer; And form a patterned transparent conductive layer.
And, for achieving the above object, the invention provides a kind of method of manufacturing one LCD unit structure, comprise: form a patterning the first metal layer on a substrate, it comprises a grid lead, one first data conductor section reaches gate pad; On this substrate, form a dielectric layer, semi-conductor layer and a photoresist layer in regular turn; Use half light modulation mask to carry out little shadow program; Remove this photoresist layer of part, form a plurality of first openings and form one second opening at least to expose this semiconductor layer surface of this time gate pad top to the open air to expose this semiconductor layer surface of this top, first data conductor section two ends to the open air, to reach; Remove this interior semiconductor layer of those first openings and this second opening and/or this dielectric layer under it; Remove partly this photoresist layer, make this remaining photoresist layer be positioned at this grid lead top at least; Remove this semiconductor layer that is not covered by this photoresist layer; Remove remaining this photoresist layer, to form a pattern dielectric layer and a patterned semiconductor layer; Form a patterning second metal level on this pattern dielectric layer and this patterned semiconductor layer, it comprises one and shares gate pad on electrode wires, the one second data conductor section and, wherein, this second data conductor section is electric connection by those first openings and this first data conductor section, and gate pad is electric connection by this second opening and this time gate pad on this; Form a patterning protective layer; And form a patterned transparent conductive layer.
And, for achieving the above object, the invention provides a kind of method of making LCD unit structure, comprise: on a substrate, form one first data conductor section in regular turn and cover a pattern dielectric layer of this first data conductor section, wherein, this pattern dielectric layer has a plurality of first openings and is positioned at this first data conductor section two ends; Form a patterned semiconductor layer in this data conductor top; Form one second data conductor section and and share electrode wires on this patterned semiconductor layer, wherein this second data conductor section is electric connection by those first openings and this first data conductor section; Form a patterning protective layer; And form a patterned transparent conductive layer.
And, for achieving the above object, the invention provides a kind of method of making LCD unit structure, comprise: on a substrate, form one first data conductor section in regular turn and cover a dielectric layer of this data conductor; Form one first semiconductor layer; Form an etching stopping layer on this first semiconductor layer of this first data conductor section top; Form one second semiconductor layer on this first semiconductor layer and this etching stopping layer; This dielectric layer of etching, this first semiconductor layer and this second semiconductor layer, with a plurality of first openings of definition on this dielectric layer, exposing the two ends of this first data conductor section, and this dielectric layer of patterning, this first semiconductor layer and this second semiconductor layer; Form one second data conductor section and and share electrode wires on this patterning second semiconductor layer, wherein this second data conductor section is electric connection by those first openings and this first data conductor section; Form a patterning protective layer; And form a patterned transparent conductive layer.
And, for achieving the above object, the invention provides a kind of LCD unit structure, comprise: one first data conductor section is formed on the substrate; One pattern dielectric layer covers this first data conductor section; One patterned first semiconductor layer is formed on this pattern dielectric layer; One patterning, second semiconductor layer is formed on this patterned first semiconductor layer; And one share electrode wires and one second data conductor section is formed on this patterning second semiconductor layer; Wherein, this pattern dielectric layer has a plurality of first openings in the first data conductor section two ends, electrically connects this second data conductor section for this first data conductor section.
Adopt the present invention, the problem that can avoid parasitic capacitance Cpd effect to produce, technology is simple, cost is low.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the schematic diagram of prior art;
Fig. 2 is the schematic diagram of another prior art;
Fig. 3 A to Fig. 3 N is the process schematic representation of first embodiment of the invention, and wherein Fig. 3 E to Fig. 3 H uses half to transfer (halftone) photomask to carry out little shadow program and etching program technology to form the process schematic representation of Fig. 3 D;
Fig. 4 A to Fig. 4 L is the process schematic representation of second embodiment of the invention; And
Fig. 5 A to Fig. 5 L is the process schematic representation of third embodiment of the invention.
Wherein, Reference numeral:
101,201,301,401,501: substrate 103,3071,4071,5071: shared electrode wire
105,305 ', 405 ', 505 ': dielectric layer 107,207: data conductor
109: protective layer 111,211: pixel electrode
205: the second insulating barriers of 203: the first insulating barriers
Insulating barrier 213 in 209: the three: storage electrode
3011: transistor area 303,403,503: patterning the first metal layer
3033: following gate pad 3031,4031,5031: the first data conductor sections
3035,4035,5035: grid lead 305,405,505: pattern dielectric layer
307: patterning second metal level 3075,4075,5075: source/drain electrode
3073: go up gate pad 3077,4077,5077: the second data conductor sections
309,409,509: patterning protective layer 311,411,511: patterned transparent conductive layer
313,413: patterned semiconductor layer 313 ': semiconductor layer
3131 ', 5131 ': first semiconductor layer, 3133 ', 5133 ': second semiconductor layer
321: the three openings 319,417,517: the first openings
315: photoresist layer 317,421,521: the second openings
3131,4131,5131: patterned first semiconductor layer
3133,4133,5133: patterning second semiconductor layer
515: etching stopping layer
Embodiment
Fig. 3 A to Fig. 3 N is the schematic diagram of first embodiment of the invention.Fig. 3 A is the top view of Fig. 3 B, and Fig. 3 B is the generalized section of corresponding diagram 3A section line AA ', BB ', CC ' and DD '.At first, on a substrate 301, form patterning the first metal layer 303 with reference to figure 3B.Substrate 301 is general normal to be glass substrate, especially the glass of alkali-free metal ion (as sodium, potassium ion) and low-thermal-expansion rate.Substrate 301 is through after the suitable cleaning, use suitable method, the for example deposition or the method for sputter (sputter), metal material is coated on the substrate 301 comprehensively, afterwards, utilize development and etch process that unwanted metal material is removed, make metal material on substrate 301, form patterning the first metal layer 303.Also can use the mode of printing or similar printing in addition, directly on substrate 301, form a patterning the first metal layer 303.Those skilled in the art form patterning the first metal layer 303 as can be known and do not limit aforesaid method, and the needs in the visual use are selected other method for use.
From the above, can be according to technologic demand, select to form the material of patterning the first metal layer 303, it can be the alloy of molybdenum (molybdenum), tantalum (tantalum), chromium (Chromium), tungsten (tungsten), aluminium (aluminum), other conductive metal or aforementioned metal.Patterning the first metal layer 303 also can be contained among a multilayer (multi-layer) structure, one barrier layer (barrier layer) for example is set earlier, on this barrier layer, form patterning the first metal layer 303 again, diffuse into substrate when avoiding the metal ion deposition.
Aforementioned formed patterning the first metal layer 303 comprises one first data conductor section 3031, once a gate pad 3033 and a grid lead 3035.Wherein, this grid lead 3035 is arranged in a transistor area 3011 of LCD unit structure and is electric connection with this time gate pad 3033.
Continue with reference to figure 3C and Fig. 3 D, wherein Fig. 3 C is the top view of Fig. 3 D, forms a pattern dielectric layer 305 and a patterned semiconductor layer 313.Pattern dielectric layer 305 is contained on the first data conductor section 3031 a plurality of first openings 319 of definition exposing the end points of the first data conductor section 3031, and in gate pad 3033 tops down, exposes second opening 317 of gate pad 3033 down with one.Execution mode commonly used is as follows, but the needs in the visual use select other method, step for use or carry out order, and not as limit: utilize the chemical vapor deposition (CVD) method in regular turn dielectric material and semi-conducting material to be arranged on the substrate 301 comprehensively.Utilize little shadow and etching mode again, form a pattern dielectric layer 305 and patterned semiconductor layer 313.The dielectric material of aforementioned pattern dielectric layer 305 can be silicon nitride or other material.
The implementation method that another is commonly used, can utilize the method for chemical vapour deposition (CVD) that one dielectric material is coated on the substrate 301 comprehensively, afterwards, utilize development and etch process that unwanted dielectric material is removed, form pattern dielectric layer 305, wherein comprise aforesaid first opening 319 and second opening 317.Then, utilize the method for chemical vapour deposition (CVD) that semi-conducting material is coated on the substrate 301 comprehensively, and utilize development and etch process that unwanted semi-conducting material is removed, form aforesaid semiconductor layer 313, its result is still shown in Fig. 3 D.
For obtaining the production time of more favourable display panels, another implementation method commonly used is also promptly selected the half light modulation mask (half-tone mask) that can reduce the technology number of times for use again, to carry out little shadow program and etching program, to obtain the structure of Fig. 3 D.Fig. 3 E to Fig. 3 H is to use half light modulation mask to carry out little shadow program and etching program technology to form the structure of Fig. 3 D, is described as follows.At first, on substrate 301, form dielectric layer 305 ', semi-conductor layer 313 ' and photoresist layer 315 in regular turn with reference to figure 3E.Wherein, semiconductor layer 313 ' comprises first semiconductor layer 3131 ' and second semiconductor layer 3133 ' thereon.At the beginning of predetermined formation first opening 319 and second opening 317, also promptly descend gate pad 3033 tops and part first data conductor section top 3031, remove the partly surface of semiconductor layer 313 ' respectively.Then, continuous ginseng Fig. 3 F carries out etching program to remove the semiconductor layer 313 ' through exposing in first opening 319 and second opening 317.In this, whether alternative decision further removes the part dielectric layer 305 ' in first opening 319 and second opening 317.For the purpose of explanation, below will describe with the aspect that removes the part dielectric layer 305 ' in first opening 319 and second opening 317.
Afterwards, shown in Fig. 3 G, carry out photoresist layer 315 and remove technology, remove another photoresist layer 315 partly again.In this step, retain partly photoresist layer 315 to being less than grid lead 3035 tops, and expose the semiconductor layer 313 ' on the first data conductor section 3031 at least.As Fig. 3 H shown in, remove the semiconductor layer 313 ' that not by this photoresist layer 315 covered, to form patterned semiconductor layer 313 thereafter.Simultaneously if in the step of Fig. 3 F, select residual fraction dielectric layer 305 ' in first opening 319 and second opening 317, also in this step, remove simultaneously, with formation pattern dielectric layer 305, and expose the end points (i.e. first opening, 319 places) of the first data conductor section 3031 and expose gate pad 3033 (i.e. second opening, 317 places) down.At last, carry out second time photoresist material and remove technology, remove remaining photoresist layer 315 to form structure as Fig. 3 D.
Continuous with reference to figure 3I and Fig. 3 J, wherein Fig. 3 I is the top view of Fig. 3 J, forms a patterning second metal level 307, this design can be in the viewing area also circuit region around.Second metal level 307 of formed patterning comprises shared electrode lead 3071, goes up gate pad 3073, source/drain electrode 3075 and the second data conductor section 3077.Wherein, source/drain electrode 3075 is arranged on the partially patterned semiconductor layer 313 of grid lead 3035 tops and with this partially patterned semiconductor layer 313 that overlaps and is electric connection.Patterning second metal level 307 is electric connection by this first opening 319 and second opening 317 with patterning the first metal layer 303.In detail, the first data conductor section 3031 is electric connection by first opening 319 and the second data conductor section 3077, so, causes the first data conductor section 3031 and the second data conductor section, the 3077 common necessary data conductor of liquid crystal display of forming; Last gate pad 3073 is electric connection by second opening 317 with following gate pad 3033, so, also causes grid lead 3035 and last gate pad 3073 to be electric connection.
Formation patterning second metal level 307 modes commonly used are as follows, but the needs in the visual use, select other method, step for use or carry out order, and not as limit: the comprehensive plating material of method that utilizes sputter, utilize development and etch process that unwanted metal material is removed again, to form second metal level 307 of patterning.Look the needs in the application, patterning second metal level 307 employed materials can be identical or different with patterning the first metal layer 303.In addition; because patterned semiconductor layer 313 comprises patterned first semiconductor layer 3131 and patterning second semiconductor layer 3133 in the present embodiment; so can utilize dry-etching method or other method in the grid lead top usually, etched patternization second semiconductor layer 3133 is with further exposure patternization first semiconductor layer 3131.
With reference to figure 3K and Fig. 3 L, wherein Fig. 3 K is the top view of Fig. 3 L again, forms a patterning protective layer 309.Generation type following (but not as limit) utilizes the method for chemical vapour deposition (CVD) to form a dielectric materials layer comprehensively.Afterwards, utilize development and etch process that unwanted dielectric material is removed again, to form patterning protective layer 309.Wherein, be contained in gate pad 3033 tops, in second opening 317, the upper surface of gate pad 3073 on the expose portion, and the appropriate location on source/drain electrode 3075 forms one the 3rd opening 321 with expose portion source/drain electrode 3075.Certainly, the needs in the visual use also can be selected other method, step for use or carry out order to form patterning protective layer 309.Patterning protective layer 309 employed materials can be silicon nitride or other material.
At last, with reference to figure 3M and Fig. 3 N, wherein Fig. 3 M is the top view of Fig. 3 N, form a patterned transparent conductive layer 311, wherein patterned transparent conductive layer 311 is electrically connect by the 3rd opening 321 with source/drain electrode 3075, and is electrically connect by second opening 317 with last gate pad 3073.Usually utilize the comprehensive coating electrically conductive material of method of sputter.Afterwards, utilize development and etch process that unwanted electric conducting material is removed again, to form patterned transparent conductive layer 311.Certainly, look the needs of technology, the method that also can select other for use is to form patterned transparent conductive layer 311.Patterned transparent conductive layer 311 employed materials can be tin indium oxide (Indium Tin Oxide) or other material.
Fig. 4 A to Fig. 4 L is the schematic diagram of second embodiment of the invention.Fig. 4 A is the top view of Fig. 4 B, and Fig. 4 B is the generalized section of corresponding diagram 4A section line AA ', BB ' and CC '.Those skilled in the art are when understanding, and the step among first embodiment can be applicable to present embodiment, so the present embodiment partial content omits appropriateness.At first, on a substrate 401, form patterning the first metal layer 403 with reference to figure 4B.Patterning the first metal layer 403 comprises one first a data conductor section 4031 and a grid lead 4035.
Continuous ginseng is with reference to figure 4C and Fig. 4 D, and wherein Fig. 4 C is the top view of Fig. 4 D, forms a dielectric layer 405 '.Afterwards, form a patterned semiconductor layer 413 in the part first data conductor section 4031 and grid lead 4035 tops.Wherein, patterned semiconductor layer 413 comprises patterned first semiconductor layer 4131 and patterning second semiconductor layer 4133.Patterned first semiconductor layer 4131 can be an amorphous silicon layer, and patterning second semiconductor layer 4133 can be a N type ion heavily doped amorphous silicon layer, but not as limit.The step that forms this patterned semiconductor layer 413 is as follows, but not as limit: extensively form one first semiconductor layer earlier on dielectric layer 405 ', form one second semiconductor layer again on this first semiconductor layer, carry out a little shadow and etching program then simultaneously with first semiconductor layer and second semiconductor layer patternization, to form patterned semiconductor layer 413.Perhaps, also can form patterned first semiconductor layer 4131 and patterning second semiconductor layer 4133 respectively, to form patterned semiconductor layer 413.
Afterwards, shown in Fig. 4 E and Fig. 4 F, Fig. 4 E is the top view of Fig. 4 F, removes part dielectric layer 405 ' to form pattern dielectric layer 405, wherein is contained in a plurality of first openings 417 of dielectric layer 405 ' middle formation of this first data conductor section end points top.With reference to figure 4G and Fig. 4 H, wherein Fig. 4 G is the top view of Fig. 4 H, on the first data conductor section 4031 in those first openings 417, on this patterning second semiconductor layers 4133 of partial data lead 4031 tops, with this patterning second semiconductor layers 4133 of grid lead 4035 tops on, form one second data conductor section 4077, respectively and share electrode wires 4071 and one source/drain electrode 4075.Wherein, this second data conductor section 4077 is to be electric connection by those first openings 417 and this first data conductor section 4031, and source/drain electrode 4075 then is electric connection with this patterning second semiconductor layers 4133 of grid lead 4035 tops.
Reference is with reference to figure 4I and Fig. 4 J again, and wherein the top view of Fig. 4 I Fig. 4 J forms a patterning protective layer 409, and the appropriate location on source/drain electrode 4075 forms one second opening 421 with expose portion source/drain electrode 4075.Protective layer 409 employed materials can be silicon nitride or other material.At last, with reference to figure 4K and Fig. 4 L, wherein the top view of Fig. 4 K Fig. 4 L forms a patterned transparent conductive layer 411, and wherein patterned transparent conductive layer 411 is electrically connect by second opening 421 with source/drain electrode 4075.Patterned transparent conductive layer 411 employed materials can be tin indium oxide or other material.
Fig. 5 A to Fig. 5 L is the schematic diagram of another embodiment of the present invention.Fig. 5 A is the top view of Fig. 5 B, and Fig. 5 A is the generalized section of corresponding diagram 5B section line AA ', BB ' and CC '.Those skilled in the art are when understanding, and the step among first embodiment can be applicable to present embodiment, so the present embodiment partial content omits appropriateness.At first, on a substrate 501, form patterning the first metal layer 503 with reference to figure 5B.Patterning the first metal layer 503 comprises one first a data conductor section 5031 and a grid lead 5035.
Continuous ginseng Fig. 5 C and Fig. 5 D, wherein the top view of Fig. 5 C Fig. 5 D forms a dielectric layer 505 '.Afterwards, form one first semiconductor layer 5131 '.Continue and form an etching stopping layer 515 in the part first data conductor section 5031 and grid lead 5035 tops.With reference to figure 5E and Fig. 5 F, wherein the top view of Fig. 5 E Fig. 5 F forms one second semiconductor layer 5133 ' and upward reaches on the etching stopping layer 515 in this first semiconductor layer 5131 ' then.Wherein, patterned first semiconductor layer 5131 can be an amorphous silicon layer, patterning second semiconductor layer 5133 can be a N type ion heavily doped amorphous silicon layer, the material of etching stopping layer can be selected from one of group family that silicon nitride, silica, silicon oxynitride and organic material form and combination thereof, all can as long as can reach the material that etching stops purpose.
Continue with reference to figure 5G and Fig. 5 H, the top view of Fig. 5 G Fig. 5 H wherein, this dielectric layer 505 ' of etching, first semiconductor layer 5131 ' and second semiconductor layer 5133 ' are to form pattern dielectric layer 505, patterned first semiconductor layer 5131 and patterning second semiconductor layer 5133.Simultaneously, a plurality of first openings 517 of definition in this dielectric layer 505 ' are to expose the end points of this first data conductor section 5031.Then, form simultaneously one second data conductor section 5077 in first opening 517, one share electrode wires 5071 in the part first data conductor section, 5031 tops and one source/drain electrode 5075 on patterning second semiconductor layer 5133 of grid lead 5035 tops.Wherein, this second data conductor section 5077 is electric connection by those first openings 517 and this first data conductor section 5031, and source/drain electrode 5075 then is electric connection with partially patterned second semiconductor layer 5133 of grid lead 5035 tops.
With reference to figure 5I and Fig. 5 J, wherein Fig. 5 I is the top view of Fig. 5 J again, forms a patterning protective layer 509, and the appropriate location on source/drain electrode 5075 forms one second opening 521 with expose portion source/drain electrode 5075.Protective layer 509 employed materials can be silicon nitride or other material.At last, with reference to figure 5K and Fig. 5 L, wherein Fig. 5 K is the top view of Fig. 5 L, forms a patterned transparent conductive layer 511, and wherein patterned transparent conductive layer 511 is electrically connect by second opening 521 with source/drain electrode 5075.Patterned transparent conductive layer 511 employed materials can be tin indium oxide or other material.
In sum, the present invention effectively is applied to make the method for liquid crystal display by forming the means of shared electrode in the segment data line top, to reach to solve the effect of parasitic capacitance Cpd effect problem.If collocation half light modulation mask (half-tone mask) carries out little shadow program, then can further make work simplification, save production time and cost etc.; If aforesaid semiconductor layer and/or etching stopping layer further are set between patterned transparent conductive layer and data conductor, the load in the time of then more can further reducing the data conductor transmission signals.The real tool industrial utilization of the present invention.
The various embodiments described above all are not limited to content shown in the drawings, and especially those skilled in the art consider the technology contents in this exposure in light of actual conditions, when thinking and the carrying out order of various different enforcement sample attitude, implementation method, implementation step or enforcement.For example, visual demand in first embodiment patterned first semiconductor layer 3131 and patterning second semiconductor layer 3133 between a dielectric materials layer is set again thinks under etching stopping layer or each metal level in each embodiment a barrier layer be set.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (17)
1. a method of making a LCD unit structure is characterized in that, comprises:
Form a patterning the first metal layer on a substrate, it comprises a grid lead, one first data conductor section reaches gate pad;
On this substrate, form a dielectric layer, semi-conductor layer and a photoresist layer in regular turn;
Use half light modulation mask to carry out little shadow program;
Remove this photoresist layer of part, form a plurality of first openings and form one second opening at least to expose this semiconductor layer surface of this time gate pad top to the open air to expose this semiconductor layer surface of this top, first data conductor section two ends to the open air, to reach;
Remove this interior semiconductor layer of those first openings and this second opening and/or this dielectric layer under it;
Remove partly this photoresist layer, make this remaining photoresist layer be positioned at this grid lead top at least;
Remove this semiconductor layer that is not covered by this photoresist layer;
Remove remaining this photoresist layer, to form a pattern dielectric layer and a patterned semiconductor layer;
Form a patterning second metal level on this pattern dielectric layer and this patterned semiconductor layer, it comprises one and shares gate pad on electrode wires, the one second data conductor section and, wherein, this second data conductor section is electric connection by those first openings and this first data conductor section, and gate pad is electric connection by this second opening and this time gate pad on this;
Form a patterning protective layer; And
Form a patterned transparent conductive layer.
2. method according to claim 1 is characterized in that, this step that forms this patterning protective layer comprises:
Form a protective layer; And
At least this protective layer that removes this second opening top is to expose the upward gate pad in this second opening.
3. method according to claim 1 is characterized in that, this patterning second metal level also comprises the one source/drain electrode that is positioned at this grid lead top.
4. method according to claim 1 is characterized in that, this patterned semiconductor layer comprises an amorphous silicon layer and a N type ion heavily doped amorphous silicon layer.
5. method according to claim 1 is characterized in that this protective layer comprises a silicon nitride layer.
6. method according to claim 1 is characterized in that this transparency conducting layer comprises an indium tin oxide layer.
7. a method of making LCD unit structure is characterized in that, comprises:
Form one first data conductor section in regular turn and cover a pattern dielectric layer of this first data conductor section on a substrate, this pattern dielectric layer has a plurality of first openings and is positioned at this first data conductor section two ends;
Form a patterned semiconductor layer in this data conductor top;
Form one second data conductor section and and share electrode wires on this patterned semiconductor layer, this second data conductor section is electric connection by those first openings and this first data conductor section;
Form a patterning protective layer; And
Form a patterned transparent conductive layer.
8. according to the method for claim 7, it is characterized in that, this patterned semiconductor layer comprise a patterned first semiconductor layer and on patterning second semiconductor layer.
9. method according to Claim 8 is characterized in that, the step that forms this patterned semiconductor layer comprises:
Form one first semiconductor layer;
Form one second semiconductor layer on this first semiconductor layer; And
Carry out a little shadow and etching program with simultaneously with this first semiconductor layer and this second semiconductor layer patternization.
10. method according to Claim 8 is characterized in that, the step that forms this patterned semiconductor layer comprises:
Form a patterned first semiconductor layer; And
Form a patterning second semiconductor layer on this patterned first semiconductor layer.
11. a method of making LCD unit structure is characterized in that, comprises:
On a substrate, form one first data conductor section in regular turn and cover a dielectric layer of this data conductor;
Form one first semiconductor layer;
Form an etching stopping layer on this first semiconductor layer of this first data conductor section top;
Form one second semiconductor layer on this first semiconductor layer and this etching stopping layer;
This dielectric layer of etching, this first semiconductor layer and this second semiconductor layer, with a plurality of first openings of definition on this dielectric layer, exposing the two ends of this first data conductor section, and this dielectric layer of patterning, this first semiconductor layer and this second semiconductor layer;
Form one second data conductor section and and share electrode wires on this patterning second semiconductor layer, this second data conductor section is electric connection by those first openings and this first data conductor section;
Form a patterning protective layer; And
Form a patterned transparent conductive layer.
12. a method of making a LCD unit structure is characterized in that, comprises:
Form a patterning the first metal layer on a substrate, it comprises one first data conductor section and a grid lead reaches gate pad down;
Form a pattern dielectric layer, on this first data conductor section, to define a plurality of first openings and definition one second opening on this time gate pad;
Form a patterning second metal level, it comprises one and shares gate pad on electrode wires, the one second data conductor section and, should go up gate pad and be electric connection, and this second data conductor section is electric connection by those first openings and this first data conductor section by this first opening and this time gate pad;
Form a patterning protective layer; And
Form a patterned transparent conductive layer.
13. a LCD unit structure is characterized in that, comprises:
One first data conductor section is arranged on the substrate;
One pattern dielectric layer covers this first data conductor section;
One patterned first semiconductor layer is arranged on this pattern dielectric layer;
One patterning, second semiconductor layer is arranged on this patterned first semiconductor layer; And
One shared electrode wires and one second data conductor section are arranged on this patterning second semiconductor layer;
This pattern dielectric layer has a plurality of first openings in the first data conductor section two ends, electrically connects this second data conductor section for this first data conductor section.
14. structure according to claim 13 is characterized in that, also comprises an etching stopping layer between this patterned first semiconductor layer and this patterning second semiconductor layer.
15. structure according to claim 13 is characterized in that, this patterned first semiconductor layer is an amorphous silicon layer.
16. structure according to claim 13 is characterized in that, this patterning second semiconductor layer is a N type ion heavily doped amorphous silicon layer.
17. structure according to claim 13 is characterized in that, this etching stopping layer material is selected from one of group family that silicon nitride, silica, silicon oxynitride and organic material form and combination thereof.
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| CNA2008100010597A CN101221926A (en) | 2008-01-18 | 2008-01-18 | LCD unit structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008100010597A CN101221926A (en) | 2008-01-18 | 2008-01-18 | LCD unit structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101950733A (en) * | 2010-08-02 | 2011-01-19 | 友达光电股份有限公司 | Manufacturing method of pixel structure and manufacturing method of organic light-emitting component |
| CN105549286A (en) * | 2016-03-02 | 2016-05-04 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN105759475A (en) * | 2016-03-23 | 2016-07-13 | 友达光电股份有限公司 | panel structure with light sensing circuit |
| CN110544669A (en) * | 2018-05-29 | 2019-12-06 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor device structure |
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| CN101950733A (en) * | 2010-08-02 | 2011-01-19 | 友达光电股份有限公司 | Manufacturing method of pixel structure and manufacturing method of organic light-emitting component |
| CN101950733B (en) * | 2010-08-02 | 2012-06-27 | 友达光电股份有限公司 | Manufacturing method of pixel structure and manufacturing method of organic light-emitting component |
| CN105549286A (en) * | 2016-03-02 | 2016-05-04 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN105549286B (en) * | 2016-03-02 | 2019-05-24 | 京东方科技集团股份有限公司 | The manufacturing method of display panel, display device and display panel |
| US10606132B2 (en) | 2016-03-02 | 2020-03-31 | Boe Technology Group Co., Ltd. | Display panel, display device, and method for manufacturing display panel |
| CN105759475A (en) * | 2016-03-23 | 2016-07-13 | 友达光电股份有限公司 | panel structure with light sensing circuit |
| CN111108541A (en) * | 2017-09-27 | 2020-05-05 | 夏普株式会社 | Flexible display device and method for manufacturing flexible display device |
| CN111108541B (en) * | 2017-09-27 | 2021-10-15 | 夏普株式会社 | Flexible display device and method for manufacturing flexible display device |
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