KR20210077279A - Display Device And Method Of Fabricating The Same - Google Patents

Abstract

The present invention provides a substrate comprising: a substrate including at least one sub-pixel having a circuit region and a light emitting region; a first anti-reflective layer and a light-blocking layer sequentially disposed in the circuit region on the substrate; a buffer layer disposed on the light blocking layer; a semiconductor layer disposed on the buffer layer corresponding to the light blocking layer; a gate insulating layer and a second non-reflective layer sequentially disposed on the semiconductor layer; a gate electrode disposed on the second non-reflective layer corresponding to the central portion of the semiconductor layer; a source electrode disposed on the second anti-reflective layer corresponding to one end of the semiconductor layer and in contact with the light blocking layer through a first contact hole of the second anti-reflective layer, the gate insulating layer, and the buffer layer; a drain electrode disposed on the second non-reflective layer corresponding to the other end of the semiconductor layer; a planarization layer disposed on the gate electrode, the source electrode, and the drain electrode; Provided is a display device including a light emitting diode disposed on the planarization layer and connected to the source electrode.

Description

Display Device And Method Of Fabricating The Same

The present invention relates to a display device, and more particularly, to a display device in which reflection of external light is minimized without deterioration of contact characteristics, and a method for manufacturing the same.

Recently, a liquid crystal display device (LCD), a plasma display panel device (PDP), an organic light emitting diode display having excellent characteristics such as reduction in thickness, weight reduction, and low power consumption. Flat panel displays such as device: OLED) and field emission display device (FED) have been widely developed and applied to various fields.

In such a flat panel display device, incident external light is reflected by a metal wire or the like and transmitted to the user, thereby preventing the user from recognizing the image, thereby deteriorating the display quality of the image.

In order to solve this problem, a method for minimizing external light reflection by forming an anti-reflection layer on a surface on which external light such as metal wiring is incident has been proposed.

However, since the anti-reflective layer has a relatively high specific resistance, there is a problem in that contact characteristics such as metal wiring are deteriorated, and thus electrical characteristics of the display device are deteriorated.

The present invention has been proposed to solve this problem, and by selectively forming an anti-reflective layer on the gate insulating layer except for the contact hole, the external light reflection is minimized and the deterioration of the contact characteristic is prevented at the same time, a display device and a method for manufacturing the same aims to provide

In the present invention, by forming a contact hole and an anti-reflective layer using a transflective mask after forming the gate insulating material layer and the non-reflective material layer, external light reflection is minimized without deterioration of contact characteristics, and the manufacturing process is simplified, thereby manufacturing cost Another object of the present invention is to provide a reduced display device and a method for manufacturing the same.

In order to solve the above problems, the present invention provides a substrate including at least one sub-pixel having a circuit region and a light emitting region; a first anti-reflective layer and a light-blocking layer sequentially disposed in the circuit region on the substrate; a buffer layer disposed on the light blocking layer; a semiconductor layer disposed on the buffer layer corresponding to the light blocking layer; a gate insulating layer and a second non-reflective layer sequentially disposed on the semiconductor layer; a gate electrode disposed on the second non-reflective layer corresponding to the central portion of the semiconductor layer; a source electrode disposed on the second anti-reflective layer corresponding to one end of the semiconductor layer and in contact with the light blocking layer through a first contact hole of the second anti-reflective layer, the gate insulating layer, and the buffer layer; a drain electrode disposed on the second non-reflective layer corresponding to the other end of the semiconductor layer; a planarization layer disposed on the gate electrode, the source electrode, and the drain electrode; Provided is a display device including a light emitting diode disposed on the planarization layer and connected to the source electrode.

The source electrode is in contact with one end of the semiconductor layer through a source contact hole of the second non-reflective layer and the gate insulating layer, and the drain electrode is a drain contact hole of the second non-reflective layer and the gate insulating layer. It can be in contact with the other end of the semiconductor layer through the.

The light emitting diode may include: a first electrode disposed on the at least one sub-pixel on the planarization layer; a bank layer disposed on the first electrode and exposing the first electrode of the light emitting region; a light emitting layer disposed on the first electrode in the light emitting region; A second electrode disposed on the light emitting layer may be included.

The display device may include: the first anti-reflective layer and a first capacitor electrode sequentially disposed in the circuit region between the substrate and the buffer layer; a second capacitor electrode disposed on the buffer layer corresponding to the first capacitor electrode; and a passivation layer disposed between the gate electrode, the source electrode, the drain electrode, and the second capacitor electrode and the planarization layer, wherein the first electrode passes through an opening exposing the passivation layer to expose the second capacitor It may be in contact with the protective layer corresponding to the electrode.

Also, the first electrode may contact the source electrode through a second contact hole of the planarization layer and the passivation layer.

The display device may further include a color filter layer disposed in the light emitting region between the buffer layer and the planarization layer.

In addition, each of the first and second anti-reflective layers includes molybdenum oxide tantalum (MoOx:Ta), the light blocking layer includes copper (Cu), and the gate electrode, the source electrode, and the drain electrode each include molybdenum. It may include a first layer of titanium (MoTi) and a second layer of copper (Cu).

Meanwhile, the present invention provides the steps of sequentially forming a first anti-reflective layer and a light blocking layer in a circuit region of at least one sub-pixel on an upper portion of a substrate; forming a buffer layer on the light blocking layer; forming a semiconductor layer on the buffer layer corresponding to the light blocking layer; sequentially forming a gate insulating layer and a second anti-reflective layer on the semiconductor layer; A gate electrode is formed on the second anti-reflective layer corresponding to the central portion of the semiconductor layer, and the second anti-reflective layer, the gate insulating layer, and the buffer layer are formed on the second anti-reflective layer corresponding to one end of the semiconductor layer. forming a source electrode in contact with the light-shielding layer through a first contact hole of the semiconductor layer, and forming a drain electrode on the second non-reflective layer corresponding to the other end of the semiconductor layer; forming a planarization layer on the gate electrode, the source electrode, and the drain electrode; and forming a light emitting diode connected to the source electrode on the planarization layer.

The forming of the gate insulating layer and the second non-reflective layer may include: forming the gate insulating layer and the second non-reflective layer on the semiconductor layer; A first contact hole for exposing the light blocking layer is formed in the second anti-reflective layer, the gate insulating layer, and the buffer layer, and a source contact is formed to expose both ends of the semiconductor layer to the second anti-reflective layer and the gate insulating layer. The method may include forming a hole and a drain contact hole.

In addition, the forming of the first contact hole, the source contact hole, and the drain contact hole includes using an exposure mask having a transmissive part, a semi-transmissive part, and a blocking part, and a first photo film having a first thickness on the second non-reflective layer. forming a resist pattern and a second photoresist pattern having a second thickness smaller than the first thickness; forming the first contact hole by etching the second anti-reflective layer, the gate insulating layer, and the buffer layer using the first and second photoresist patterns as etch masks; removing the second photoresist pattern; and forming the source contact hole and the drain contact hole by etching the second anti-reflective layer and the gate insulating layer using the first photoresist pattern as an etching mask.

The source electrode and the drain electrode may contact both ends of the semiconductor layer through the source contact hole and the drain contact hole, respectively.

The forming of the light emitting diode may include: forming a first electrode in the at least one sub-pixel on the planarization layer; forming a bank layer exposing the first electrode of the light emitting region of the at least one subpixel on the first electrode; forming a light emitting layer on the first electrode in the light emitting region; The method may include forming a second electrode on the light emitting layer.

The method of manufacturing the display device may include: sequentially forming the first anti-reflective layer and a first capacitor electrode in the circuit region between the substrate and the buffer layer; forming a second capacitor electrode on the buffer layer corresponding to the first capacitor electrode; The method may further include forming a protective layer between the gate electrode, the source electrode, the drain electrode, and the second capacitor electrode and the planarization layer, wherein the first electrode passes through an opening exposing the protective layer. The second capacitor may be in contact with the protective layer corresponding to the electrode.

The forming of the passivation layer and the planarization layer may include forming a second contact hole exposing the source electrode in the passivation layer and the planarization layer, wherein the first electrode is the second contact It may be in contact with the source electrode through the hole.

The method of manufacturing the display device may further include forming a color filter layer in a light emitting area of the at least one sub-pixel between the buffer layer and the planarization layer.

According to the present invention, by selectively forming an anti-reflective layer on the gate insulating layer except for the contact hole, reflection of external light is minimized and deterioration of the contact characteristic is prevented.

In the present invention, by forming a contact hole and an anti-reflective layer using a transflective mask after forming the gate insulating material layer and the non-reflective material layer, external light reflection is minimized without deterioration of contact characteristics, and the manufacturing process is simplified, thereby manufacturing cost This has a saving effect.

1 is a plan view illustrating a plurality of sub-pixels of a display device according to an embodiment of the present invention;
2 is a cross-sectional view illustrating one sub-pixel of a display device according to an embodiment of the present invention;
3 is a view illustrating a first non-reflective layer and a light blocking layer 124 of a display device according to an embodiment of the present invention.
4A to 4D are plan views illustrating a method of manufacturing a display device according to an embodiment of the present invention;
5A to 5J are cross-sectional views for explaining a method of manufacturing a display device according to an embodiment of the present invention;
6A and 6B are views illustrating contact characteristics between a source electrode and a semiconductor layer according to an embodiment of the present invention and Comparative Example 1, respectively;
7A and 7B are diagrams illustrating a source-drain current according to a source-drain voltage of a driving thin film transistor according to an embodiment of the present invention and Comparative Example 1, respectively;
8A to 8C are diagrams illustrating a source-drain current according to a gate-source voltage after completion of the gate electrode of a driving thin film transistor according to an embodiment of the present invention, Comparative Example 1, and Comparative Example 2, respectively;
9A to 9C are diagrams illustrating a source-drain current according to a gate-source voltage after completion of a display device of a driving thin film transistor according to an embodiment of the present invention, Comparative Example 1, and Comparative Example 2, respectively;

Hereinafter, a display device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a plurality of sub-pixels of a display device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating one sub-pixel of a display device according to an embodiment of the present invention. emission) type organic light emitting diode display device will be described as an example.

1 and 2 , the display device 110 according to the embodiment of the present invention includes a substrate 120, a switching thin film transistor Tsw, a driving thin film transistor Tdr, and a sensing thin film transistor Tse. , a storage capacitor Cst, and a light emitting diode Del.

Specifically, the substrate 120 includes a display area DA and a pad area PA disposed around the display area DA, wherein the display area DA includes first, second, third, and fourth display areas DA. It includes sub-pixels SP1, SP2, SP3, and SP4, and the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 have an emission area EA and a circuit area CA, respectively. includes

For example, the first, second, third, and fourth subpixels SP1 , SP2 , SP3 , and SP4 may emit light corresponding to blue, green, red, and white, respectively.

The sub-pixel SP of FIG. 2 may be any one of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 of FIG. 1 .

A first anti-reflective layer 122 is formed on the left and right boundaries between the circuit area CA of each sub-pixel SP of the display area DA on the substrate 120 and the left and right boundaries between the pad area PA and the sub-pixel SP, respectively. are placed

For example, the first anti-reflective layer 122 may include molybdenum oxide tantalum (MoOx:Ta) and have a specific resistance of about 40 mΩcm.

A light blocking layer 124 and a first capacitor electrode 126 are respectively disposed on the first anti-reflective layer 122 of the circuit area CA of each sub-pixel SP of the display area DA, and the pad area PA ), a pad 128 is disposed on the first anti-reflective layer 122, and a data line DL and a power line (DL) and a power line (DL) are disposed on the first anti-reflection layer 122 at the boundary between the sub-pixels (SP) in the vertical direction ( PL) and the reference wiring RL are disposed.

For example, the light blocking layer 124 , the first capacitor electrode 126 , the pad 128 , the data line DL, the power line PL, and the reference line RL may include copper (Cu). .

The pad 128 may be a gate pad connected to the gate line GL or a data pad connected to the data line DL.

A buffer layer 130 is disposed on the entire surface of the substrate 120 on the light blocking layer 124 , the first capacitor electrode 126 , the pad 128 , the data line DL, the power line PL, and the reference line RL. do.

For example, the buffer layer 130 may include a first layer of silicon nitride (SiNx) on a lower portion and a second layer of silicon oxide (SiOx) on an upper portion.

A semiconductor layer 132 and a second capacitor electrode 134 are respectively disposed on the light blocking layer 124 and the buffer layer 130 corresponding to the first capacitor electrode 126 , for example, the semiconductor layer 132 and The second capacitor electrode 134 may include an oxide semiconductor material such as indium-gallium-zinc oxide (IGZO).

A gate insulating layer 136 and a second anti-reflective layer 138 are respectively disposed on the central portion and both ends of the semiconductor layer 132 , and on the buffer layer 130 at the upper and lower boundary between the sub-pixels SP.

The second anti-reflective layer 138 and the gate insulating layer 136 have a source contact hole and a drain contact hole exposing both ends of the semiconductor layer 132 , and the second anti-reflective layer 138 and the gate insulating layer 136 . and the buffer layer 130 has a first contact hole C1 exposing the light blocking layer 124 .

For example, the gate insulating layer 136 includes an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), and the second anti-reflective layer 138 is formed of molybdenum oxide tantalum (MoOx:Ta). and may have a resistivity of about 40 mΩcm.

Both ends of the semiconductor layer 132 exposed through the source contact hole and the drain contact hole of the gate insulating layer 136 become conductors and operate as a source region and a drain region, and the semiconductor covered with the gate insulating layer 136 . The central portion of the layer 132 may act as a channel region, and the second capacitor electrode 134 may be conductive.

The gate electrode 140 is disposed on the second non-reflective layer 138 corresponding to the central portion of the semiconductor layer 132 , and the source is disposed on the second non-reflective layer 138 corresponding to both ends of the semiconductor layer 132 , respectively. The electrode 146 and the drain electrode 152 are disposed, and the gate wiring GL and the sensing wiring SL are disposed in the horizontal direction on the second non-reflective layer 138 at the upper and lower boundary between the subpixels SP. do.

The source electrode 146 and the drain electrode 152 contact both ends of the semiconductor layer 132 through the source contact hole and the drain contact hole, respectively, and the source electrode 146 blocks light through the first contact hole C1. contact layer 124 .

The gate electrode 140 includes a lower first gate layer 132 and an upper second gate layer 144 , and the source electrode 146 has a lower first source layer 148 and an upper second source. layer 150 , and the drain electrode 152 may include a lower first drain layer 154 and an upper second drain layer 156 .

For example, each of the first gate layer 132 , the first source layer 148 , and the first drain layer 154 includes molybdenum titanium (MoTi), and the second gate layer 144 and the second source layer Each of 150 and the second drain layer 156 may include copper (Cu).

The gate electrode 140 , the source electrode 146 , the drain electrode 152 , and the semiconductor layer 132 constitute the driving thin film transistor Tdr.

Although not shown, the switching thin film transistor Tsw and the sensing thin film transistor Tse may have the same structure as the driving thin film transistor Tdr.

The gate electrode of the switching thin film transistor Tsw is connected to the gate wiring GL, the source electrode of the switching thin film transistor Tsw is connected to the data line DL, and the drain electrode of the switching thin film transistor Tsw is the driving thin film. It is connected to the gate electrode 140 of the transistor Tdr.

The source electrode 146 of the driving thin film transistor Tdr is connected to the first electrode 164 of the light emitting diode Del, and the drain electrode 152 of the driving thin film transistor Tdr is connected to the power wiring PL. .

The gate electrode of the sensing thin film transistor Tse is connected to the sensing line SL, the source electrode of the sensing thin film transistor Tse is connected to the first electrode 164 of the light emitting diode Del, and the sensing thin film transistor Tse ) is connected to the reference line RL.

A protective layer 158 is disposed on the entire surface of the substrate 120 over the switching thin film transistor Tsw, the driving thin film transistor Tdr, the sensing thin film transistor Tse and the second capacitor electrode 134, the protective layer 158 and the buffer layer 130 has an opening exposing the pad 128 of the pad area PA.

For example, the protective layer 158 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

The color filter layer 160 is disposed on the passivation layer 158 of the emission area EA of each subpixel SP of the display area DA.

For example, blue, green, and red color filter layers are respectively disposed on the passivation layer 158 of the light emitting area EA of the first, second, and third subpixels SP, and the fourth subpixel SP The color filter layer may be omitted on the passivation layer 158 of the light emitting area EA.

A planarization layer 162 is disposed on the entire surface of the substrate over the color filter layer 160 and the passivation layer 158 .

For example, the planarization layer 162 may include an organic insulating material such as photoacryl.

The planarization layer 162 has an opening exposing the passivation layer 158 corresponding to the second capacitor electrode 134 , and the planarization layer 162 and the passivation layer 158 expose the second capacitor electrode 146 . It has a contact hole C2.

A first electrode 164 is disposed on the planarization layer 162 , and the first electrode 164 contacts the source electrode 146 through the second contact hole C2 .

The first capacitor electrode 126 , the buffer layer 130 , and the second capacitor electrode 134 constitute a first capacitor, and the second capacitor electrode 134 , the protective layer 158 and the first electrode 164 form the first capacitor. 2 Capacitors are configured.

Although not shown, since the second capacitor electrode 134 is connected to the gate electrode 140 , and the first capacitor electrode 126 and the first electrode 164 are connected to the source electrode 146 , the first and The second capacitor constitutes the storage capacitor Cst.

A bank layer 166 is disposed on the first electrode 164 , wherein the bank layer 166 is a first electrode 164 corresponding to the emission area EA of each sub-pixel SP of the display area DA. It has an opening that exposes the

The light emitting layer 168 is disposed on the first electrode 164 exposed through the opening of the bank layer 166 , and the second electrode 170 is disposed on the entire surface of the substrate 120 on the light emitting layer 168 .

The first electrode 164 , the light emitting layer 168 , and the second electrode 170 constitute a light emitting diode Del.

For example, the first electrode 164 is an anode providing a hole in the emission layer 168 and may include indium zinc oxide (ITO) having a relatively large work function. The second electrode 170 is a cathode that provides electrons to the emission layer 168 and may include aluminum (Al) or magnesium silver (MgAg) having a relatively small work function.

The light emitting layer 168 includes a hole injecting layer, a hole transporting layer, an emitting material layer, an electron transporting layer, and an electron injecting layer. may include

Although not shown, an encapsulation layer is disposed on the entire surface of the substrate 120 on the second electrode 170 to prevent penetration of external moisture or oxygen.

In the display device 110 , the light emitted from the light emitting layer 168 passes through the substrate 120 and is transmitted to the user to display an image, and external light incident on the display device 110 is divided into first and second ratios. It can be minimized by being canceled out by the reflective layers 122 and 138 .

FIG. 3 is a view illustrating a first anti-reflective layer and a light blocking layer 124 of a display device according to an embodiment of the present invention, which will be described with reference to FIGS. 1 and 2 together.

As shown in FIG. 3 , the first light L1 , which is external light incident on the display device 110 , is reflected at the interface between the substrate 120 and the first non-reflecting layer 122 to be the second light L2 . It is emitted and reflected at the interface between the first anti-reflective layer 122 and the light blocking layer 124 and emitted as the third light L3, so that the phases of the second and third lights L2 and L3 have a 180 degree difference. When the thickness and refractive index of the first anti-reflective layer 122 are adjusted, the second and third lights L2 and L3 are canceled to minimize reflection of external light.

This principle applies between the first anti-reflective layer 122 and the first capacitor electrode 126 , between the first anti-reflective layer 122 and the pad 128 , the second anti-reflective layer 138 and the gate electrode 140 , and the second The same may be applied between the anti-reflective layer 138 and the source electrode 146 , and the second anti-reflective layer 138 and the drain electrode 152 .

In this case, the second non-reflective layer 138 having a relatively large resistivity includes the upper portion of the light blocking layer 124 exposed through the first contact hole C1 and the semiconductor layer 132 exposed through the source contact hole and the drain contact hole. ) is not formed on both ends, but is selectively formed only on the gate insulating layer 136 .

Accordingly, the first source layer 148 of the source electrode 146 directly contacts the light-shielding layer 124 through the first contact hole C1 and at one end of the semiconductor layer 132 through the source contact hole. The first drain layer 154 of the drain electrode 152 is in direct contact with the other end of the semiconductor layer 132 through the drain contact hole, and as a result, the contact characteristic is prevented from being deteriorated.

A method of manufacturing such a display device will be described with reference to the drawings.

4A to 4D are plan views illustrating a method of manufacturing a display device according to an embodiment of the present invention, and FIGS. 5A to 5J are cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the present invention; It will be described with reference to FIGS. 1 and 2 together.

As shown in FIGS. 4A and 5A , the circuit of each sub-pixel SP of the display area DA on the upper portion of the substrate 120 through a deposition process of an anti-reflective material and a metal material and a photolithographic process A first anti-reflective layer 122 and a light blocking layer 124, a first anti-reflective layer 122, and a first capacitor electrode 126 are formed in the area CA, and are formed in the pad area PA on the substrate 120. The first anti-reflective layer 122 and the pad 128 are formed, and the first anti-reflective layer 122, the data line DL, and the first anti-reflective layer are formed at the boundary between the sub-pixels SP on the substrate 120. 122), the power wiring PL, the first anti-reflective layer 122, and the reference wiring RL are formed.

The first anti-reflective layer 122 includes molybdenum oxide tantalum (MoOx:Ta), and a light blocking layer 124 , a first capacitor electrode 126 , a pad 128 , a data line DL, and a power line PL. , the reference line RL may include copper (Cu).

As shown in FIGS. 4B and 5B , the light blocking layer 124 , the first capacitor electrode 126 , the pad 128 , the data line DL, the power line PL, and the reference line RL are disposed on the upper substrate. (120) A buffer layer 130 is formed on the entire surface.

The buffer layer 130 may include a first layer of silicon nitride (SiNx) on a lower portion and a second layer of silicon oxide (SiOx) on an upper portion.

Thereafter, the semiconductor layer 132 and the second capacitor electrode 134 are respectively disposed on the light blocking layer 124 and the buffer layer 130 corresponding to the first capacitor electrode 126 through the deposition process of the semiconductor material and the exposure etching process. to form

The semiconductor layer 132 and the second capacitor electrode 134 may include an oxide semiconductor material such as indium-gallium-zinc oxide (IGZO).

As shown in FIG. 5C , the gate insulating layer 136 and the second ratio are deposited on the entire surface of the substrate 120 on the semiconductor layer 132 and the second capacitor electrode 134 through a deposition process of an insulating material and a non-reflective material. A reflective layer 138 is formed.

The gate insulating layer 136 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), and the second anti-reflective layer 138 may include molybdenum oxide tantalum (MoOx:Ta).

After the deposition process of the insulating material, before the deposition process of the non-reflective material, a heat treatment process for the gate insulating layer 136 may be performed.

As shown in FIG. 5D , a photoresist layer is formed on the second anti-reflective layer 158, and an exposure mask having a transmissive portion (TA), a semi-transmissive portion (HTA), and a blocking portion (BA) on the photoresist layer ( PM), the photoresist layer is exposed through the exposure mask PM, and then developed to form a first photoresist pattern PP1 having a first thickness and a second photoresist pattern having a second thickness smaller than the first thickness. PP2).

The blocking portion BA and the transflective portion HTA of the exposure mask PM correspond to the first and second photoresist patterns PP1 and PP2, respectively, and a portion corresponding to the transmission portion TA of the exposure mask PM. The photoresist layer is completely removed.

Here, the transmission part TA of the exposure mask PM corresponds to the first contact hole C1, and the blocking part BA of the exposure mask PM connects the gate electrode 140 and the first contact hole C1. It may correspond to the source electrode 146 and the drain electrode 152 except for.

The transmittance of the semi-transmissive portion HTA is greater than the transmittance of the blocking portion BA and less than the transmittance of the transmitting portion TA.

As shown in FIG. 5E , the second anti-reflective layer 138 , the gate insulating layer 136 , and the buffer layer 130 are etched to block light using the first and second photoresist patterns PP1 and PP2 as etch masks. A first contact hole C1 exposing the layer 124 is formed.

As shown in FIG. 5F , the second photoresist pattern PP2 is removed through an ashing process for the first and second photoresist patterns PP1 and PP2, and only the first photoresist pattern PP1 is removed. make it remain

In this case, the first thickness of the first photoresist pattern PP1 may be reduced by the second thickness of the second photoresist pattern PP2 .

As shown in FIGS. 4C and 5G , the second anti-reflective layer 138 and the gate insulating layer 136 are etched using the first photoresist pattern PP1 as an etch mask to form a central portion of the semiconductor layer 132 and The gate insulating layer 136 and the second anti-reflective layer 138 are selectively formed on the upper portions of both ends and the upper and lower boundary portions between the sub-pixels SP and the buffer layer 130 .

Accordingly, the gate insulating layer 136 and the second anti-reflective layer 138 have a source contact hole and a drain contact hole exposing both ends of the semiconductor layer 132 , and the gate insulating layer 136 and the second anti-reflective layer 138 . 138 and the buffer layer 130 have a first contact hole C1 exposing the light blocking layer 124 .

The second non-reflective layer 138 and the gate insulating layer 136 are etched to expose both ends of the semiconductor layer 132 and the second capacitor electrode 134 , and then a plasma treatment process is performed to expose the exposed semiconductor layer 132 . ) and the second capacitor electrode 134 may be conductive.

As shown in FIGS. 4D and 5H , the gate electrode 140 is disposed on the second non-reflective layer 138 corresponding to the central portion of the semiconductor layer 132 through the deposition process and the exposure etching process of the first and second metal materials. ), a source electrode 146 and a drain electrode 152 are formed on the second anti-reflective layer 138 corresponding to both ends of the semiconductor layer 132 , respectively, and the upper and lower boundaries between the sub-pixels SP A gate wiring GL and a sensing wiring SL are formed on the second non-reflective layer 138 in the horizontal direction.

The source electrode 146 and the drain electrode 152 contact both ends of the semiconductor layer 132 through the source contact hole and the drain contact hole, respectively, and the source electrode 146 blocks light through the first contact hole C1. contact layer 124 .

The gate electrode 140 includes a lower first gate layer 132 and an upper second gate layer 144 , and the source electrode 146 has a lower first source layer 148 and an upper second source. layer 150 , and the drain electrode 152 may include a lower first drain layer 154 and an upper second drain layer 156 .

For example, each of the first gate layer 132 , the first source layer 148 , and the first drain layer 154 includes molybdenum titanium (MoTi), and the second gate layer 144 and the second source layer Each of 150 and the second drain layer 156 may include copper (Cu).

As shown in FIG. 5I, the switching thin film transistor (Tsw), the driving thin film transistor (Tdr), the sensing thin film transistor (Tse) and the second capacitor electrode 134 through the deposition process of the insulating material, the front surface of the substrate 120 A protective layer 158 is formed thereon.

Thereafter, the color filter layer 160 is formed on the protective layer 158 of the light emitting area EA of each subpixel SP of the display area DA through a coating process of the color filter material and an exposure development process.

Thereafter, a planarization layer 162 is formed on the entire surface of the substrate over the color filter layer 160 and the protective layer 158 through an insulating material deposition process and an exposure etching process.

The planarization layer 162 may include an organic insulating material such as photoacryl.

The planarization layer 162 has an opening exposing the passivation layer 158 corresponding to the second capacitor electrode 134 , and the planarization layer 162 and the passivation layer 158 expose the second capacitor electrode 146 . It has a contact hole C2.

Thereafter, a first electrode 164 is formed on the planarization layer 162 through a deposition process of a transparent conductive material and an exposure etching process, and the first electrode 164 is a source electrode ( 146).

The first electrode 164 may include indium zinc oxide (ITO).

As shown in FIG. 5J , a bank layer 166 is formed on the first electrode 164 through a deposition process of an organic material and an exposure development process. The bank layer 166 is each part of the display area DA. It has an opening exposing the first electrode 164 corresponding to the emission area EA of the pixel SP.

Thereafter, an emission layer 168 is formed on the first electrode 164 exposed through the opening of the bank layer 166 through a deposition process of an organic material using a shadow mask.

Thereafter, the second electrode 170 is formed on the entire surface of the substrate 120 on the light emitting layer 168 through a metal material deposition process.

The second electrode 170 may include aluminum (Al) or magnesium silver (MgAg).

As described above, in the display device 110 according to the embodiment of the present invention, reflection of the first and second non-reflective layers 122 and 138 is removed by destructive interference, thereby minimizing reflection of external light.

In addition, instead of sequentially forming the second anti-reflective layer 138 , the first source layer 148 , and the second source layer 150 inside the first contact hole C1 , the gate insulating layer 132 is formed on the upper portion. By forming the first contact hole C1 after forming the second anti-reflective layer 138 , the first source layer 148 and the second source layer 150 are sequentially formed in the first contact hole C1 . Accordingly, the first source layer 148 may be in direct contact with the light blocking layer 124 , and as a result, the contact characteristics may be prevented from being deteriorated.

6A and 6B are diagrams showing the contact characteristics between the source electrode and the semiconductor layer according to Example and Comparative Example 1 of the present invention, respectively, and FIGS. 7A and 7B are each in Example and Comparative Example 1 of the present invention. is a view showing the source-drain current according to the source-drain voltage of the driving thin film transistor according to the present invention, and FIGS. 8A to 8C are the gate after completion of the gate electrode of the driving thin film transistor according to the embodiment of the present invention, Comparative Example 1 and Comparative Example 2, respectively. It is a view showing the source-drain current according to the source voltage, and FIGS. 9A to 9C are the source-drain according to the gate-source voltage after the display device of the driving thin film transistor according to the embodiment of the present invention, Comparative Example 1, and Comparative Example 2 is completed, respectively. It is a diagram showing the current.

In the driving thin film transistor Tdr according to the embodiment of the present invention, the source electrode 146 and the semiconductor layer 132 are in direct contact with each other without the second non-reflective layer 138, and in the driving thin film transistor according to Comparative Example 1, the source electrode and a second non-reflective layer disposed between the semiconductor layers, and the second non-reflective layer is omitted in the driving thin film transistor according to Comparative Example 2.

As shown in FIG. 6A , in the driving thin film transistor Tdr according to the embodiment of the present invention, the source electrode 146 and the semiconductor layer 132 are in direct contact with each other without the second non-reflective layer 138, so the source electrode An ohmic contact is formed between 146 and the semiconductor layer 132, so that the current I linearly increases according to the voltage V in all ranges.

As shown in FIG. 6B , in the driving thin film transistor according to Comparative Example 1, since the second non-reflective layer having a relatively large resistivity is interposed between the source electrode and the semiconductor layer, a Schottky contact ( Schottky contact is formed and the current is kept constant according to the voltage (V) at a low voltage, but exhibits a diode characteristic in which the current rapidly increases according to the voltage (V) at a high voltage above a certain voltage, and as a result, the contact characteristic is deteriorated.

Accordingly, as shown in FIG. 7A , in the driving thin film transistor Tdr according to the embodiment of the present invention, the source and drain between the source electrode 146 and the drain electrode 152 in a low voltage linear region. The source-drain current Ids between the source electrode 146 and the drain electrode 152 increases linearly according to the voltage Vds, and in a high voltage saturation region, the source-drain current Ids increases according to the source-drain voltage Vds. It has a normal transistor characteristic in which the drain current Ids is kept constant.

On the other hand, as shown in FIG. 7B , in the driving thin film transistor according to Comparative Example 1, in the low-voltage linear region, the contact characteristic is deteriorated by the second non-reflective layer, and the source-drain current is linearly increased according to the source-drain voltage. It has an abnormal transistor characteristic that the source-drain current does not reach a specific value even in a high-voltage saturation region.

Meanwhile, as shown in FIGS. 8A and 9A , the driving thin film transistor Tdr according to the embodiment of the present invention has a low voltage V1 and a high voltage after completion of the gate electrode 140 and the completion of the display device 110 . Both of the source-drain voltages Vds of (V2) have an off-state and an on-state which are clearly distinguished according to the gate-source voltage Vgs between the gate electrode 140 and the source electrode 146 .

On the other hand, as shown in FIGS. 8B and 9B , in the driving thin film transistor according to Comparative Example 1, after completion of the gate electrode and after completion of the display device, the second non-reflective layer at the source-drain voltage Vds of the low voltage V1. has an off-state and an on-state that are not differentiated according to the gate-source voltage Vgs, and the off-state and the on-state are distinguished according to the gate-source voltage Vgs in the source-drain voltage Vds of the high voltage V2. It has degraded on-off characteristics such as swing or on-off ratio.

And, as shown in FIGS. 8C and 9C , the driving thin film transistor according to Comparative Example 2 has a source-drain voltage (Vds) of a low voltage (V1) and a high voltage (V2) after completion of the gate electrode and after completion of the display device. Both have an off-state and an on-state clearly distinguished according to the gate-source voltage Vgs.

That is, in the driving thin film transistor Tdr according to the embodiment of the present invention in which the source electrode 146 and the semiconductor layer 132 are in direct contact with each other without the second non-reflective layer 138, the second non-reflective layer is omitted. has the same electrical characteristics as those of the driving thin film transistor according to , and as a result, deterioration of the characteristics of the driving thin film transistor Tdr according to the embodiment of the present invention due to the second non-reflective layer 138 is prevented.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: display device 120: substrate
124: first non-reflective layer 132: semiconductor layer
136: gate insulating layer 138: second non-reflective layer
140: gate electrode 146: source electrode
152: drain electrode

Claims (15)

a substrate including at least one sub-pixel having a circuit region and a light emitting region;
a first anti-reflective layer and a light blocking layer sequentially disposed in the circuit region on the substrate;
a buffer layer disposed on the light blocking layer;
a semiconductor layer disposed on the buffer layer corresponding to the light blocking layer;
a gate insulating layer and a second non-reflective layer sequentially disposed on the semiconductor layer;
a gate electrode disposed on the second non-reflective layer corresponding to the central portion of the semiconductor layer;
a source electrode disposed on the second non-reflective layer corresponding to one end of the semiconductor layer and in contact with the light blocking layer through the first contact hole of the second non-reflective layer, the gate insulating layer, and the buffer layer;
a drain electrode disposed on the second non-reflective layer corresponding to the other end of the semiconductor layer;
a planarization layer disposed on the gate electrode, the source electrode, and the drain electrode;
A light emitting diode disposed on the planarization layer and connected to the source electrode
A display device comprising a.
The method of claim 1,
the source electrode is in contact with one end of the semiconductor layer through a source contact hole of the second non-reflective layer and the gate insulating layer;
The drain electrode is in contact with the other end of the semiconductor layer through a drain contact hole of the second non-reflective layer and the gate insulating layer.
The method of claim 1,
The light emitting diode is
a first electrode disposed on the at least one sub-pixel on the planarization layer;
a bank layer disposed on the first electrode and exposing the first electrode of the light emitting region;
a light emitting layer disposed on the first electrode in the light emitting region;
a second electrode disposed on the light emitting layer
display device comprising
4. The method of claim 3,
the first anti-reflective layer and a first capacitor electrode sequentially disposed in the circuit region between the substrate and the buffer layer;
a second capacitor electrode disposed on the buffer layer corresponding to the first capacitor electrode;
a protective layer disposed between the gate electrode, the source electrode, the drain electrode, and the second capacitor electrode and the planarization layer
further comprising,
The first electrode contacts the passivation layer corresponding to the second capacitor electrode through an opening exposing the passivation layer.
5. The method of claim 4,
The first electrode is in contact with the source electrode through a second contact hole of the planarization layer and the passivation layer.
The method of claim 1,
and a color filter layer disposed in the light emitting region between the buffer layer and the planarization layer.
The method of claim 1,
The first and second anti-reflective layers each include molybdenum oxide tantalum (MoOx:Ta),
The light blocking layer includes copper (Cu),
and the gate electrode, the source electrode, and the drain electrode each include a first layer of molybdenum titanium (MoTi) and a second layer of copper (Cu).
sequentially forming a first anti-reflective layer and a light-blocking layer in a circuit region of at least one sub-pixel on a substrate;
forming a buffer layer on the light blocking layer;
forming a semiconductor layer on the buffer layer corresponding to the light blocking layer;
sequentially forming a gate insulating layer and a second anti-reflective layer on the semiconductor layer;
A gate electrode is formed on the second anti-reflective layer corresponding to the central portion of the semiconductor layer, and the second anti-reflective layer, the gate insulating layer, and the buffer layer are formed on the second anti-reflective layer corresponding to one end of the semiconductor layer. forming a source electrode in contact with the light-shielding layer through a first contact hole in the semiconductor layer, and forming a drain electrode on the second non-reflective layer corresponding to the other end of the semiconductor layer;
forming a planarization layer on the gate electrode, the source electrode, and the drain electrode;
forming a light emitting diode connected to the source electrode on the planarization layer
A method of manufacturing a display device comprising a.
9. The method of claim 8,
Forming the gate insulating layer and the second non-reflective layer,
forming the gate insulating layer and the second anti-reflective layer on the semiconductor layer;
A first contact hole exposing the light blocking layer is formed in the second anti-reflective layer, the gate insulating layer, and the buffer layer, and both ends of the semiconductor layer are exposed to the second anti-reflective layer and the gate insulating layer. Forming a hole and a drain contact hole
A method of manufacturing a display device comprising a.
10. The method of claim 9,
The forming of the first contact hole, the source contact hole, and the drain contact hole may include:
forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness smaller than the first thickness on the second non-reflective layer by using an exposure mask having a transmissive portion, a semi-transmissive portion, and a blocking portion;
forming the first contact hole by etching the second anti-reflective layer, the gate insulating layer, and the buffer layer using the first and second photoresist patterns as etch masks;
removing the second photoresist pattern;
forming the source contact hole and the drain contact hole by etching the second anti-reflective layer and the gate insulating layer using the first photoresist pattern as an etch mask
A method of manufacturing a display device comprising a.
10. The method of claim 9,
The source electrode and the drain electrode are in contact with both ends of the semiconductor layer through the source contact hole and the drain contact hole, respectively.
9. The method of claim 8,
Forming the light emitting diode comprises:
forming a first electrode in the at least one sub-pixel on the planarization layer;
forming a bank layer exposing the first electrode of the light emitting region of the at least one subpixel on the first electrode;
forming a light emitting layer on the first electrode in the light emitting region;
forming a second electrode on the light emitting layer
A method of manufacturing a display device comprising a.
13. The method of claim 12,
sequentially forming the first anti-reflective layer and a first capacitor electrode in the circuit region between the substrate and the buffer layer;
forming a second capacitor electrode on the buffer layer corresponding to the first capacitor electrode;
forming a protective layer between the gate electrode, the source electrode, the drain electrode, and the second capacitor electrode and the planarization layer;
further comprising,
The first electrode contacts the protective layer corresponding to the second capacitor electrode through an opening exposing the protective layer.
14. The method of claim 13,
Forming the protective layer and the planarization layer,
forming a second contact hole exposing the source electrode in the protective layer and the planarization layer;
The first electrode is in contact with the source electrode through the second contact hole.
9. The method of claim 8,
and forming a color filter layer in an emission region of the at least one sub-pixel between the buffer layer and the planarization layer.

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