CN100557964C - Surge absorber - Google Patents

Abstract

The invention provides a kind of surge absorber, it possesses: the 1st terminal electrode, the 2nd terminal electrode, the 3rd terminal electrode, inductor portion, surge absorbing portion and resistance section.Inductor portion has the 1st inner conductor and the 2nd inner conductor of mutual polarity coupled in reverse wi.One end of the 1st inner conductor is connected with the 1st terminal electrode.One end of the 2nd inner conductor is connected with above-mentioned the 2nd terminal electrode.The other end of the 1st inner conductor is connected with the other end of the 2nd inner conductor.Surge absorbing portion has the 1st internal electrode and the 2nd internal electrode.The 1st internal electrode is connected on the other end of the other end of the 1st inner conductor and the 2nd inner conductor.The 2nd internal electrode is connected on the 3rd terminal electrode.Resistance section has the DC resistance component that is connected between the 1st terminal electrode and the 2nd terminal electrode.

Description

Surge absorbing element

Technical Field

The present invention relates to a surge absorbing element.

Background

Due to high-voltage static electricity, semiconductor devices such as ICs and LSIs are damaged or their characteristics are deteriorated. Therefore, an electric surge absorbing element such as a varistor (varistor) is used as a countermeasure against static electricity in a semiconductor device.

However, surge absorbing elements represented by varistors have a parasitic capacitance component and a parasitic inductance component. Therefore, if the surge absorbing element is applied to a circuit for processing a high-speed signal, the high-speed signal is deteriorated. In order to apply the surge absorbing element to a circuit for processing a high-speed signal, it is impossible to avoid deterioration of the rising characteristic and the delay characteristic of the high-speed signal without reducing the parasitic capacitance component of the surge absorbing element. However, if the parasitic capacitance component of the surge absorbing element is reduced, the rise of the control voltage and the energy capacity of the surge absorbing element are reduced.

As a surge absorbing element for reducing the influence of the parasitic capacitance component, a surge absorbing element including an inductor (inductor) and 2 varistors is known (for example, see japanese patent application laid-open No. 2001-60838). The surge absorbing element described in jp 2001-60838 a includes a parallel circuit including a1 st varistor and an inductor, a2 nd varistor electrically connected in series to the parallel circuit, an input/output electrode connected to both ends of the series circuit of the 2 nd varistor and the parallel circuit, and a ground electrode.

Disclosure of Invention

However, in the surge absorbing element described in japanese patent application laid-open No. 2001-60838, since the band pass filter is formed by the parasitic capacitance of the 1 st varistor and the inductor, it is difficult to obtain impedance matching in a wide frequency band. Therefore, sufficient characteristics cannot be achieved for high-speed signals.

The invention aims to provide a surge absorption element which is excellent in impedance matching even for high-speed signals.

The surge absorbing element of the present invention includes: a1 st terminal electrode; a2 nd terminal electrode; a3 rd terminal electrode; an inductor unit having a1 st inner conductor and a2 nd inner conductor which are coupled to each other in opposite polarities, one end of the 1 st inner conductor being connected to the 1 st terminal electrode, one end of the 2 nd inner conductor being connected to the 2 nd terminal electrode, and the other end of the 1 st inner conductor being connected to the other end of the 2 nd inner conductor; a surge absorbing portion having a1 st inner electrode connected to the other end of the 1 st inner conductor and the other end of the 2 nd inner conductor, and a2 nd inner electrode connected to the 3 rd terminal electrode; and a resistance portion having a direct current resistance component connected between the 1 st terminal electrode and the 2 nd terminal electrode.

In the surge absorbing element of the present invention, the inductor section includes a1 st inner conductor and a2 nd inner conductor which are coupled with each other in opposite polarities. Therefore, by appropriately setting the inductance of the inductor part with respect to the parasitic capacitance component of the surge absorbing part, the influence of the parasitic capacitance component can be eliminated. As a result, a flat input impedance having a frequency characteristic can be realized over a wide frequency band.

The surge absorbing element of the present invention further includes a resistance portion having a dc resistance component. This makes the surge absorbing element relatively high in impedance. Therefore, the surge absorbing element has a relatively higher impedance than a protected element such as an IC or LSI with respect to a high frequency component of an electrostatic pulse generated when a human body comes into contact with a terminal of an electronic device or the like. As a result, the passage of the Electrostatic pulse to the protected element can be suppressed, the Electrostatic pulse can be efficiently guided to the surge absorbing portion, and the level of ESD (Electrostatic Discharge) protection by the surge absorbing element can be increased.

Preferably, the dc resistance component of the resistor is set to be greater than 0 Ω and 7.5 Ω or less.

As one of the methods for transmitting digital signals between electronic devices, there is a differential transmission method. The differential transmission method is a method of inputting digital signals in opposite directions to 1-pair lines, and can cancel radiation noise or external noise generated by signal lines by differential transmission. In the differential transmission system, since noise is reduced by canceling out extraneous noise, a signal can be transmitted with a small amplitude. The differential transmission system has the following advantages: since the signal has a small amplitude, the rise and fall times of the signal are shortened, and the signal transmission is speeded up.

As Interface specifications using a Differential transmission system, there are USB (Universal Serial Bus), IEEE1394, LVDS (Low Voltage Differential Signaling), DVI (Digital Video Interface), HDMI (High-Definition Multimedia Interface), and the like. Among them, HDMI is an interface that can transmit more digital signals, and is a high-speed interface that can transmit uncompressed digital signals between a Source (Source) device (e.g., a DVD player, a set-top box, or the like) and a sink (sink) device (e.g., a digital television, a projector, or the like). The image signal and the sound signal can be transmitted at high speed by 1 cable by the HDMI.

In a high-speed interface such as HDMI, the structure of the IC itself is vulnerable to ESD in order to achieve high speed. Therefore, the demand for measures against ESD in high-speed transmission system ICs has increased.

However, it is again clear that: when a surge absorbing element as an ESD countermeasure component is inserted into a transmission line, a signal transmitted through the transmission line, particularly a high-frequency (200MHz or more) or high-speed pulse signal, has a problem of reflection and attenuation. This is due to the following reasons: that is, when the surge absorbing element is inserted into the transmission line, the characteristic impedance at the position of the transmission line where the surge absorbing element is inserted is lowered due to the capacitance component of the surge absorbing element, and the impedance is not matched at the position. When there is an impedance mismatch portion in the transmission line, a high-frequency component of the signal is reflected by the mismatch portion of the characteristic impedance, and thus a return loss (return loss) occurs. As a result, the signal is attenuated considerably. Further, unnecessary radiation is generated in the transmission line due to reflection, which causes noise. In the HDMI, a predetermined value (TDR Specification) of the characteristic impedance of a transmission line is defined as 100 Ω ± 15% (High-Definition Multimedia Interface Specification Version 1.1).

As described above, in the differential transmission system in which digital signals in opposite directions are input to 1 pair of lines, if the characteristic impedance of one line is within the range of 50 ± 7.5 Ω, impedance matching can be achieved. Therefore, by setting the dc resistance component of the resistor to be greater than 0 Ω and 7.5 Ω or less, impedance matching can be achieved even when a surge absorbing element is inserted into a transmission line of a differential transmission system such as HDMI.

Preferably, the resistance portion has a dc resistance component formed of the 1 st inner conductor and the 2 nd inner conductor. In this case, it is not necessary to separately provide a resistor or the like for constituting the resistance portion, and the configuration of the surge absorbing element can be simplified and the surge absorbing element can be downsized.

Preferably, a combined dc resistance component of the 1 st inner conductor and the 2 nd inner conductor is set to be greater than 0 Ω and 7.5 Ω or less. In this case, as described above, even when a surge absorbing element is inserted into a transmission line of a differential transmission system such as HDMI, impedance matching can be achieved.

Preferably, the surge absorbing element further includes a capacitor portion having a capacitance component connected between the 1 st terminal electrode and the 2 nd terminal electrode. This makes it possible to flexibly set the inductance of the inductor section and the capacitance of the capacitance component of the capacitor section with respect to the parasitic capacitance component of the surge absorbing section.

Preferably, the capacitor unit has a capacitance component formed by the 1 st inner conductor and the 2 nd inner conductor. In this case, it is not necessary to separately provide internal electrodes and the like for constituting the capacitor unit. Therefore, the element can be miniaturized while simplifying the configuration of the element.

Preferably, the inductor section is configured by laminating an inductor layer formed with a1 st inner conductor and an inductor layer formed with a2 nd inner conductor, the surge absorbing section is configured by laminating a varistor layer formed with a1 st inner electrode and a varistor layer formed with a2 nd inner electrode, the 1 st inner conductor and the 2 nd inner conductor include a region overlapping each other when viewed from a laminating direction of the inductor layers, and the 1 st inner electrode and the 2 nd inner electrode include a region overlapping each other when viewed from the laminating direction of the varistor layers. At this time, the 1 st inner conductor and the 2 nd inner conductor are capacitively coupled to each other in a region overlapping each other when viewed in the lamination direction of the inductor layers, and the capacitance component is formed between the regions. This eliminates the need for providing a separate internal electrode or the like for forming the capacitor portion, and simplifies the structure of the element and reduces the size of the element. The surge absorbing portion may be a varistor.

More preferably: each varistor layer contains ZnO as a main component, at least one element selected from rare earth elements and Bi as an additive, and Co; each inductor layer contains ZnO as a main component and substantially no Co. In this case, the varistor layer and the body of the inductor layer are mainly composed of the same material (ZnO). Therefore, even when these are integrally sintered, stress and the like are less likely to occur between the two layers due to the difference in the volume change rate of the element body during sintering. This greatly reduces the separation between the surge absorbing portion and the inductor portion. The material constituting the inductor layer, that is, the material containing ZnO as a main component and substantially not containing Co has a very high specific resistance and a low dielectric constant as compared with the ZnO material alone or the constituent material of the varistor layer (the material in which the rare earth element, Bi, or Co is added to ZnO). Therefore, the inductor layer containing the above material has excellent inductance characteristics.

Preferably, the 1 st, 2 nd and 3 rd terminal electrodes are formed on the outer surface of the element body including the inductor part, the surge absorbing part and the resistor part, and the other end of the 1 st inner conductor, the other end of the 2 nd inner conductor and the 1 st inner electrode are connected by an outer conductor formed on the outer surface of the element body. In this case, the other end of the 1 st inner conductor, the other end of the 2 nd inner conductor, and the 1 st inner electrode can be easily and reliably connected.

Preferably, the 1 st terminal electrode is an input terminal electrode, the 2 nd terminal electrode is an output terminal electrode, and the 1 st inner conductor and the 2 nd inner conductor are positively coupled.

Preferably, the first and second electrodes have a plurality of 1 st terminal electrodes, 2 nd terminal electrodes, 3 rd terminal electrodes, 1 st inner conductors, 2 nd inner conductors, 1 st inner electrodes, and 2 nd inner electrodes, respectively. In this case, the surge absorbing elements can be realized in an array.

Preferably, the resistance portion has a1 st direct current resistance component connected between the 1 st terminal electrode and the 1 st internal electrode, and a2 nd direct current resistance component larger than the 1 st direct current resistance component and connected between the 1 st internal electrode and the 2 nd terminal electrode. At this time, the impedance of the surge absorbing element, particularly, the circuit portion between the surge absorbing portion and the 2 nd terminal electrode becomes relatively large. Therefore, the circuit portion between the surge absorbing portion and the 2 nd terminal electrode has relatively higher impedance than a protected element such as an IC or LSI with respect to a high frequency component of an electrostatic pulse generated when a human body comes into contact with a terminal of an electronic device or the like. As a result, when the element to be protected is connected to the 2 nd terminal electrode, the passage of the electrostatic pulse to the element to be protected can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion, and the level of ESD protection by the surge absorbing element can be improved.

Preferably, the combined dc resistance component of the 1 st dc resistance component and the 2 nd dc resistance component is set to be greater than 0 Ω and 7.5 Ω or less. In this case, as described above, even when a surge absorbing element is inserted into the transmission line of the differential transmission system such as HDMI, impedance matching can be achieved.

Preferably, the 1 st direct current resistance component is formed by the 1 st inner conductor, and the 2 nd direct current resistance component is formed by the 2 nd inner conductor. In this case, it is not necessary to separately provide a resistor or the like for constituting the resistance portion, and the configuration of the surge absorbing element can be simplified and the surge absorbing element can be downsized.

Preferably, a combined dc resistance component of the 1 st inner conductor and the 2 nd inner conductor is set to be greater than 0 Ω and 7.5 Ω or less. In this case, as described above, even when a surge absorbing element is inserted into the transmission line of the differential transmission system such as HDMI, impedance matching can be achieved.

According to the present invention, a surge absorbing element excellent in impedance matching even for a high-speed signal can be provided. Further, according to the present invention, the level of protection of ESD using the surge absorbing element can be improved.

The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only and are not to be considered as limiting the present invention.

The scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Drawings

Fig. 1 is a perspective view schematically showing a surge absorbing element according to embodiment 1.

Fig. 2 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 1.

Fig. 3 is a diagram for explaining a circuit configuration of the surge absorbing element according to embodiment 1.

Fig. 4 is a diagram showing an equivalent circuit of the circuit configuration shown in fig. 3.

Fig. 5 is a diagram showing an equivalent circuit of the varistor.

Fig. 6 is a flowchart illustrating a process of manufacturing the surge absorbing element according to embodiment 1.

Fig. 7 is a perspective view schematically showing a surge absorbing element according to embodiment 2.

Fig. 8 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 2.

Fig. 9 is an exploded perspective view for explaining the structure of one modification of the element body included in the surge absorbing element according to embodiment 2.

Fig. 10 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 3.

Fig. 11 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 4.

Detailed Description

The best mode of the present invention will be described in detail below with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and redundant description thereof will be omitted.

(embodiment 1)

First, the structure of the surge absorbing element SA1 according to embodiment 1 will be described with reference to fig. 1 and 2. Fig. 1 is a perspective view schematically showing a surge absorbing element according to embodiment 1. Fig. 2 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 1.

As shown in fig. 1, the surge absorbing element SA1 includes an element body 1, a1 st terminal electrode 3, a2 nd terminal electrode 5, a3 rd terminal electrode 7, and an outer conductor 9. The element body 1 has a rectangular parallelepiped shape, and has a length of about 1mm, a width of about 0.5mm, and a height of about 0.3mm, for example. The 1 st terminal electrode 3 and the 2 nd terminal electrode 5 are formed at the ends of the element body 1 in the longitudinal direction, respectively. The 3 rd terminal electrode 7 and the outer conductor 9 are formed on the side surfaces of the element body 1 so as to face each other. The 1 st terminal electrode 3 functions as an input terminal electrode of the surge absorbing element SA 1. The 2 nd terminal electrode 5 functions as an output terminal electrode of the surge absorbing element SA 1. The 3 rd terminal electrode 7 functions as a ground terminal electrode of the surge absorbing element SA 1.

As shown in fig. 2, the element body 1 includes an inductor section 10 and a surge absorption section 20. The element body 1 has a structure in which a surge absorption portion 20, an inductor portion 10, and a protective layer 50 are laminated in this order from the bottom in the drawing.

The inductor section 10 has a1 st inner conductor 11 and a2 nd inner conductor 13 which are coupled with opposite polarities to each other. The inductor section 10 is configured by laminating an inductor layer 15 on which a1 st inner conductor 11 is formed and an inductor layer 17 on which a2 nd inner conductor 13 is formed.

One end of the 1 st inner conductor 11 is drawn out to the edge of the inductor layer 15 so as to be exposed at one end face of the element body 1 (the end face on which the 1 st terminal electrode 3 is formed). One end of the 1 st inner conductor 11 is physically and electrically connected to the 1 st terminal electrode 3. One end of the 2 nd inner conductor 13 is drawn out to the edge of the inductor layer 17 so as to be exposed at the other end face of the element body 1 (the end face on which the 2 nd terminal electrode 5 is formed). One end of the 2 nd inner conductor 13 is physically and electrically connected to the 2 nd terminal electrode 5. The other end of the 1 st inner conductor 11 and the other end of the 2 nd inner conductor 13 are drawn out to the edges of the inductor layers 15 and 17, respectively, so as to be exposed on the same side surface of the element body 1 (the side surface on which the outer conductor 9 is formed). The other end of the 1 st inner conductor 11 and the other end of the 2 nd inner conductor 13 are physically and electrically connected to the outer conductor 9 formed on the side surface of the element body 1. The other end of the 1 st inner conductor 11 and the other end of the 2 nd inner conductor 13 are electrically connected by the outer conductor 9.

The 1 st inner conductor 11 and the 2 nd inner conductor 13 include regions 11a and 13a that overlap each other when viewed in the lamination direction of the inductor layers 15 and 17. The 1 st inner conductor 11 and the 2 nd inner conductor 13 are capacitively coupled in the regions 11a, 13 a. The 1 st inner conductor 11 and the 2 nd inner conductor 13 may be connected to each other by a via conductor or the like formed inside the element body 1, instead of the outer conductor 9 described above. The conductive material contained in the 1 st inner conductor 11 and the 2 nd inner conductor 13 is not particularly limited, but is preferably made of Pd or an Ag — Pd alloy.

Each of the inductor layers 15 and 17 is made of a ceramic material containing ZnO as a main component. The ceramic material constituting the inductor layers 15 and 17 may contain, as an additive, a metal element such as rare earth (e.g., Pr), K, Na, Cs, or Rb in addition to ZnO. Among them, rare earth is particularly preferably added. By adding a rare earth element, the difference in the volume change rate between the inductor layers 15 and 17 and the varistor layers 25 and 27 described later can be easily reduced. In addition, the inductor layers 15 and 17 may further contain Cr, Ca, and Si in order to improve coupling with the surge absorption portion 20 described later. These metal elements contained in the inductor layers 15 and 17 may be present in various forms such as a simple metal, an oxide, and the like. The appropriate content of the additive contained in the inductor layers 15 and 17 is preferably 0.02 mol% or more and 2 mol% or less of the total amount of ZnO contained in the inductor layers 15 and 17. The content of these metal elements can be measured, for example, by an inductively coupled high-frequency plasma spectrometer (ICP).

The inductor layers 15 and 17 do not substantially contain Co contained in the varistor layers 25 and 27 described later. Here, the state of "substantially not containing" refers to a state in which these elements are not intentionally contained as raw materials when forming the inductor layers 15 and 17. For example, the case where these elements are unintentionally contained by diffusion from the surge absorbing portion 20 to the inductor portion 10 corresponds to a state of "substantially not containing". As long as the inductor layers 15 and 17 satisfy the above conditions, other metal elements and the like may be further contained for the purpose of further improving the characteristics and the like.

The surge absorbing element 20 has a1 st internal electrode 21 and a2 nd internal electrode 23. The surge absorbing portion 20 is formed by laminating a varistor layer 25 on which the 1 st internal electrode 21 is formed and a varistor layer 27 on which the 2 nd internal electrode 23 is formed.

The 1 st internal electrode 21 has a straight-line pattern extending in the short-side direction of the varistor layer 25. One end of the 1 st inner electrode 21 is drawn out to the edge of the varistor layer 25 so as to be exposed on the side surface of the element body 1 (the side surface on which the outer conductor 9 is formed). The other end of the 1 st inner electrode 21 is not exposed on the side surface of the element body 1 (the side surface on which the 3 rd terminal electrode 7 is formed), and is located at a position drawn from the side surface. One end of the 1 st inner electrode 21 is physically and electrically connected to the outer conductor 9 formed on the side surface of the element body 1. The other end of the 1 st inner conductor 11, the other end of the 2 nd inner conductor 13, and one end of the 1 st inner electrode 21 are electrically connected by the outer conductor 9.

The 2 nd internal electrode 23 has a straight-line pattern extending in the short side direction of the varistor layer 27. One end of the 2 nd inner electrode 23 is drawn out to the edge of the varistor layer 27 so as to be exposed on the side surface of the element body 1 (the side surface on which the 3 rd terminal electrode 7 is formed). The other end of the 2 nd inner electrode 23 is not exposed on the side surface of the element body 1 (the side surface on which the outer conductor 9 is formed), but is positioned to be drawn in from the side surface. One end of the 2 nd inner electrode 23 is physically and electrically connected to the 3 rd terminal electrode 7 formed on the side surface of the element body 1.

The 1 st internal electrode 21 and the 2 nd internal electrode 23 include regions 21a and 23a that overlap each other when viewed from the stacking direction of the varistor layers 25 and 27. Therefore, the regions 21a and 23a of the varistor layers 25 and 27 that overlap the 1 st internal electrode 21 and the 2 nd internal electrode 23 function as regions exhibiting varistor characteristics. The conductive material contained in the 1 st internal electrode 21 and the 2 nd internal electrode 23 is not particularly limited, but is preferably made of Pd or an Ag — Pd alloy.

Each varistor layer 25, 27 is made of a ceramic material containing ZnO as a main component. The ceramic material may further contain Co and at least one element selected from rare earths and Bi as an additive. Here, the varistor layers 25 and 27 contain Co in addition to rare earth elements, and therefore have high dielectric constant (∈) in addition to excellent current-voltage nonlinear characteristics (that is, variable resistance characteristics). On the other hand, the varistor layers 15 and 17 do not have varistor characteristics because they do not contain Co, and have a small dielectric constant and a high resistivity. Therefore, the inductor layers 15 and 17 have extremely suitable characteristics as the components of the inductor section 10. The ceramic material constituting the varistor layers 25 and 27 may contain Al as an additive. When Al is contained, the varistor layers 25 and 27 have low resistance. The rare earth element contained as an additive is preferably Pr.

The metal element as the additive may be present in the form of a simple metal or an oxide in the varistor layers 25 and 27. In order to further improve the characteristics, the varistor layers 25 and 27 may further contain metal elements other than the above elements (e.g., Cr, Ca, Si, K, etc.) as additives.

The 1 st inner conductor 11 has a1 st direct current resistance component. The 1 st direct current resistance component is inserted between the 1 st terminal electrode 3 and the 1 st internal electrode 21. That is, the 1 st direct current resistance component is connected between the 1 st terminal electrode 3 and the 1 st internal electrode 21, one end thereof is electrically connected to the 1 st terminal electrode 3, and the other end thereof is electrically connected to the 1 st internal electrode 21.

The 2 nd inner conductor 13 has a2 nd direct current resistance component. The 2 nd direct current resistance component is inserted between the 1 st internal electrode 21 and the 2 nd terminal electrode 5. That is, the 2 nd direct current resistance component is connected between the 1 st inner electrode 21 and the 2 nd terminal electrode 5, one end thereof is electrically connected to the 1 st inner electrode 21, and the other end thereof is electrically connected to the 2 nd terminal electrode 5.

The 2 nd inner conductor 13 has a2 nd direct-current resistance component set to be larger than the 1 st direct-current resistance component of the 1 st inner conductor 11. Further, a composite dc resistance component of the 1 st dc resistance component and the 2 nd dc resistance component is set to be larger than 0 Ω and 7.5 Ω or less. In the present embodiment, the 1 st inner conductor 11 has a1 st dc resistance component of about 0.5 Ω, and the 2 nd inner conductor 13 has a2 nd dc resistance component of about 4.5 Ω. Therefore, the combined dc resistance component of the 1 st dc resistance component and the 2 nd dc resistance component is about 5 Ω.

The protective layers 50 are each made of a ceramic material and protect the inductor unit 10. The material constituting the protective layer 50 is not particularly limited, and various ceramic materials and the like can be used, but from the viewpoint of reducing peeling from the above-described laminated structure, a material containing ZnO as a main component is preferably contained.

The 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, and the outer conductor 9 are preferably made of a metal material that can be electrically connected well to the metals such as Pd constituting the inner conductors 11 and 13 and the inner electrodes 21 and 23. For example, Ag is suitable as a material for the external electrodes because it has good electrical connectivity with the internal conductors 11 and 13 and the internal electrodes 21 and 23 made of Pd, and good adhesion to the end faces of the element body 1.

Ni plating (not shown), Sn plating (not shown), and the like are sequentially formed on the surfaces of the 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, and the outer conductor 9. These plating layers are formed mainly for improving solder heat resistance and solder wettability when the surge absorption element SA1 is mounted on a substrate or the like by reflow soldering.

Next, a circuit configuration of the surge absorbing element SA1 having the above-described configuration will be described with reference to fig. 3 and 4. Fig. 3 is a diagram for explaining a circuit configuration of the surge absorbing element according to embodiment 1. Fig. 4 is a diagram showing an equivalent circuit of the circuit configuration shown in fig. 3.

The 1 st inner conductor 11 and the 2 nd inner conductor 13 include regions 11a and 13a overlapping each other when viewed from the lamination direction of the inductor layers 15 and 17, respectively, as described above, and are capacitively coupled to the regions 11a and 13 a. Therefore, the surge absorbing element SA1 has a capacitance component 61 formed by the 1 st inner conductor 11 and the 2 nd inner conductor 13, as shown in fig. 3. The capacitance component 61 is connected between the 1 st terminal electrode 3 and the 2 nd terminal electrode 5.

The 1 st inner conductor 11 has an inductance component and a1 st direct current resistance component 62a connected in series. The 2 nd inner conductor 13 has an inductance component and a2 nd direct current resistance component 62b connected in series. Thus, as shown in fig. 3, the surge absorbing element SA1 has a dc resistance component 62 (a combined resistance component of the 1 st dc resistance component 62a and the 2 nd dc resistance component 62 b) formed by the 1 st inner conductor 11 and the 2 nd inner conductor 13. The direct-current resistance component 62 is electrically connected between the 1 st terminal electrode 3 and the 2 nd terminal electrode 5. The 2 nd dc resistance component 62b is, as described above, larger than the 1 st dc resistance component 62 a.

Here, the term "polarity-reversed coupling" means that, as shown in fig. 3, when the winding start position of the inductance component corresponding to the 1 st inner conductor 11 is set to the 1 st terminal electrode 3 side and the winding start position of the inductance component corresponding to the 2 nd inner conductor 13 is set to the side connected to the 1 st inner conductor 11 (the outer conductor 9 side in the present embodiment), the coupling between the 1 st inner conductor 11 and the 2 nd inner conductor 13 is "positive". That is, the "polarity-reverse coupling" means that a current flows into the 1 st inner conductor 11 from the 1 st terminal electrode 3 side, a current flows into the 2 nd inner conductor 13 from the side connected to the 1 st inner conductor 11 (the outer conductor 9 side in the present embodiment), and a magnetic flux generated in the 1 st inner conductor 11 and a magnetic flux generated in the 2 nd inner conductor 13 are mutually intensified.

In the surge absorbing element SA1, the 1 st inner electrode 21, the 2 nd inner electrode 23, and the regions 21a and 23a of the varistor layers 25 and 27 that overlap the 1 st inner electrode 21 and the 2 nd inner electrode 23 constitute one varistor 63. As shown in fig. 3, the varistor 63 is electrically connected between the 3 rd terminal electrode 7 and a connection point (outer conductor 9) between the 1 st inner conductor 11 and the 2 nd inner conductor 13.

The 1 st inner conductor 11 and the 2 nd inner conductor 13, which are coupled to each other in reverse polarity, may be converted into a1 st inductance component 65, a2 nd inductance component 67, and a3 rd inductance component 69, as shown in fig. 4. The 1 st inductance component 65 and the 2 nd inductance component 67 are connected in series between the 1 st terminal electrode 3 and the 2 nd terminal electrode 5. The 3 rd inductance component 69 is connected between the connection point of the 1 st inductance component 65 and the 2 nd inductance component 67 connected in series and the varistor 63. When the inductance of each of the inner conductors 11 and 13 is Lz and the coupling coefficient between the inner conductors 11 and 13 is Kz, the inductance of the 1 st inductance component 65 and the 2 nd inductance component 67 is (1+ Kz) Lz, and the inductance of the 3 rd inductance component 69 is-KzLz.

The varistor 63, as shown in fig. 4, can be converted into a varistor 71 and a parasitic capacitance component 73 connected in parallel between the 3 rd inductance component 69 and the 3 rd terminal electrode 7. The variable resistor 71 is generally large in resistance value, and becomes small in resistance value when a high voltage surge is applied. In the varistor 63, for a high-speed signal of small amplitude, only the parasitic capacitance component 73 can be approximated.

The input impedance Zin of the surge absorbing element SA1 shown in fig. 4 is expressed by the following equation (1). Here, the capacitance of the capacitance component 61 is Cs, and the capacitance of the parasitic capacitance component 73 of the varistor 63 is Cz. Further, since the dc resistance has a small influence on the impedance, equations relating to the capacitance component and the inductance component are examined.

<math> <mrow> <mi>Zin</mi> <mo>=</mo> <msqrt> <mfrac> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Lz</mi> </mrow> <mi>Cz</mi> </mfrac> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cz</mi> <mo>/</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cs</mi> <mo>)</mo> </mrow> </mrow> </mfrac> </msqrt> <mo>.</mo> <mo>.</mo> <mo>.</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>

In the equation (1), if the capacitance Cs of the capacitance component 61 is set so as to satisfy the following equation (2), the input impedance Zin does not depend on the frequency characteristic. When the capacitance Cs of the capacitance component 61 is set to the following expression (2) and the inductance Lz of each internal conductor is set as shown in the following expression (3), the input impedance Zin can be matched to the characteristic impedance Zo.

$\mathrm{Cs}=\frac{1-\mathrm{Kz}}{4(1+\mathrm{Kz})}\mathrm{Cz}...\left(2\right)$

$\mathrm{Lz}=\frac{{Z_0}^2\mathrm{Cz}}{2(1+\mathrm{Kz})}...\left(3\right)$

As is clear from the above expressions (2) and (3), since the coupling coefficient Kz between the internal conductors 11 and 13 is arbitrarily selected, a highly flexible circuit design can be performed.

Therefore, according to the present embodiment, the surge absorbing element SA1 can be a surge absorbing element that protects a semiconductor device or the like from high-voltage static electricity and has excellent impedance matching even for a high-speed signal.

As shown in fig. 5, the varistor 63 also contains a parasitic inductance component 75. Normally, the resistance value of the variable resistor 71 is large, and becomes small when a high voltage surge is applied. However, the varistor 63 has a parasitic capacitance component 73 and a parasitic inductance component 75. Therefore, if the surge absorbing element SA1 is added to the input side of the semiconductor device that processes the high-speed signal as the input signal, the high-speed signal is degraded. In order to apply the surge absorbing element SA1 to a circuit for processing a high-speed signal, it is preferable to reduce the influence of not only the parasitic capacitance component 73 but also the parasitic inductance component 75.

As is clear from the equivalent circuit shown in fig. 4, when the 3 rd inductance component 69 having a negative inductance is used, the parasitic inductance component 75 of the varistor 63 can be eliminated. However, since it seems that the coupling is in the same state as the state in which the coupling is reduced, the coupling coefficient Kz and the inductance Lz are kept unchanged, and the capacitance Cs of the capacitance component 61 is set to the following expression (4). Here, let the inductance of the parasitic inductance component 75 be Le.

$\mathrm{Cs}=\frac{1-\mathrm{Kz}+2\mathrm{Le}/\mathrm{Lz}}{4(1+\mathrm{Kz})}\mathrm{Cz}...\left(4\right)$

However, Kzlz ≧ Le. With this configuration, even if the surge absorbing element SA1 includes the parasitic capacitance component 73 and the parasitic inductance component 75, the input impedance Zin can be matched to the characteristic impedance Zo.

Next, a method of manufacturing the surge absorbing element SA1 according to embodiment 1 will be described with reference to fig. 6. Fig. 6 is a flowchart for explaining a process of manufacturing the surge absorbing element according to embodiment 1.

In manufacturing the surge absorbing element SA1, first, a paste containing a ceramic material to be a raw material of the inductor layers 15 and 17 and the varistor layers 25 and 27 is manufactured (step S101). Specifically, the paste for forming the varistor layers 25 and 27 can be prepared by adding at least one element selected from rare earth elements (e.g., Pr) and Bi, Co, and if necessary, Al, Cr, Ca, Si, K, etc., as additives to ZnO as a main component, making the contents thereof a desired content after firing, and adding and mixing these binders. The metal element in this case may be added as an oxide, for example.

The paste for forming the inductor layers 15 and 17 can be prepared by adding a metal element such as rare earth and Bi as an additive to ZnO as a main component, if necessary, and further adding a binder to the metal element and the additive, and mixing the resulting mixture. The paste for forming the inductor layers 15 and 17 is different from the paste for forming the varistors 25 and 27, and no Co is added. The metal element may be added in the form of a compound such as an oxide, oxalate or carbonate. The amounts of these elements added are adjusted so that the metal element has the above-mentioned desired content in the element assembly 1 after sintering, which will be described later.

These pastes are applied to a plastic film or the like by a doctor blade method or the like and then dried to form a green sheet made of a ceramic material (step S102). Thus, the required number of pieces of green sheets for forming the inductor layers 15 and 17 (hereinafter referred to as "inductor sheets") and the required number of pieces of green sheets for forming the varistor layers 25 and 27 (hereinafter referred to as "varistor sheets") are obtained. In the formation of the green sheet, the plastic film or the like may be peeled off from each sheet immediately after coating and drying, or may be peeled off before lamination described later. In the green sheet forming step, a green sheet for forming the ZnO-containing protective layer 50 is formed simultaneously with the above sheets by the same method as described above.

Next, on the inductor chip or the varistor chip, a conductor paste for forming the 1 st and 2 nd inner conductors 11 and 13 or the 1 st and 2 nd inner electrodes 21 and 23 is screen-printed on each chip so as to form a desired pattern (step S103). Thus, each sheet provided with a conductor paste layer having a desired pattern was obtained. Here, the conductor paste layers having the desired patterns for obtaining the 1 st and 2 nd inner conductors 11 and 13 are formed so that the 1 st and 2 nd inner conductors 11 and 13 obtained by firing in the subsequent step have the desired dc resistance components, respectively. Examples of the conductor paste include a conductor paste containing Pd or an Ag — Pd alloy as a main component.

Next, varistor sheets having conductor paste layers corresponding to the 1 st and 2 nd internal electrodes 21 and 23, respectively, are sequentially stacked (step S104). Then, inductor pieces provided with conductor paste layers corresponding to the 1 st and 2 nd inner conductors 11, 13, respectively, are sequentially stacked thereon (step S105). Further, a green sheet for forming the protective layer 50 is further stacked on these laminated structures, and these are pressure-welded to obtain a laminate which is a precursor of the element body 1.

Then, the obtained laminate is cut into a desired size into a chip unit, and the chip is sintered at a predetermined temperature (for example, 1000 to 1400 ℃) to obtain an element body 1 (step S106). Subsequently, Li is diffused from the surface of the obtained body 1 into the inside thereof. Here, after the Li compound is attached to the surface of the obtained body 1, heat treatment or the like is performed. For the adhesion of the Li compound, a sealed rotary pot can be used. The Li compound is not particularly limited, but it is a compound that can diffuse Li from the surface of the element body 1 to the vicinity of the 1 st and 2 nd inner conductors 11, 13 and the 1 st and 2 nd inner electrodes 21, 23 by heat treatment, and examples thereof include oxides, hydroxides, chlorides, nitrates, borates, carbonates, oxalates, and the like of Li. In the manufacture of the surge absorbing element SA1, this Li diffusion step is not essential.

Then, by transferring a paste containing silver as a main component onto the side surface of the element body 1 in which Li is diffused, sintering the paste, and plating the paste, the 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, and the external conductor 9 are formed, respectively, to obtain the surge absorbing element SA1 (step S107). The plating layer may be performed by electroplating, and for example, Cu and Ni and Sn, Ni and Au, Ni and Pd and Ag, or Ni and Ag, or the like may be used.

As described above, in embodiment 1, the inductor section 10 includes the 1 st inner conductor 11 and the 2 nd inner conductor 13 that are coupled to each other in opposite polarities. Therefore, by appropriately setting the inductance of the inductor unit 10 with respect to the parasitic capacitance component 73 of the surge absorbing unit 20, the influence of the parasitic capacitance component 73 can be eliminated. As a result, an input impedance having flat frequency characteristics over a wide frequency band can be realized.

In embodiment 1, the surge absorbing element SA1 includes a resistor portion having a dc resistance component 62. Thereby, the impedance of the surge absorbing element SA1 becomes relatively large. Therefore, the surge absorbing element SA1 has a relatively higher impedance than a protected element such as an IC or LSI with respect to a high frequency component of the electrostatic pulse. As a result, the passage of the electrostatic pulse to the protected element can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion 20 (varistor 63), and the ESD protection level by the surge absorbing element SA1 can be improved.

Further, in embodiment 1, the resistance portion has a1 st dc resistance component 62a and a2 nd dc resistance component 62b larger than the 1 st dc resistance component 62 a. Thereby, the impedance of the surge absorbing element SA1, particularly, the circuit portion between the surge absorbing portion 20 (varistor 63) and the 2 nd terminal electrode 5 becomes relatively large. Therefore, the circuit portion between the surge absorbing portion 20 (varistor 63) and the 2 nd terminal electrode 5 has a relatively higher impedance than a protected element such as an IC or LSI with respect to a high frequency component of an electrostatic pulse generated when a human body comes into contact with a terminal of an electronic device or the like. As a result, when the element to be protected is connected to the 2 nd terminal electrode 5, the passage of the electrostatic pulse to the element to be protected can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion 20 (varistor 63), and the ESD protection level by the surge absorbing element SA1 can be improved.

In embodiment 1, the combined dc resistance component of the 1 st dc resistance component 62a and the 2 nd dc resistance component 62b is set to be greater than 0 Ω and 7.5 Ω or less. Thus, even when the surge absorbing element SA1 is inserted into a transmission line of a differential transmission system such as HDMI, impedance matching can be achieved.

In embodiment 1, the 1 st dc resistance component 62a is formed by the 1 st inner conductor 11, and the 2 nd dc resistance component 62b is formed by the 2 nd inner conductor 13. In this case, it is not necessary to separately provide a resistor or the like for constituting the resistor section, and the configuration of the element SA1 can be simplified and the element SA1 can be downsized. In embodiment 1, the combined dc resistance component of the 1 st dc resistance component 62a of the 1 st inner conductor 11 and the 2 nd dc resistance component 62b of the 2 nd inner conductor 13 is set to be greater than 0 Ω and 7.5 Ω or less.

In embodiment 1, the surge absorbing element SA1 further includes a capacitor unit having a capacitance component 61. This makes it possible to flexibly set the inductance of the inductor unit 10 and the capacitance of the capacitor unit capacitance component 61 with respect to the parasitic capacitance component 73 of the surge absorbing unit 20.

The surge absorbing element SA1 according to embodiment 1 can be a surge absorbing element SA1 that protects semiconductor devices and the like from high-voltage static electricity and is excellent in impedance matching even for high-speed signals.

In embodiment 1, the capacitance component 61 of the capacitor unit is formed by the 1 st inner conductor 11 and the 2 nd inner conductor 13. This eliminates the need for providing a separate internal electrode or the like for constituting the capacitor unit 40, simplifies the configuration of the surge absorbing element SA1, and enables the surge absorbing element SA1 to be downsized.

In embodiment 1, the inductor section 10 is configured by laminating an inductor layer 15 formed with a1 st inner conductor 11 and an inductor layer 17 formed with a2 nd inner conductor 13, and the 1 st inner electrode 11 and the 2 nd inner electrode 13 include regions 11a and 13a overlapping each other when viewed from a laminating direction of the inductor layers 15 and 17. As a result, capacitive coupling is achieved between the regions 11a, 13a of the 1 st inner conductor 11 and the 2 nd inner conductor 13 that overlap each other when viewed in the stacking direction of the inductor layers 15, 17, and the capacitance component 61 is formed by the regions 11a, 13 a. This eliminates the need for providing a separate internal electrode or the like for constituting the capacitor unit, simplifies the structure of the surge absorbing element SA1, and reduces the size of the surge absorbing element SA 1.

In embodiment 1, the surge absorbing portion 20 is configured by laminating a varistor layer 25 having a1 st internal electrode 21 and a varistor layer 27 having a2 nd internal electrode 23, and the 1 st internal electrode 21 and the 2 nd internal electrode 23 include regions overlapping each other when viewed from the laminating direction of the varistor layers 25 and 27. Thus, the varistor 63 can constitute the surge absorbing unit 20.

In embodiment 1, the inductor layers 15 and 17 constituting the inductor section 10 and the varistor layers 25 and 27 constituting the surge absorbing section 20 are each formed of a ceramic material containing ZnO as a main component. Therefore, the difference in volume change occurring at the time of firing is extremely small in the inductor portion 10 and the surge absorbing portion 20. Therefore, even if they are sintered at the same time, deformation, stress, and the like are hardly generated therebetween. As a result, the obtained surge absorbing element SA1 is extremely less likely to peel off from the inductor section 10 and the surge absorbing section 20, compared to the surge absorbing element SA1 of the related art in which the two are formed of different materials.

As described above, the inductor layers 15 and 17 are made of a ceramic material containing ZnO as a main component and substantially no Co as an additive. Such a material has a sufficiently high degree of resistivity as a constituent material of the inductor. Specifically, it is easy to be a material having a resistivity exceeding 1M Ω suitable as an inductor material. Therefore, the inductor section 10 can exhibit excellent inductor characteristics, although containing ZnO as a main component, which has insufficient characteristics in terms of resistivity alone.

In embodiment 1, the other end of the 1 st inner conductor 11, the other end of the 2 nd inner conductor 13, and the 1 st inner electrode 21 are connected by the outer conductor 9. This makes it possible to easily and reliably connect the other end of the 1 st inner conductor 11, the other end of the 2 nd inner conductor 13, and the 1 st inner electrode 21.

As a method of adjusting the 1 st dc resistance component 62a of the 1 st inner conductor 11 and the 2 nd dc resistance component 62b of the 2 nd inner conductor 13 to the desired values, there is the following method. The width, thickness, line length, or the like of the 1 st and 2 nd inner conductors 11, 13 is adjusted. The metal material contained in the conductor paste used to form the 1 st and 2 nd inner conductors 11, 13 is selected, whereby the resistivity is adjusted. The densities of the 1 st and 2 nd inner conductors 11 and 13 are adjusted by adjusting the mixing ratio of the metal materials contained in the conductor paste or adjusting the particle size of the metal materials.

(embodiment 2)

Next, the structure of the surge absorbing element SA2 according to embodiment 2 will be described with reference to fig. 7 and 8. Fig. 7 is a perspective view schematically showing a surge absorbing element according to embodiment 2. Fig. 8 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 2. The surge absorbing element SA2 according to embodiment 2 is different from the surge absorbing element SA1 according to embodiment 1 in the number of the 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, the 1 st inner conductor 11, the 2 nd inner conductor 13, the 1 st inner electrode 21, the 2 nd inner electrode 23, and the outer conductor 9.

As shown in fig. 7, the surge absorbing element SA2 includes an element body 1. The element body 1 has a rectangular parallelepiped shape, and has a length of about 1.4mm, a width of about 1.0mm, and a height of about 0.5mm, for example. The surge absorbing element SA2 includes a plurality of (2 in the present embodiment) 1 st terminal electrode 3, 2 nd terminal electrode 5, 3 rd terminal electrode 7, and outer conductor 9, respectively. The 1 st, 2 nd and 3 rd terminal electrodes 3, 5, 7 are formed on the side surfaces of the element body 1 so as to face each other. The outer conductors 9 are formed at the ends of the element body 1 in the longitudinal direction.

As shown in fig. 8, the inductor unit 10 includes a plurality of (2 in the present embodiment) 1 st inner conductors 11 and 2 nd inner conductors 13 having mutually opposite polarities and coupled to each other. The 1 st inner conductors 11 are electrically insulated from each other by a predetermined distance on the inductor layer 15. The 2 nd inner conductors 13 are electrically insulated from each other by a predetermined distance on the inductor layer 17.

The DC resistance component of each 2 nd inner conductor 13 is larger than that of each 1 st inner conductor 11. The combined dc resistance component of the dc resistance component of each 1 st inner conductor 11 and the dc resistance component of each 2 nd inner conductor 13 is set to be greater than 0 Ω and 7.5 Ω or less, respectively. In the surge absorbing element SA2, the inductor section 10 has a dc resistance component greater than 0 Ω and equal to or less than 15 Ω. In the present embodiment, the dc resistance component of each 1 st inner conductor 11 is set to about 0.5 Ω, and the dc resistance component of each 2 nd inner conductor 13 is also set to about 4.5 Ω. Therefore, in the surge absorbing element SA2, the inductor section 10 has a dc resistance component of about 10 Ω.

As shown in fig. 8, the surge absorbing portion 20 includes a plurality of (2 in the present embodiment) 1 st and 2 nd internal electrodes 21 and 23, respectively.

On the varistor layer 25, the 1 st internal electrodes 21 are electrically insulated from each other by a predetermined distance. Each 1 st internal electrode 21 includes a1 st electrode portion 31 and a2 nd electrode portion 33. The 1 st electrode portion 31 and a1 st electrode portion 35 of a2 nd inner electrode 23 described later overlap each other when viewed from the laminating direction of the varistors 25, 27. The 1 st electrode portion 31 has a substantially rectangular shape. The 2 nd electrode portion 33 is drawn from the 1 st electrode portion 31 so as to be exposed on the side surface of the element body 1 (the side surface on which the outer conductor 9 is formed), and functions as a lead conductor. Each 1 st electrode portion 31 is electrically connected to the outer conductor 9 through the 2 nd electrode portion 33. The 2 nd electrode part 33 is formed integrally with the 1 st electrode part 31.

Each 2 nd internal electrode 23 includes a1 st electrode portion 35 and a2 nd electrode portion 37. The 1 st electrode portion 35 is formed to overlap with the 1 st electrode portion 31 of the 1 st inner electrode 21 as viewed from the laminating direction of the varistors 25, 27. The 1 st electrode portions 35 are each substantially rectangular in shape. The 2 nd electrode portion 37 is drawn from each 1 st electrode portion 35 so as to be exposed on both side surfaces of the element body 1 (both side surfaces on which the 3 rd terminal electrode 7 is formed), and functions as a lead conductor. Each 1 st electrode portion 35 is electrically connected to the 3 rd terminal electrode 7 through the 2 nd electrode portion 37. The 2 nd electrode portion 37 is formed integrally with the 1 st electrode portion 35.

As shown in fig. 9, the 2 nd inner electrodes 23 may have a predetermined distance therebetween in the varistor layer 27 so as to be electrically insulated from each other. At this time, as shown in fig. 9, the 2 nd electrode portions 37 are drawn out from the 1 st electrode portions 35, respectively, to be exposed on the side surfaces of the element body 1 (the both side surfaces on which the 3 rd terminal electrode 7 is formed).

In the surge absorbing portion 20, one varistor is constituted by the 1 st electrode portion 31, the 1 st electrode portion 35, and the region where the 1 st electrode portion 31 and the 1 st electrode portion 35 overlap in the varistor layers 25, 27.

As described above, in embodiment 2, as in embodiment 1, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching with respect to a high-speed signal is further excellent.

In embodiment 2, as in embodiment 1, the passage of the electrostatic pulse to the element to be protected can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion 20 (varistor 63), and the ESD protection level by the surge absorbing element SA2 can be improved.

In embodiment 2, the first embodiment includes a plurality of the 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, the 1 st inner conductor 11, the 2 nd inner conductor 13, the 1 st inner electrode 21, and the 2 nd inner electrode 23. This makes it possible to realize surge absorbing elements SA2 in an array form.

(embodiment 3)

Next, the structure of the surge absorbing element according to embodiment 3 will be described with reference to fig. 10. Fig. 10 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 3. The surge absorbing element of embodiment 3 is different from the surge absorbing element SA1 of embodiment 1 in the structure of the capacitor unit 40.

The surge absorbing device according to embodiment 3 includes an element body 1, a1 st terminal electrode 3, a2 nd terminal electrode 5, a3 rd terminal electrode 7, and an outer conductor 9, similarly to the surge absorbing device SA1 shown in fig. 1. As shown in fig. 10, the element body 1 includes an inductor section 10, a surge absorption section 20, and a capacitor section 40. The element body 1 has a structure in which a surge absorption section 20, an inductor section 10, a capacitor section 40, and a protective layer 50 are laminated in this order from the bottom in the drawing.

The DC resistance component of the 2 nd inner conductor 13 is larger than that of the 1 st inner conductor 11. The combined dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 is set to be greater than 0 Ω and 7.5 Ω or less, respectively. In the surge absorbing element according to embodiment 3, the inductor section 10 has a dc resistance component greater than 0 Ω and equal to or less than 15 Ω. In the present embodiment, the dc resistance component of the 1 st inner conductor 11 is set to about 0.5 Ω, and the dc resistance component of the 2 nd inner conductor 13 is also set to about 4.5 Ω. Therefore, in the surge absorbing element according to embodiment 3, the inductor section 10 has a dc resistance component of about 10 Ω.

The capacitor unit 40 has a3 rd internal electrode 41 and a 4 th internal electrode 43. The capacitor unit 40 is configured by laminating an insulator layer 45 on which the 3 rd internal electrode 41 is formed and an insulator layer 47 on which the 4 th internal electrode 43 is formed.

The 3 rd internal electrode 41 includes a1 st electrode part 41a and a2 nd electrode part 41 b. The 1 st electrode portion 41a overlaps with a1 st electrode portion 43a of a 4 th internal electrode 43 described later, as viewed from the laminating direction of the insulator layers 45 and 47. The 1 st electrode portion 41a has a substantially rectangular shape. The 2 nd electrode portion 41b is led out from the 1 st electrode portion 41a so as to be exposed at one end face of the element body 1 (the end face on which the 1 st terminal electrode 3 is formed), and functions as an lead conductor. The 1 st electrode part 41a is electrically connected to the 1 st terminal electrode 3 through the 2 nd electrode part 41 b. The 2 nd electrode part 41b is integrally formed with the 1 st electrode part 41 a.

The 4 th internal electrode 43 includes a1 st electrode part 43a and a2 nd electrode part 43 b. The 1 st electrode portion 43a overlaps the 1 st electrode portion 41a of the 3 rd inner electrode 41 as viewed in the stacking direction of the insulator layers 45 and 47. The 1 st electrode portion 43a has a substantially rectangular shape. The 2 nd electrode portion 43b is led out from the 1 st electrode portion 43a to be exposed at the other end face of the element body 1 (the end face on which the 2 nd terminal electrode 5 is formed), and functions as an lead conductor. The 1 st electrode part 43a is electrically connected to the 2 nd terminal electrode 5 through the 2 nd electrode part 43 b. The 2 nd electrode part 43b is formed integrally with the 1 st electrode part 43 a.

The 1 st electrode portion 41a of the 3 rd internal electrode 41 is capacitively coupled to the 1 st electrode portion 43a of the 4 th internal electrode 43, and a capacitance component 61 is formed by the 3 rd internal electrode 41 and the 4 th internal electrode 43. Thus, the capacitor part 40 has a capacitance component 61 connected between the 1 st terminal electrode 3 and the 2 nd terminal electrode 5.

Each of the insulator layers 45 and 47 is a layer made of a ceramic material. The material constituting the insulator layers 45 and 47 is not particularly limited, and various ceramic materials and the like can be used, but a material containing ZnO as a main component is preferable from the viewpoint of reducing peeling from the laminated structure.

As described above, in embodiment 3, as in embodiment 1, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching with respect to a high-speed signal is further excellent.

In embodiment 3, as in embodiment 1, the passage of the electrostatic pulse to the element to be protected can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion 20 (varistor 63), and the ESD protection level by the surge absorbing element SA3 can be improved.

(embodiment 4)

Next, the structure of the surge absorbing element according to embodiment 4 will be described with reference to fig. 11. Fig. 11 is an exploded perspective view for explaining the structure of the element body included in the surge absorbing element according to embodiment 4. The surge absorbing element according to embodiment 4 is different from the surge absorbing element SA2 according to embodiment 2 in the structure of the inductor unit 10 and the surge absorbing unit 20.

The surge absorbing device according to embodiment 4 includes a plurality of (2 in the present embodiment) element bodies 1, a1 st terminal electrode 3, a2 nd terminal electrode 5, a3 rd terminal electrode 7, and an outer conductor 9, respectively, as in the surge absorbing device SA2 shown in fig. 7.

The inductor section 10 includes a plurality of (2 layers in this embodiment) inductor layers 15 each having the 1 st inner conductor 11 formed thereon and an inductor layer 17 each having the 2 nd inner conductor 13 formed thereon. The inductor section 10 is configured by laminating an inductor layer 15 and an inductor layer 17 in a paired manner.

The DC resistance component of each 2 nd inner conductor 13 is larger than that of the 1 st inner conductor 11. The combined dc resistance component of the dc resistance component of each 1 st inner conductor 11 and the dc resistance component of each 2 nd inner conductor 13 is set to be greater than 0 Ω and 7.5 Ω or less, respectively. In the surge absorbing element according to embodiment 4, the inductor section 10 has a dc resistance component greater than 0 Ω and equal to or less than 15 Ω. In the present embodiment, the dc resistance component of each 1 st inner conductor 11 is set to about 0.5 Ω, and the dc resistance component of each 2 nd inner conductor 13 is also set to about 4.5 Ω. Therefore, in the surge absorbing element according to embodiment 4, the inductor section 10 has a dc resistance component of about 10 Ω.

The inductor section 10 includes a plurality of (2 layers in the present embodiment) insulating layers (dummy layers) 19 in which no internal conductor is formed. Insulator layer 19 is located between the 1 st pair of inductor layers, which is formed by inductor layer 15 and inductor layer 17, and the 2 nd pair of inductor layers, which is formed by inductor layer 15 and inductor layer 17. The insulator layer 19 is a layer for suppressing reverse coupling of the polarity of the 2 nd inner conductor 13 formed on the inductor layer 17 constituting the 1 st inductor layer pair and the 1 st inner conductor 11 formed on the inductor layer 15 constituting the 2 nd inductor layer pair. The material constituting the insulator layer 19 is not particularly limited, and various ceramic materials and the like can be used, but from the viewpoint of reducing delamination from the laminated structure, a material containing ZnO as a main component is preferable as in the inductor layers 15 and 17.

A plurality of (2 layers in this embodiment) insulator layers (dummy layers) 51 having no internal conductor formed thereon are also located below the inductor section 10. An insulator layer (dummy layer) having no internal conductor formed may be located between the inductor layer 15 and the inductor layer 17 constituting the 1 st inductor layer pair. An insulator layer (dummy layer) where no internal conductor is formed may be located between the inductor layer 15 and the inductor layer 17 constituting the 2 nd inductor layer pair.

In the surge absorbing device according to embodiment 4, when the length and width of the element body 1 are the same, that is, the areas of the inductor layers 15 and 17 are the same, as compared to the surge absorbing device SA2 according to embodiment 2, the coil area determined by the 1 st inner conductor 11 and the 2 nd inner conductor 13 can be set to be large. As a result, the surge absorbing element of embodiment 4 can have a larger inductance (inductance value) than the surge absorbing element SA2 of embodiment 2.

The surge absorbing portion 20 includes a plurality of (2 in the present embodiment) 1 st and 2 nd inner electrodes 21 and 23, respectively. A plurality of insulator layers (dummy layers) in which no internal conductor is formed are located between the inductor section 10 and the surge absorbing section 20. The plurality of insulator layers (dummy layers) 28 and 29, on which no internal conductor is formed, are located above and below the surge absorbing portion 20 so as to sandwich the surge absorbing portion 20. The constituent material of the insulator layers 28 and 29 is not particularly limited, and various ceramic materials and the like can be used, but from the viewpoint of reducing peeling from the above-described laminated structure, a material containing ZnO as a main component is preferable, as in the varistors 25 and 27. An insulator layer (dummy layer) not formed with an internal conductor may also be located between the varistor layer 25 and the varistor layer 27.

On the varistor layer 25, the 1 st internal electrodes 21 are electrically insulated from each other by a predetermined distance. On the varistor layer 27, the 2 nd internal electrodes 23 are electrically insulated from each other with a predetermined interval. Each 1 st internal electrode 21 includes a1 st electrode portion 31 and a2 nd electrode portion 33. Each 2 nd internal electrode 23 includes a1 st electrode portion 35 and a2 nd electrode portion 37. The 1 st electrode portion 31 and the 1 st electrode portion 35 overlap each other as viewed in the laminating direction of the varistor layers 25, 27. The 1 st electrode portion 31 and the 1 st electrode portion 35 each have a substantially trapezoidal shape.

In the surge absorbing element according to embodiment 4, the area of the portion where the 1 st electrode part 31 and the 1 st electrode part 35 overlap each other is set to be larger than the surge absorbing element SA2 according to embodiment 2. This makes it possible to reduce the Equivalent Series Resistance (ESR) and the equivalent series inductance (ESL). The predetermined interval between the 1 st internal electrodes 21 is set to a value that can suppress the occurrence of crosstalk, taking into account the crosstalk between the 1 st internal electrodes 21. The predetermined interval between the 2 nd internal electrodes 23 is set to a value that can suppress the occurrence of crosstalk, taking into account the crosstalk between the 2 nd internal electrodes 23.

As described above, in embodiment 4, as in embodiment 1, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching with respect to a high-speed signal is further excellent.

In embodiment 4, as in embodiment 1, the passage of the electrostatic pulse to the element to be protected can be suppressed, the electrostatic pulse can be efficiently guided to the surge absorbing portion 20 (varistor 63), and the ESD protection level by the surge absorbing element can be improved.

In embodiment 4, the 1 st terminal electrode 3, the 2 nd terminal electrode 5, the 3 rd terminal electrode 7, the 1 st inner conductor 11, the 2 nd inner conductor 13, the 1 st inner electrode 21, and the 2 nd inner electrode 23 are provided in plural numbers. This makes it possible to realize surge absorbing elements formed in an array.

The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

The dc resistance components of the 1 st inner conductor 11 and the 2 nd inner conductor 13 are not limited to the above values. As described above, it is preferable if the dc resistance component of the 2 nd inner conductor 13 is larger than the dc resistance component of the 1 st inner conductor 11, and the combined dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 is larger than 0 Ω and 7.5 Ω or less. The 1 st inner conductor 11 may have a dc resistance component of 0 Ω.

The dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 may be the same. In this case, the combined dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 is also preferably larger than 0 Ω and 7.5 Ω or less. For example, in embodiment 1, the dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 may be set to about 2.5 Ω, respectively. At this time, the resultant dc resistance component of the 1 st inner conductor 11 and the dc resistance component of the 2 nd inner conductor 13 is about 5 Ω. In embodiments 2 to 4, the dc resistance component of each 1 st inner conductor 11 and the dc resistance component of each 2 nd inner conductor 13 may be set to about 2.5 Ω, respectively. At this time, the inductor portion 10 of the surge absorbing element has a dc resistance component of about 10 Ω.

In the above embodiment, the 1 st direct current resistance component 62a is formed by the 1 st inner conductor 11, and the 2 nd direct current resistance component 62b is formed by the 2 nd inner conductor 13, but the present invention is not limited thereto. For example, the 1 st dc resistance component 62a may be formed by a resistance connected in series to the 1 st inner conductor 11, or the 2 nd dc resistance component 62b may be formed by a resistance connected in series to the 2 nd inner conductor 13.

The surge absorbing element of the present invention can be configured as an equivalent circuit or a circuit having the same function as the equivalent circuit, and the formation position of the laminated structure, the electrode, and the like can be arbitrarily changed. That is, although the configuration in which the inductor unit 10 is provided on the surge absorbing unit 20 is exemplified in the above embodiment, for example, a configuration in which the inductor unit 10 is sandwiched between a pair of surge absorbing units 20 may be adopted. In addition, the positional relationship between the terminal electrodes 3 to 7 and the external conductor 9 may be arbitrarily changed. Even with these structures, the surge absorbing element SA1 having excellent effects as described above can be obtained.

Although the varistor 63 is used as the surge absorbing portion 20 in the present embodiment, the present invention is not limited thereto. As the surge absorbing unit 20, a capacitor, a PN junction (e.g., a zener diode, a silicon surge clamp, or the like), a gap discharge element, or the like may be used.

The number of stacked layers of the inductor unit 10, the surge absorbing unit 20, the capacitor unit 40, and the protective layer 50 is not limited to the above embodiment. That is, for example, the number of windings in the coil pattern can be further increased by repeatedly laminating the inductor layers 15 and 17 having the internal conductors formed thereon. In addition, the varistor layers 25 and 27 having the internal electrodes formed thereon may be further repeatedly stacked. The number of these layers can be appropriately adjusted according to the desired characteristics of the surge absorbing element.

When the inner conductors are laminated in the inductor portion 10 of the surge absorbing element, if the materials constituting the inductor layers 15 and 17 have a high dielectric constant, the inner conductors adjacent to each other in the laminating direction are coupled to each other, and a parasitic capacitance is generated between the inner conductors. Therefore, the surge absorbing element having the structure in which the inductor section 10 is laminated with the internal conductor tends to be difficult to be applied to high frequency applications in particular. From such a viewpoint, the dielectric constant of the inductor layers 15 and 17 is preferably low, and specifically, the dielectric constant is preferably 50 or less.

As is apparent from the above description, the present invention can be modified in various ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims (18)

1. A surge absorbing element is characterized by comprising:

a1 st terminal electrode;

a2 nd terminal electrode;

a3 rd terminal electrode;

an inductor unit having a1 st inner conductor and a2 nd inner conductor which are coupled to each other in opposite polarities, one end of the 1 st inner conductor being connected to the 1 st terminal electrode, one end of the 2 nd inner conductor being connected to the 2 nd terminal electrode, and the other end of the 1 st inner conductor being connected to the other end of the 2 nd inner conductor;

a surge absorbing portion having a1 st inner electrode connected to the other end of the 1 st inner conductor and the other end of the 2 nd inner conductor, and a2 nd inner electrode connected to the 3 rd terminal electrode;

a resistance unit having a direct-current resistance component connected between the 1 st terminal electrode and the 2 nd terminal electrode; and

a capacitor part having a capacitance component connected between the 1 st terminal electrode and the 2 nd terminal electrode,

wherein,

an input impedance Zin, a characteristic impedance Zo, an inductance Lz of the 1 st inner conductor and the 2 nd inner conductor, a coupling coefficient Kz between the 1 st inner conductor and the 2 nd inner conductor, a capacitance Cs of the capacitance component, a capacitance Cz of a parasitic capacitance component of the surge absorption portion, and an inductance Le of a parasitic inductance component of the surge absorption portion satisfy the following equations (1) to (4),

<math> <mrow> <mi>Zin</mi> <mo>=</mo> <msqrt> <mfrac> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Lz</mi> </mrow> <mi>Cz</mi> </mfrac> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cz</mi> <mo>/</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cs</mi> <mo>)</mo> </mrow> </mrow> </mfrac> </msqrt> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Cs</mi> <mo>=</mo> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> </mrow> <mrow> <mn>4</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>Cz</mi> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Lz</mi> <mo>=</mo> <mfrac> <mrow> <msup> <msub> <mi>Z</mi> <mn>0</mn> </msub> <mn>2</mn> </msup> <mi>Cz</mi> </mrow> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>3</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Cs</mi> <mo>=</mo> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> <mo>+</mo> <mn>2</mn> <mi>Le</mi> <mo>/</mo> <mi>Lz</mi> </mrow> <mrow> <mn>4</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>Cz</mi> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>4</mn> <mo>)</mo> </mrow> <mo>.</mo> </mrow> </math>

2. a surge absorbing element according to claim 1,

the resistance portion has the DC resistance component set to be greater than 0 Ω and 7.5 Ω or less.

3. A surge absorbing element according to claim 1 or 2,

the resistance part has the dc resistance component formed of the 1 st inner conductor and the 2 nd inner conductor.

4. A surge absorbing element according to claim 3,

the resultant DC resistance component of the 1 st inner conductor DC resistance component and the 2 nd inner conductor DC resistance component is set to be greater than 0 Ω and 7.5 Ω or less.

5. A surge absorbing element according to claim 1,

the capacitor unit has a capacitance component formed by the 1 st inner conductor and the 2 nd inner conductor.

6. A surge absorbing element according to claim 1,

the inductor section is configured by laminating an inductor layer on which the 1 st inner conductor is formed and an inductor layer on which the 2 nd inner conductor is formed,

the surge absorbing portion is formed by laminating a varistor layer having the 1 st internal electrode and a varistor layer having the 2 nd internal electrode,

the 1 st inner conductor and the 2 nd inner conductor include regions overlapping each other when viewed from a stacking direction of the inductor layers,

the 1 st internal electrode and the 2 nd internal electrode include regions overlapping each other when viewed from the stacking direction of the varistor layers.

7. A surge absorbing element according to claim 6,

each varistor layer contains ZnO as a main component, at least one element selected from rare earth elements and Bi as an additive, and Co,

each of the inductor layers contains ZnO as a main component and substantially does not contain Co.

8. A surge absorbing element according to claim 1,

wherein the 1 st terminal electrode, the 2 nd terminal electrode, and the 3 rd terminal electrode are formed on an outer surface of an element body including the inductor part, the surge absorbing part, and the resistor part,

the other end of the 1 st inner conductor, the other end of the 2 nd inner conductor, and the 1 st inner electrode are connected by an outer conductor formed on the outer surface of the element body.

9. A surge absorbing element according to claim 1,

the 1 st terminal electrode is an input terminal electrode,

the 2 nd terminal electrode is an output terminal electrode,

the 1 st inner conductor and the 2 nd inner conductor are positively coupled.

10. A surge absorbing element according to claim 1,

the first terminal electrode, the second terminal electrode, the third terminal electrode, the fourth inner conductor, the fourth inner electrode, and the fourth inner electrode are provided in plural numbers.

11. A surge absorbing element according to claim 6,

each varistor layer contains ZnO as a main component and Pr and Co as additives,

each of the inductor layers contains ZnO as a main component, contains Pr as an additive, and substantially does not contain Co,

the content of the additive contained in the inductor layer is 0.02 mol% or more and 2 mol% or less of the total amount of ZnO contained in the inductor layer.

12. A surge absorbing element according to claim 1,

the resistance part has a1 st direct current resistance component connected between the 1 st terminal electrode and the 1 st internal electrode, and a2 nd direct current resistance component which is larger than the 1 st direct current resistance component and connected between the 1 st internal electrode and the 2 nd terminal electrode.

13. A surge absorbing element according to claim 12,

the composite DC resistance component of the 1 st DC resistance component and the 2 nd DC resistance component is set to be larger than 0 Ω and 7.5 Ω or less.

14. A surge absorbing element according to claim 12 or 13,

the 1 st direct current resistance component is formed by the 1 st inner conductor, and the 2 nd direct current resistance component is formed by the 2 nd inner conductor.

15. A surge absorbing element according to claim 14,

the resultant DC resistance component of the 1 st inner conductor DC resistance component and the 2 nd inner conductor DC resistance component is set to be greater than 0 Ω and 7.5 Ω or less.

16. A surge absorbing element according to claim 1,

the capacitor unit has a capacitance component formed by the 1 st inner conductor and the 2 nd inner conductor.

17. A surge absorbing element according to claim 12,

the 1 st terminal electrode is an input terminal electrode,

the 2 nd terminal electrode is an output terminal electrode,

the 1 st inner conductor and the 2 nd inner conductor are positively coupled.

18. A surge absorbing element is characterized by comprising:

a1 st terminal electrode;

a2 nd terminal electrode;

a3 rd terminal electrode;

an inductor unit having a1 st inner conductor and a2 nd inner conductor which are coupled to each other in opposite polarities, one end of the 1 st inner conductor being connected to the 1 st terminal electrode, one end of the 2 nd inner conductor being connected to the 2 nd terminal electrode, and the other end of the 1 st inner conductor being connected to the other end of the 2 nd inner conductor;

a surge absorbing portion having a1 st inner electrode connected to the other end of the 1 st inner conductor and the other end of the 2 nd inner conductor, and a2 nd inner electrode connected to the 3 rd terminal electrode;

a resistance unit having a1 st direct current resistance component connected between the 1 st terminal electrode and the 1 st internal electrode, and a2 nd direct current resistance component larger than the 1 st direct current resistance component and connected between the 1 st internal electrode and the 2 nd terminal electrode; and

a capacitor part having a capacitance component connected between the 1 st terminal electrode and the 2 nd terminal electrode,

wherein,

an input impedance Zin, a characteristic impedance Zo, an inductance Lz of the 1 st inner conductor and the 2 nd inner conductor, a coupling coefficient Kz between the 1 st inner conductor and the 2 nd inner conductor, a capacitance Cs of the capacitance component, a capacitance Cz of a parasitic capacitance component of the surge absorption portion, and an inductance Le of a parasitic inductance component of the surge absorption portion satisfy the following equations (1) to (4),

<math> <mrow> <mi>Zin</mi> <mo>=</mo> <msqrt> <mfrac> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Lz</mi> </mrow> <mi>Cz</mi> </mfrac> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cz</mi> <mo>/</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> <mrow> <mn>1</mn> <mo>-</mo> <msup> <mi>&omega;</mi> <mn>2</mn> </msup> <mi>Lz</mi> <mrow> <mo>(</mo> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> <mi>Cs</mi> <mo>)</mo> </mrow> </mrow> </mfrac> </msqrt> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Cs</mi> <mo>=</mo> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> </mrow> <mrow> <mn>4</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>Cz</mi> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Lz</mi> <mo>=</mo> <mfrac> <mrow> <msup> <msub> <mi>Z</mi> <mn>0</mn> </msub> <mn>2</mn> </msup> <mi>Cz</mi> </mrow> <mrow> <mn>2</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>3</mn> <mo>)</mo> </mrow> </mrow> </math>

<math> <mrow> <mi>Cs</mi> <mo>=</mo> <mfrac> <mrow> <mn>1</mn> <mo>-</mo> <mi>Kz</mi> <mo>+</mo> <mn>2</mn> <mi>Le</mi> <mo>/</mo> <mi>Lz</mi> </mrow> <mrow> <mn>4</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>Kz</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>Cz</mi> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>4</mn> <mo>)</mo> </mrow> <mo>.</mo> </mrow> </math>

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