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CN100468775C - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN100468775C
CN100468775C CNB2006100714793A CN200610071479A CN100468775C CN 100468775 C CN100468775 C CN 100468775C CN B2006100714793 A CNB2006100714793 A CN B2006100714793A CN 200610071479 A CN200610071479 A CN 200610071479A CN 100468775 C CN100468775 C CN 100468775C
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大竹诚治
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Sanyo Electric Co Ltd
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Abstract

本发明涉及一种半导体装置，在现有的半导体装置中，由于N沟道型MOS晶体管的漏极结构，而存在ON电阻值增大的问题。在本发明的半导体装置中，在P型衬底(1)上堆积有N型外延层(2)。在外延层(2)上形成有作为背栅极区域使用的P型扩散层(5)。作为漏极区域使用的N型扩散层(8)包围P型扩散层(5)的周围而形成。而且，P型扩散层(5)和N型扩散层(8)将其一部分区域重叠。根据该结构，可使漏极-源极间的分开距离缩短，且可降低ON电阻值。另外，由于可在漏极区域形成浓度斜度，故可在缩小元件形成区域的同时，维持耐压特性。

Description

半导体装置
技术领域
本发明涉及通过漏极区域的结构降低ON电阻值，实现大电流化的半导体装置。
背景技术
作为现有的半导体装置，公知有如下技术。例如，在CMOS晶体管中，在硅衬底上形成有P型阱区域和N型阱区域。在P型阱区域形成有N沟道型MOS晶体管。在N型阱区域形成有P沟道型MOS晶体管。例如，在N沟道型MOS晶体管中，在P型阱区域形成有由LDD结构构成的源极区域和漏极区域。此时，源极区域和漏极区域是在形成于硅衬底上的P型阱区域上离子注入N型杂质而形成的(例如参照专利文献1)。
另外，作为现有的半导体装置，公知有如下技术。例如，在N沟道型MOS半导体装置中，在P型单晶硅衬底上堆积有N型外延层。在N型外延层上形成有P型阱区域。在P型阱区域形成有N型源极区域。P型阱区域相对N型外延层上的栅极电极，形成到其局部下方。N型漏极区域在P型阱区域附近形成于N型外延层上。而且，栅极氧化膜形成将漏极区域侧形成得较厚，将源极区域侧形成得较薄。利用该栅极氧化膜的结构，防止由漏极区域侧的高电场造成的硅氧化膜的特性变动(例如参照专利文献2)。
专利文献1:特开2004-140404号公报(第10-11页，第1-2图)
专利文献2:特开2002-314065号公报(第5-7页，第1-2图)
如上所述，在现有的半导体装置中，在CMOS晶体管的N沟道型MOS晶体管中，在P型阱区域形成有N型源极区域及漏极区域。因此，在P型阱区域和N型源极区域及漏极区域上难以将杂质浓度相互消除而得到所希望的杂质浓度。而且，在使N型源极区域及漏极区域成为高浓度杂质区域的情况下，耗尽层的形成区域变窄，产生MOS晶体管的耐压恶化的问题。另外，在使P型阱区域的杂质浓度为低浓度的情况下，耗尽层向沟道侧的形成区域扩宽，产生MOS晶体管增大的问题。
另外，在现有的半导体装置中，在N沟道型MOS晶体管中，存在有厚地形成漏极区域侧的栅极氧化膜以及薄地形成源极区域侧的栅极氧化膜的情况。在该情况下，漏极区域形成至厚的栅极氧化膜的下方。而且，在P型阱区域形成沟道区域，且沟道区域与漏极区域分离形成。根据该结构，P型阱区域和漏极区域分离，使电流路径变长，产生ON(导通)电阻值增大的问题。另外，由于改变栅极氧化膜的膜厚而形成，因而存在制造工艺复杂且耗费制造成本的问题。
发明内容
本发明是鉴于上述各情况而构成的，本发明的半导体装置具有:一种导电类型的半导体衬底；层积于所述半导体衬底上的反向导电类型的外延层；形成于所述外延层上面的栅极氧化膜及栅极电极；形成于所述半导体衬底和所述外延层上的反向导电类型的埋入扩散层；形成于所述外延层上，并且在底部与所述埋入扩散层重叠的一种导电类型的背栅极扩散层；形成于所述外延层上且至少一部分与所述背栅极扩散层重叠，并且所述重叠了的区域成为反向导电类型的扩散区域的反向导电类型的漏极扩散层；形成于所述背栅极扩散层上的反向导电类型的源极扩散层；与所述漏极扩散层连接的漏极电极；与所述源极扩散层连接的源极电极。因此，在本发明中，在栅极电极的下方，成为沟道形成区域的一种导电类型的背栅极扩散层和反向导电类型的漏极扩散层局部重叠而形成。根据该结构，可缩短漏极-源极间的分离距离，且可降低ON电阻值。
另外，本发明的半导体装置中，所述漏极扩散层包围所述背栅极扩散层而形成一环状。因此，在本发明中，漏极扩散层包围背栅极扩散层而形成一环状。根据该结构，可提高电流能力。另外，由于可有效地配置漏极扩散层，故可缩小元件形成区域。
本发明的半导体装置中，在所述漏极扩散层上一环状地形成有漏极接触扩散层。因此，在本发明中，使元件形成区域缩小，但可通过在漏极扩散层的浓度斜度来维持电场缓和。
本发明的半导体装置中，具有形成于所述背栅极扩散层上且位于所述源极扩散层附近的一种导电类型的背栅极接触扩散层，所述源极电极与所述源极扩散层及所述背栅极接触扩散层连接。因此，在本发明中，源极电极相对源极扩散层和背栅极接触扩散层共用接触。根据该结构，可将元件形成区域缩小。
在本发明中，在N型外延层上形成有P型背栅极扩散层。另一方面，在外延层上形成有N型漏极扩散层，以使背栅极扩散层与形成区域的一部分重叠。根据该结构，可使漏极-源极间的离开距离缩短，且可降低ON电阻值。
在本发明中，漏极扩散层和背栅极扩散层重叠的区域形成为N型扩散区域。根据该结构，漏极扩散层具有杂质浓度随着接近源极扩散层侧而降低的浓度斜度。而且，即使将元件形成区域缩小，也可以维持耐压特性。
在本发明中，漏极扩散层包围背栅极扩散层而形成一环状。根据该结构，可有效地配置漏极扩散层，且可将元件形成区域缩小，同时实现大电流化。
另外，在本发明中，使用N沟道型MOS晶体管构成电荷泵电路。根据该电路结构，可通过降低电荷传送用MOS晶体管的ON电阻值来实现大电流化。
附图说明
图1是说明本发明实施例的半导体装置的剖面图；
图2是说明本发明实施例的半导体装置的上面图；
图3是以往的实施例的电荷泵装置的电路图；
图4是本发明实施例的电荷泵装置的电路图；
图5是说明本发明实施例的电荷泵装置的剖面图。
符号说明
1  P型单晶硅衬底
2  N型外延层
3  P型隔离区域
4  N型埋入扩散层
5  P型扩散层
8  N型扩散层
10 栅极电极
具体实施方式
下面，参照图1及图2详细说明本发明一实施例的半导体装置。图1是用于说明本发明实施例的半导体装置的剖面图。图2是说明本发明实施例的半导体装置的上面图。
如图1所示，N沟道型MOS晶体管主要由P型单晶硅衬底1、N型外延层2、P型隔离区域3、N型埋入扩散层4、作为背栅极区域使用的P型扩散层5、作为源极区域使用的N型扩散层6、7、作为漏极区域使用的N型扩散层8、9以及栅极电极10构成。
N型外延层2形成于P型单晶硅衬底1上面。另外，在本实施例中，表示了在衬底1上形成有一层外延层2的情况，但不限于该情况。例如，也可以仅为衬底的情况，还可以为在衬底上面层积有多个外延层的情况。另外，衬底也可以为N型单晶硅衬底、化合物半导体衬底。
P型隔离区域3将从衬底1表面向上下方向扩散的P型埋入扩散层和从外延层2表面扩散的P型扩散层连结而形成。隔离区域3将衬底1与外延层2区分，在衬底1和外延层2上形成有多个岛区域。
N型埋入扩散层4形成于衬底1和外延层2上。根据该结构，P型衬底1和P型扩散层5通过N型埋入扩散层4而电分离。而且，在埋入扩散层4上例如可施加漏极电压，且可在P型衬底1和P型扩散层5上施加单独的电位。
P型扩散层5形成于外延层2上。P型扩散层5通过从外延层2表面离子注入P型杂质，例如以140～170keV的加速电压、1.0×1012～0×1014/cm2的导入量离子注入硼(B)而形成。P型扩散层5在深部使其至少一部分与N型埋入扩散层4重叠地形成。
N型扩散层6、7形成于P型扩散层5上。N型扩散层6、7用作为源极区域。N型扩散层6与N型扩散层7的形成区域重叠形成。而且，N型扩散层6的杂质浓度比N型扩散层7的杂质浓度高，实现接触电阻的降低等。
N型扩散层8、9形成于外延层2上。N型扩散层8、9用作为漏极区域。由圆标记11包围，如剖面线所示，N型扩散层8使其一部分与P型扩散层5重叠而形成。N型扩散层8通过从外延层2表面离子注入N型杂质，例如以30～60keV的加速电压、1.0×1014～1.0×1016/cm2的导入量离子注入磷(P)而形成。而且，P型扩散层5和N型扩散层8重叠的区域校正N型杂质浓度和P型杂质浓度，成为低浓度的N型扩散区域。另一方面，N型扩散层9与N型扩散层8的形成区域重叠而形成。而且，N型扩散层9的杂质浓度比N型扩散层8的杂质浓度高。
即，在漏极区域，具有从N型扩散层9向与P型扩散层5重叠的N型扩散层8的浓度斜度。而且，P型扩散层5和N型扩散层8重叠的区域形成为N型低浓度区域。根据该结构，由于可有效地将漏极区域向源极区域侧配置，因此可将漏极-源极间的电流经路缩短，且可降低ON电阻。另外，通过使P型扩散层5和N型扩散层8重叠，可缩小元件形成区域。
另一方面，由圆标记11包围其由剖面线所示的重叠区域被作为漏极区域使用，配置于栅极电极10的下方。根据该结构，可通过漏极区域的低浓度区域对来自栅极电极的垂直方向电场谋求电场缓和。另外，从源极区域朝向漏极区域的沟道方向电场在漏极区域的端部最大。对沟道方向的电场也相同，根据上述结构，可通过漏极区域的低浓度区域谋求电场缓和。即，元件形成区域缩小，但可谋求漏极区域的电场缓和，且可维持MOS晶体管的耐压特性。
栅极电极10形成于栅极氧化膜12上面。栅极电极10由多晶硅膜形成。在栅极电极10的侧壁形成有侧壁13。而且，在栅极电极10的上面形成有TEOS(Tetra-Ethyl-Orso-Silicate)膜14及氮化硅膜15。
LOCOS(Local Oxidation of Silicon)氧化膜16形成于外延层2上。在LOCOS氧化膜16的平坦部，其膜厚例如为3000～5000
Figure C200610071479D0007122416QIETU
左右。
绝缘层17形成于外延层2上面。绝缘层17堆积BPSG(Boron PhosphoSilicate Glass)膜、SOG(Spin On Glass)膜等形成。而且，使用公知的光刻技术，例如由使用CHF3+O2类气体的干式蚀刻在绝缘层17上形成接触孔18、19、20。
接触孔18、19、20由阻挡金属膜(バリアメタル膜)21及钨(W)膜22埋设。在钨膜22的表面选择地形成铝铜(AlCu)膜及阻挡金属膜，形成漏极电极23及源极电极24。在P型扩散层5上形成P型扩散层25作为背栅极接触区域。而且，源极电极24与成为源极区域的N型扩散层6和P型扩散层25连接。根据该结构，可不必分别地形成背栅极电极，而可实现元件的微细化。另外，在图1所示的截面，向栅极电极10连接的配线层未图示，但在其它区域与配线层连接。
如图2所示，从外侧开始，实线26与P型分散区域3对应，虚线27与N型扩散层8对应，虚线28与N型埋入扩散层4对应，点划线29与P型扩散层5对应，双点划线30与N型扩散层6对应，三点划线31与P型扩散层25对应。
如图所示，成为漏极区域的N型扩散层8在P型扩散层5周围形成一环状。如上所述，剖面线所示的区域是P型扩散层5与N型扩散层8重叠的区域，成为低浓度的N型扩散区域。根据该结构，可高效地配置漏极区域。另外，在P型扩散层5上，被N型扩散层6包围而形成作为背栅极接触区域的P型扩散层25。根据该结构，可使背栅极接触区域为一处，且可将源极电极兼用作背栅电极。即，在本实施例中，可在提高电流能力的同时，缩小元件形成区域。
另外，在本实施例中，对使漏极区域在背栅极区域周围一环状形成的情况进行了说明，但不限于该情况。例如，也可以是将漏极区域配置在相对的侧边等，将区分的漏极区域在背栅极区域的周围配置多个的情况。另外，在不脱离本发明主旨的范围内，可进行各种变更。
其次，参照图3～图5详细说明使用由图1及图2说明了的N沟道型MOS晶体管的电荷泵装置。图3是四级的迪克森电荷泵装置(デイクソン·チヤ—ジポンプ装
Figure C200610071479D0008122502QIETU
)的电路图。图4是将图3所示的二极管元件置换为MOS晶体管元件时的四级的迪克森电荷泵装置的电路图。图5是图4所示的迪克森电荷泵装置的电荷传输用的MOS晶体管的剖面图。
首先，对迪克森电荷泵装置进行说明。
如图3所示，将二极管D1～D5串联连接。C1～C4是在各二极管D1～D5的连接点连接的耦合电容(Coupling Capacitor)。CL是输出电容(OutputCapacitor)，CLK和CLKB是相互反相的输入时钟脉冲。另外，虚线所示的41是输入有CLK及CLKB的时钟驱动器，实线所示的42是电流负载。向时钟驱动器41供给电源电压。由此，从时钟驱动器4l输出的时钟脉冲ヨ1、ヨ2的输出振幅约为Vdd。并且，将时钟脉冲ヨ1供给向电容C2、C4，将时钟脉冲ヨ2供给向电容C1、C3。
在稳定状态下，在输出上流过稳定电流Iout时，向电荷泵装置输入的电流成为来自输入电压Vin的电流和从时钟驱动器供给的电流。这些电流若与向寄生电容充放电的电流无关，则如下地，在F1＝高(High)，F2＝低(Low)期间，沿图中实线箭头方向流过2Iout的平均电流。
另外，在F1＝低(Low)，F2＝高(High)期间，沿图中虚线箭头方向流过2Iout的平均电流。时钟循环下的这些平均电流全部为Iout。稳定状态下的电荷泵装置的升压电压Vout如下表示。
式1
V out = V in - V d + n ( V φ ′ - V 1 - V d )
在此，是在各连接节点，伴随时钟脉冲的变化而由耦合电容产生的电压振幅。V1是由输出电流Iout产生的压降，Vin是输入电压，通常正升压时为0V。Vd是顺向偏压二极管电压(Forward bias diode voltage)，n是泵浦级数。另外，V1和由下式表示。
数2
V 1 = I out f ( C + C S ) = 2 I out T / 2 C + C s
数3
V φ ′ = V φ C C + C S
在此，C1～C4是时钟耦合电容(Clock coupling Capacitor)，Cs是各连接节点的寄生电容(stray capacitance at each node)，Vφ是时钟脉冲的振幅(clock pulse amplitude)，f是时钟脉冲的频率，T是时钟周期(clock period)。电荷泵装置的输出效率与从时钟驱动器流向寄生电容的充放电电流无关，为Vin＝Vdd，由下式表示。
数4
η = V out I out ( n + 1 ) V dd I out = V out ( n + 1 ) V dd
这样，在电荷泵装置中，将二极管作为电荷输送元件(charge transferdevice)使用，通过将电荷一级级地向下一级输送而进行升压。但是，在考虑向半导体集成电路装置搭载时，从工艺的适合性出发，与pn结二极管相比，使用MOS晶体管容易实现。
如图4所示，作为电荷输送元件，使用MOS晶体管M1～M5来代替二极管D1～D5。此时，式(1)中Vd为MOS晶体管的阈值电压(thresholdvoltage)Vth。
如图5所示，表示电荷输送用MOS晶体管M2、M3。该电荷泵装置的电路结构如图4所示。另外，与上述的图1相同的构成要素使用同一符号，省略其详细地说明。
P型衬底1及N型外延层2由P型隔离区域3划分成多个岛区域。在邻接的岛区域上分别形成有作为背栅极区域的P型扩散层5。而且，在P型扩散层5和与P型扩散层5邻接的N型外延层2上分别形成有电荷输送用MOS晶体管M2、M3。包围P型扩散层5而形成的漏极区域的结构与使用图1及图2所述的结构相同。
在电荷输送用MOS晶体管M2、M3中，如上所述，成为漏极区域的N型扩散层8包围成为背栅极区域的P型扩散层5而形成。P型扩散层5和N型扩散层8的一部分区域重叠。而且，重叠的区域成为低浓度的N型扩散区域。根据该结构，可谋求漏极区域的电场缓和，且可缩短漏极-源极间的分离距离，降低ON电阻值。其结果是，可使电荷泵装置的电荷输送用MOS晶体管M1～M5的ON电阻降低，且可实现大电流装置的电荷泵装置。
另外，在本实施例中，对四级的迪克森电荷泵装置适用的例子进行了说明，但显然其级数不限于四级。
另外，对使用N沟道型MOS晶体管作为电荷输送用MOS晶体管的情况进行了说明，但不限于该情况。例如也可以为使用P沟道型MOS晶体管的情况。在负升压的电荷泵装置中，电荷输送用MOS晶体管中的衬底与源极区域的连接关系相反。另外，时钟的定时也相反。
另外，电荷输送用MOS晶体管M1～M5为将栅极电极和漏极区域共同连接的结构，但不限于该情况。例如，在电荷输送用MOS晶体管M1～M5进行ON动作时，也可以适用于采用在栅极-源极间施加高的电压的电路结构的电荷泵装置。另外，在不脱离本发明主旨的范围内，可进行各种变更。

Claims (4)

1、一种半导体装置，其特征在于，具有:一种导电类型的半导体衬底；层积于所述半导体衬底上的反向导电类型的外延层；形成于所述外延层上面的栅极氧化膜及栅极电极；形成于所述半导体衬底和所述外延层的反向导电类型的埋入扩散层；形成于所述外延层、并且在底部与所述埋入扩散层重叠的一种导电类型的背栅极扩散层；形成于所述外延层且一部分与所述背栅极扩散层重叠，并且重叠了的区域成为反向导电类型的扩散区域的反向导电类型的漏极扩散层；形成于所述背栅极扩散层的反向导电类型的源极扩散层；与所述漏极扩散层连接的漏极电极；与所述源极扩散层连接的源极电极；所述漏极扩散层的重叠区域配置在所述栅极电极的端部下方的区域。
2、如权利要求1所述的半导体装置，其特征在于，所述漏极扩散层包围所述背栅扩散层而形成一环状。
3、如权利要求2所述的半导体装置，其特征在于，在所述漏极扩散层一环状地形成有漏极接触扩散层。
4、如权利要求1或2所述的半导体装置，其特征在于，具有形成于所述背栅极扩散层、且位于所述源极扩散层附近的一种导电类型的背栅极接触扩散层，所述源极电极与所述源极扩散层及所述背栅极接触扩散层连接。
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