CN100421208C - Method and apparatus for manufacturing thin film transistor array - Google Patents
Method and apparatus for manufacturing thin film transistor array Download PDFInfo
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- CN100421208C CN100421208C CNB2004100078318A CN200410007831A CN100421208C CN 100421208 C CN100421208 C CN 100421208C CN B2004100078318 A CNB2004100078318 A CN B2004100078318A CN 200410007831 A CN200410007831 A CN 200410007831A CN 100421208 C CN100421208 C CN 100421208C
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Abstract
The present invention relates to a method for manufacturing a film transistor array, which is suitable for a step for forming a conductor layer in the producing process of thin film transistor array, and the effect of static electricity damage is eliminated. The method adopts a two-stage type photomask producing process. Firstly, a first stage photomask producing process is utilized, and a conductor layer formed on a base plate is patterned; a first pattern is formed; the first pattern comprises a plurality of independent circuits and connection positions for connecting each independent circuit; the same layer of the conductor layer can be connected to equal potential, and a point discharge mechanism can be manufactured on the edge of the base plate; subsequently, before a next conductor layer is constructed, the second stage photomask producing process is utilized, and the connection positions of the first pattern are all removed; a second pattern is formed, and only the independent circuits are reserved in the second pattern.
Description
Technical field
The invention relates to a kind of thin film transistor (TFT) array (thin film transistor array, abbreviation TFT array) manufacture method, and particularly about a kind of manufacture method that can destatic the thin film transistor (TFT) array of destruction (electrostaticdischarge is called for short ESD).
Background technology
LCD is owing to have conventional cathode ray tube (cathode ray tube such as low voltage operating, radiationless line scattering, in light weight and volume be little, be called for short CRT) display of the manufacturing advantage that is beyond one's reach, with other panel displays such as plasma display panel and electroluminescence (electroluminance) display, become the major subjects of display research in recent years, more be regarded as the main flow of 21st century display.
Active-matrix formula LCD directly locates to form transistor (transistor) or diode active members (active element) such as (diode) at pixel electrode (pixel electrode), and the data of controlling LCD writes.Wherein be regarded as one of main flow of LCD now again with Thin Film Transistor-LCD.Be in when pixel electrode under the state of selection (promptly opening under the state of " ON "), signal will write on this pixel; (promptly close under the state of " OFF ") when pixel electrode is under the non-selected state, storage capacitors can be kept the current potential that drives liquid crystal.Therefore, liquid crystal and driving time have presented the characteristic of static (static).
In existing thin-film transistor processing procedure, electrostatic breakdown is the problem of being paid close attention to deeply always, because electrostatic breakdown can occur in any stage of electronic component life, such as digital electronic component is subjected to the destruction of static all easily in making, transport, store and using.And how effectively to eliminate electrostatic breakdown, increase the production yield also is the purpose of industry ongoing effort.Existing technology is to utilize Xelminator to lower the effect of electrostatic breakdown, and this kind method is in the equipment that more easily has electrostatic breakdown to generate, install an ion generator (ionizer) additional, its operating principle is with pulse ac electricity (alternating current, be called for short AC) or pulse direct current (direct current, be called for short DC) mode alternately produce positive and negative ion, utilize a large amount of ions of being supplied to lower again or eliminate subject matter with static.
Yet, above-mentioned Xelminator often in use for some time, often the probe because of Xelminator is that running stores have depleted phenomenon, not only maintenance is difficult for, and must often utilize the electrostatic detection device to proofread and correct, cause to consume cost too high.And most Xelminators can be supplied excessive plus or minus ion, cause subject matter to produce the phenomenon that has the reversed polarity electric charge.In addition, be to belong to high temperature process (process temperatures＞500 ℃) because some are arranged in the manufacture process of thin-film transistor, and Xelminator is to operate in high temperature for a long time, so can't guarantee the not influence of destruction by electrostatic field in high temperature process.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of thin film transistor (TFT) array avoiding taking place electrostatic breakdown, and reduces the spent cost of known employing Xelminator.
A further object of the present invention provides a kind of manufacture method of thin-film transistor conductor layer, to avoid taking place electrostatic breakdown.
Another object of the present invention provides a kind of electrostatic protection apparatus at thin film transistor base plate, to guarantee thin-film transistor not influence of destruction by electrostatic field in high temperature process.
Another purpose of the present invention provides a kind of thin film transistor base plate of tool electrostatic protection apparatus, can avoid taking place electrostatic breakdown, and guarantees thin-film transistor not influence of destruction by electrostatic field in high temperature process.
For achieving the above object, the manufacture method of the thin film transistor (TFT) array that the present invention proposes, be included on the substrate and form one first conductor layer, patterning first conductor layer again is with several first bond sites that form several first independent circuits and connect first independent circuits.After, remove first bond sites in first conductor layer.Then, on first conductor layer, form one first insulating barrier, on first insulating barrier, form one second conductor layer again.Subsequently, form one second insulating barrier on substrate, second insulating barrier has several contact windows.Then, on second insulating barrier, form several pixel electrodes, so that pixel electrode is electrical connected by the contact window and second conductor layer.The manufacture method of described thin film transistor (TFT) array also is included in this substrate edges place and forms a point discharge mechanism.
The present invention reintroduces a kind of manufacture method of thin-film transistor conductor layer, comprise and utilize a phase I photo-marsk process, with a conductor layer patterning that is formed on the substrate, to form one first pattern, this first pattern is included in a point discharge mechanism, several independent circuits of this substrate edges place formation and several bond sites that connect independent circuits, so that conductor layer connects into equipotential.Afterwards, utilize a second stage photo-marsk process, the bond sites of first pattern is removed.
The present invention proposes in addition a kind of electrostatic protection apparatus at thin film transistor base plate, and its structure comprises that several are positioned at the discharge tip position of thin film transistor base plate edge, and the tip at wherein per two discharge tip positions is to face one another or staggered and do not link to each other.
The present invention reintroduces a kind of thin film transistor base plate of tool electrostatic protection apparatus, comprise several thin-film transistors and several discharge tip positions, be positioned at the edge of thin film transistor base plate, the tip at wherein per two discharge tip positions is to face one another or staggered and do not link to each other.
The present invention is directed to the generation reason and the failure mode of electrostatic breakdown, from the improvement of processing procedure face, make all conductor layers connect into equipotential earlier energetically, and can make point discharge mechanism in the substrate edges place.Therefore, the continous way protection of being done in the complete section processing procedure of the present invention can be strengthened the ability to bear of thin film transistor base plate to electrostatic breakdown itself down, and then eliminates the generation of electrostatic breakdown in the processing procedure, and promotes the production yield.
Description of drawings
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Fig. 1 is the manufacturing process block diagram according to the thin film transistor (TFT) array of a preferred embodiment of the present invention.
Fig. 2 is shown to be circuit layout schematic diagram according to the step 104 of the manufacturing process of Fig. 1 thin film transistor (TFT) array.
Fig. 3 (a) is the structural representation according to the thin film transistor (TFT) array of a preferred embodiment of the present invention.
One enlarged diagram of the III part of shown Fig. 3 of Fig. 3 (b) (a).
Another enlarged diagram of the III part of shown Fig. 3 of Fig. 3 (c) (a).
Embodiment
Fig. 1 is according to the thin-film transistor of a preferred embodiment of the present invention (thin film transistor, abbreviation TFT) the manufacturing process block diagram of array (array), wherein each layer conductor layer utilizes two stage photo-marsk processes to make, and the photo-marsk process in each stage for example is through steps such as photoresistance coating, soft roasting, hard roasting, exposure, photographic fixing, development, etchings, with the conductor layer patterning.
Please refer to Fig. 1, in step 100, provide a substrate, this substrate is a transparency carrier, such as glass substrate or quartz base plate etc.Then, in step 102, on substrate, form one deck n conductor layer, wherein n=1,2 ..., n, which layer conductor layer conductor layer in present embodiment is not limited to, so long as the conductor layer of electrostatic breakdown situation can take place, all can make according to the mode of present embodiment.
Subsequently, in step 104, utilize phase I photo-marsk process patterning n conductor layer, with the bond sites that forms several independent circuits and link each independent circuits.Simultaneously can make a point discharge mechanism in this,, share and reduces the electrostatic potential that brings out accumulation in the environment, make the current potential reduction of substrate by the principle of point discharge with under the main circuit that does not influence thin film transistor (TFT) array at the substrate edges place.
Afterwards,, before the construction of one deck conductor layer, carry out step 106 again under waiting until, utilize second stage photo-marsk process patterning n conductor layer, to remove the bond sites that links each independent circuits referring again to Fig. 1.Afterwards, can carry out step 108, form one deck n insulating barrier and cover the n conductor layer on substrate, the n insulating barrier in this embodiment for example is a dielectric layer.And after step 108, can resumes step 102, the following one deck conductor layer of formation on substrate again.
When present embodiment is applied to the manufacture method of thin film transistor (TFT) array, can be according to aforesaid two stage photo-marsk processes, for example carry out step 102 earlier, on substrate, form one deck first conductor layer (n=1), carry out step 104 again, patterning first conductor layer has grid and several scan wiring independent circuits such as (scan line) that links to each other with grid and first conductor layer that is connected the bond sites of aforementioned each independent circuits with formation.Afterwards, carry out step 106, remove the bond sites of first conductor layer.Then,, one first insulating barrier (n=1) can be on substrate, formed, channel layer (channellayer) can also be on first insulating barrier, formed afterwards across grid as gate insulator (gateinsulating) in step 108.
Then, but repeating step 102, on substrate, form one deck second conductor layer (n=2), then carry out step 104, patterning second conductor layer becomes it and has source/drain and several data wire independent circuits such as (data line) that links to each other with source/drain and second conductor layer that is connected the bond sites of aforementioned each independent circuits.Afterwards, carry out step 106, remove the bond sites of second conductor layer.Then, in step 108, form one second insulating barrier (n=2) as protective layer on substrate, wherein second insulating barrier also has several contact windows.Then, can on second insulating barrier, form several pixel electrodes, so that pixel electrode is electrical connected by source/drain one end of the contact window and second conductor layer.
In addition, for the difference of explanation phase I of the present invention and second stage photo-marsk process, ask for an interview Fig. 2.
Fig. 2 is shown to be circuit layout schematic diagram according to the step 104 of the manufacturing process of the thin film transistor (TFT) array of Fig. 1.Please refer to Fig. 2, promptly pass through after the phase I photo-marsk process shown in the figure, the conductor layer layout 200 of the conductor layer that is patterned, comprising several independent circuits 202 as cyclic loop, and the bond sites 204 that connects aforementioned independent circuits 202.And the conductor layer layout 200 of Yu Bentu only is one of them example of the conductor layer that is patterned in the step 104 of Fig. 1 as an illustration, and the pattern of non-limiting conductor layer layout 200.In addition, as long as the linking part in conductor layer layout 200 204 is can be with all independent circuits 202 mutual conductings, so can only lean on a bond sites conducting to get final product as the independent circuits 202 of two rows among Fig. 2.
Please continue with reference to Fig. 2, because the phase I photo-marsk process interlinks into equipotential with the pattern that conductor layer is designed to independent circuits originally, therefore can guarantee can not cause in the successive process potential difference between this conductor layer excessive, and produce electric arc (arc) discharge because of the electrostatic effect of regional area.Second stage photo-marsk process afterwards will carry out before following one deck conductor layer construction, with the bond sites 204 of connection independent circuits 202 in the removal conductor layer layout 200, and reservation independent circuits 202 wherein.
In addition, after the step 104 of Fig. 1, once proposed the making of an electrostatic protection apparatus, therefore, asked for an interview Fig. 3 for describing this electrostatic protection apparatus in detail.
Fig. 3 (a) is the structural representation according to the thin film transistor (TFT) array of a preferred embodiment of the present invention, and Fig. 3 (b) and the III enlarged diagram partly of (c) distinguishing displayed map 3 (a).Please refer to Fig. 3 (a), Fig. 3 (b) and Fig. 3 (c), electrostatic protection apparatus of the present invention is made in substrate 300 edges simultaneously when can one deck conductor layer in office carrying out patterning process, its structure comprises two discharge tip positions 304 that the tip is relative, and the tip at these two discharge tip positions 304 is to face one another (not link to each other as Fig. 3 (b) or staggered (as Fig. 3 (c)).In addition, discharge tip position 304 can link to each other with two leads 306 of isolating mutually respectively.Because this point discharge mechanism is arranged at substrate 300 edges, so can not influence thin-film transistor 302 times, share and reduce the electrostatic potential that brings out accumulation in the environment by the principle of point discharge, make the current potential reduction of substrate 300.
The present invention makes all conductor layers connect into equipotential earlier because in the thin-film transistor processing procedure, can make electrostatic protection apparatus again in the substrate edges place.The method is excessive except guaranteeing can not cause because of the electrostatic effect of regional area in the successive process in the conductor layer between each independent circuits potential difference, and outside the generation arc discharge, the electrostatic potential of accumulation that environment brings out is shared and reduced to the conductor layer of whole base plate also point discharge mechanism thus, eliminate electrostatic breakdown (electrostatic discharge is called for short ESD).Afterwards, before following one deck conductor layer construction, remove the bond sites that connects aforementioned independent circuits in the conductor layer again.And the design of following one deck conductor layer also can utilize the same manner to do the protection of electrostatic breakdown, so method of the present invention can cooperate each element and process design collocation to use, and is not limited on the method for manufacturing thin film transistor.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill personnel, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when the claim that look application defines.
Claims (9)
1. the manufacture method of a thin film transistor (TFT) array comprises:
On a substrate, form one first conductor layer;
This first conductor layer of patterning is with a plurality of first bond sites that form a plurality of first independent circuits and connect those first independent circuits;
Remove those first bond sites in this first conductor layer;
On this first conductor layer, form one first insulating barrier;
On this first insulating barrier, form one second conductor layer;
Form one second insulating barrier on this substrate, this second insulating barrier has a plurality of contact windows; And
On this second insulating barrier, form a plurality of pixel electrodes, so that those pixel electrodes are electrical connected by those contact windows and this second conductor layer;
The manufacture method of described thin film transistor (TFT) array also is included in this substrate edges place and forms a point discharge mechanism.
2. the manufacture method of thin film transistor (TFT) array as claimed in claim 1 is characterized in that, wherein this first independent circuits comprises a plurality of grids and many scan lines that are connected with those grids.
3. the manufacture method of thin film transistor (TFT) array as claimed in claim 1 is characterized in that, wherein after forming this first insulating barrier on this substrate, also is included in and forms a plurality of channel layers on this first insulating barrier, and those channel layers are across those grids.
4. the manufacture method of thin film transistor (TFT) array as claimed in claim 1, it is characterized in that, on this first insulating barrier, form after one second conductor layer, also comprise this second conductor layer of patterning, with a plurality of second bond sites that form a plurality of second independent circuits and connect those second independent circuits.
5. the manufacture method of thin film transistor (TFT) array as claimed in claim 4 is characterized in that, wherein this second independent circuits comprises multiple source/drain electrode and many data wires that are connected with those source/drains.
6. the manufacture method of thin film transistor (TFT) array as claimed in claim 1, it is characterized in that, wherein in the step of this first conductor layer of patterning, form this point discharge mechanism, this point discharge mechanism comprises two discharge tip positions, and the tip at those discharge tip positions faces one another or staggered and do not link to each other.
7. the manufacture method of thin film transistor (TFT) array as claimed in claim 4, it is characterized in that, wherein in the step of this second conductor layer of patterning, form this point discharge mechanism, this point discharge mechanism comprises two discharge tip positions, and the tip at those discharge tip positions faces one another or staggered and do not link to each other.
8. the manufacture method of a thin-film transistor conductor layer comprises:
Utilize a phase I photo-marsk process, with a conductor layer patterning that is formed on the substrate, to form one first pattern, this first pattern is included in a point discharge mechanism, a plurality of independent circuits of this substrate edges place formation and a plurality of bond sites that connect those independent circuits, so that this conductor layer connects into equipotential; And
Utilize a second stage photo-marsk process, those bond sites of this first pattern are removed.
9. the manufacture method of thin-film transistor conductor layer as claimed in claim 8 is characterized in that, this point discharge mechanism comprises two discharge tip positions, and the tip at those discharge tip positions faces one another or staggered and do not link to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100078318A CN100421208C (en) | 2004-03-04 | 2004-03-04 | Method and apparatus for manufacturing thin film transistor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100078318A CN100421208C (en) | 2004-03-04 | 2004-03-04 | Method and apparatus for manufacturing thin film transistor array |
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| Publication Number | Publication Date |
|---|---|
| CN1664984A CN1664984A (en) | 2005-09-07 |
| CN100421208C true CN100421208C (en) | 2008-09-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100078318A Expired - Fee Related CN100421208C (en) | 2004-03-04 | 2004-03-04 | Method and apparatus for manufacturing thin film transistor array |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441372B (en) * | 2007-11-23 | 2011-12-07 | 上海中航光电子有限公司 | Electrostatic discharge protection device of LCD device and manufacturing method thereof |
| CN105242463B (en) * | 2015-11-03 | 2018-10-19 | 深圳市华星光电技术有限公司 | Liquid crystal display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254187A (en) * | 1998-08-31 | 2000-05-24 | 佳能株式会社 | Semiconductor device |
| CN1256763A (en) * | 1998-02-19 | 2000-06-14 | 精工爱普生株式会社 | Active matrix substrate, electro-optic device, method of manufacturing active matrix substrate, and electronic device |
| CN1359139A (en) * | 2000-12-06 | 2002-07-17 | 株式会社半导体能源研究所 | Semiconductor device and making method |
| US20020101547A1 (en) * | 1997-10-14 | 2002-08-01 | Lee Joo-Hyung | Liquid crystal displays |
| CN1416596A (en) * | 2001-01-11 | 2003-05-07 | 皇家菲利浦电子有限公司 | Method of mfg. active matrix substrate |
| CN2600837Y (en) * | 2003-01-08 | 2004-01-21 | 广辉电子股份有限公司 | Semi-manufactured structure of thin film transistor array |
| CN1529197A (en) * | 2003-10-17 | 2004-09-15 | 友达光电股份有限公司 | Static discharging protection structure |
-
2004
- 2004-03-04 CN CNB2004100078318A patent/CN100421208C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020101547A1 (en) * | 1997-10-14 | 2002-08-01 | Lee Joo-Hyung | Liquid crystal displays |
| CN1256763A (en) * | 1998-02-19 | 2000-06-14 | 精工爱普生株式会社 | Active matrix substrate, electro-optic device, method of manufacturing active matrix substrate, and electronic device |
| CN1254187A (en) * | 1998-08-31 | 2000-05-24 | 佳能株式会社 | Semiconductor device |
| CN1359139A (en) * | 2000-12-06 | 2002-07-17 | 株式会社半导体能源研究所 | Semiconductor device and making method |
| CN1416596A (en) * | 2001-01-11 | 2003-05-07 | 皇家菲利浦电子有限公司 | Method of mfg. active matrix substrate |
| CN2600837Y (en) * | 2003-01-08 | 2004-01-21 | 广辉电子股份有限公司 | Semi-manufactured structure of thin film transistor array |
| CN1529197A (en) * | 2003-10-17 | 2004-09-15 | 友达光电股份有限公司 | Static discharging protection structure |
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| CN1664984A (en) | 2005-09-07 |
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Granted publication date: 20080924 Termination date: 20180304 |