CN100424877C - Semiconductor memory device and method of arranging signal and power lines thereof - Google Patents
Semiconductor memory device and method of arranging signal and power lines thereof Download PDFInfo
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- CN100424877C CN100424877C CNB2005100817846A CN200510081784A CN100424877C CN 100424877 C CN100424877 C CN 100424877C CN B2005100817846 A CNB2005100817846 A CN B2005100817846A CN 200510081784 A CN200510081784 A CN 200510081784A CN 100424877 C CN100424877 C CN 100424877C
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- G—PHYSICS
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- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
Description
Technical field
The present invention relates to dynamic random access memory (DRAM) semiconductor device, relate in particular to the method that the metal level that is used for being positioned at the composition on this device is laid power supply and signal traces.
Background technology
The DRAM device comprises storage array, be used to visit the circuit of storage array and control DRAM operation and with the peripheral circuit of external device communication.Typical storage array is formed by the repeat pattern of inferior memory cell array, and described time memory cell array is arranged with the circuit distribution that is used for the access storage array of part.The access circuit of remainder is usually located in the row decoder and column decoder that is in the storage array edge.
Fig. 1 illustrates typical memory and arranges 100, and it comprises storage array 10, column decoder 20 and row decoder 30.Storage array 10 is arranged as and is similar to halma board, and inferior memory cell array (SMCA) is cut apart by time word line driver (SWD) vertical segmentation and sensor amplifier (SA) level that is stored the unit.Each time memory cell array comprises a plurality of memory cell (MC), each memory cell by the access transistor that is driven by time word line (SWL) and the capacitor that is used to store data form.This SA is connected zone (CJ) vertical segmentation, and described join domain comprises the control signal generation circuit of SA.
To describe the further aspect of Fig. 1 in conjunction with Fig. 2, Fig. 2 illustrates the further details of the part of array 10.In SMCA1 and SMCA2, show two memory cell MC1 and MC2 respectively.Each memory cell comprises the capacitor C between the source electrode that is connected unit plate voltage (Vp) and access transistor N.Usually, Vp is half of power supply service voltage.The grid of each access transistor (N) is by corresponding word line (SWL) control, and wherein SWL1 controls the MC1 access transistor and SWL2 control MC2 access transistor.
The drain electrode of each access transistor is connected to corresponding bit line (BL), for example is used for the BL1 and the BL2 that is used for MC2 of MC1.Each bit lines also is connected to other memory cell (not shown) in corresponding SMCA, and the access transistor (not shown) is connected to other SWL.Sensor amplifier region S A1 is between SMCA1 and SMCA2.With reference to SMCA1, BL1 and BL1B are connected to the pre-charge circuit PRE1 among the SA1, and are connected to a pair of sensing bit line SBL and SBLB by position isolating door ISO1.As for SMCA2, BL2 and BL2B are connected to the pre-charge circuit PRE2 among the SA1, and are connected to a pair of sensing bit line SBL and SBLB by position isolating door ISO2.Bit line sensor amplifier BLSA and data I/O door IOG also are connected to sensing bit line SBL and SBLB.
For example, in ensuing sequence, the bit line sensor amplifier amplifies the BL1 of MC1 memory cell and the voltage difference between the BL1B, and wherein memory cell is represented one of two kinds of logic states (multistate memory cell also exist and typically use more complicated sensor amplifier circuit).Isolating door ISO1 is connected to BL1 SBL and BL1B is connected to SBLB.Intermediate voltage between the voltage that pre-charge circuit PRE1 is charged to BL1 and BL1B discharging capacitor C (presentation logic 0 in identical embodiment) and the voltage of charging capacitor C (presentation logic 1 in identical embodiment).Activate SWL1 so that the MC1 memory cell capacitor is coupled to BL1.When described cell capaciator was discharged, electric charge was shared and is made the voltage on the BL1 reduce with respect to BL1B.When cell capaciator was recharged, electric charge was shared and is made the voltage on the BL1 increase with respect to BL1B.Electric charge share finish after, enable isolating door ISO1 and make the small electric pressure reduction between bit line BL1/BL1B be sent to sensing bit line SBL1/SBL1B.In either case, sensor amplifier BLSA is being activated during the predetermined period so that sensing and amplify small voltage difference between the bit line BL1/BL1B.
When output/out gate IOG was activated, IOG was coupled to SBL and SBLB on a pair of local input LIO and the LIOB, the IO door of other in regional (not shown) of other SA that LIO and LIOB equally also are connected in the SA1 above and below.At this, this I/O door LOG is activated in response to column selection line CSL (not shown).When LIO and LIOB were state of activation, local I/O door LGIOG was used for selectively LIO and LIOB being coupled to a pair of overall input/output line GIO and GIOB.Thus, the state of the memory cell of institute's sensing is coupled to peripheral input/output circuitry.
From Fig. 1 and 2, be understandable that: a large amount of leads will be routed at the top of storage array 10.The NWE line vertically connects up across described array above inferior memory cell array, and PX, LIO and LIOB line vertically connect up across described array above join domain and sensor amplifier zone.CSL, GIO and GIOB line connect up across described array on sub-memory cell array upper horizontal ground.Not shown power line, described power line also must connect up above described array so that provide power for the circuit in SA, CJ and the SWD zone.
Fig. 3 illustrates the zone of storage array 10, wherein omits to be positioned at the details of following circuit and only to illustrate and be positioned at top metal trace.On the first metal layer, LIO, PX and NWE trace are spaced apart by the first power line P1, and described first power line provides power with the different voltage levels that array circuit needs.Among the first power line P1 some can comprise earth potential line (VSS) and power line (VCC).Other line of the first power line P1 can comprise reference voltage line (Vref), negative power line (VBB), booster voltage line (VPP) etc.On second metal level, CSL and GIO trace are spaced apart by second source line P2, and described second source line provides voltage with different voltage levels.Among the second source line P2 some can comprise earth potential line (VSS) and power line (VCC).Other line of second source line P2 can comprise reference voltage line (Vref), negative power line (VBB), booster voltage line (VPP) etc.Locate above the P2 trace is positioned at the P1 trace of voltage level, described two traces are connected to each other to produce grid.The power supply that the P2 trace is located on the storage array outside of DRAM device is connected.
Fig. 4 shows the simplified structure diagram of the row decoder 30 of Fig. 1.Row decoder 30 comprises row-address decoder zone 30-1 and row address pre decoding zone 30-2.In the 30-1 of row decoder zone, each first decoder region R D1 that is illustrated produces word line selection signal PX, and each second decoder region R D2 that is illustrated produces the corresponding main word line signal of the row address DRA NEW with row address RA and pre decoding, and main word line signal NEW is produced in turn by row address predecoder 30-2.
Fig. 5 shows the part of row decoder 30, has wherein omitted the details that is positioned at following circuit and superposed metal trace is shown.Above the first decoder region R D1 on the first metal layer, holding wire S1 (for example PX line) is set at the side of the first power line PVINT1 and PVSS1.Above the second decoder region R D2 on the first metal layer, holding wire S1 (for example NWE line) is set at first additional power line PVINT1 and the side of PVSS1.
Second metal level comprises holding wire S2 (for example RA and DRA line) and second source line PVINT2 and PVSS2.PVINT2 is connected in PVINT1, two line overlaps there, and PVSS2 is connected in PVSS1, there two line overlaps.PVINT2 is connected with the power supply of PVSS2 trace with the storage array outside that is positioned at the DRAM device.In this case, under the situation that does not increase integrated circuit area, power line can't be designed to wide line.
Summary of the invention
Narrow down to the quantity of the unit in littler cell size and/or the increase storage array along with the DRAM device, can arrange more holding wire on the storage array of every unit area of the same area and the row decoder actually, and a spot of holding wire before can only be arranged in described unit area.Therefore, the width of power line dwindles pro rata so that hold compacter array.Yet because the power line width that reduces causes the bigger impedance of electric current, bigger voltage drop and power consumption, and because the electric current demand fluctuation has reduced the stability of power supply, therefore, the width that dwindles power line does not conform to demand.Different signals and power line also can be owing to device narrow down to nearer that smaller szie compresses, and this causes occurring undesirable interference between contiguous line.
Embodiment described here has adopted the DRAM design of three metal levels, and this compares the wiring that has improved signal and power line significantly with the design of double-metal layer.Although other people have advised utilizing the three-layer metal layer to arrange the various cases of holding wire above storage array, but it should be understood that design of the present invention especially in order to solve the problem of power supply, thereby produced one group of metal level that reduces the novelty of cell size well and lay scheme.
Description of drawings
Fig. 1 shows the storage array that is used for the DRAM memory device and the row/column decoder of prior art and lays scheme;
Fig. 2 shows the part zoomed-in view of Fig. 1 storage array, and it shows the details of adjunct circuit and holding wire;
Fig. 3 also shows the part zoomed-in view of Fig. 1 storage array, this time more pays close attention to be positioned at the signal of two metal levels on the storage array and the wires design of power trace;
Fig. 4 shows the part zoomed-in view of Fig. 1 row decoder, and it shows the details of adjunct circuit and holding wire;
Fig. 5 also shows the part zoomed-in view of Fig. 1 row decoder, this time more pays close attention to and covers the signal of two metal levels on the row decoder and the wires design of power trace;
Fig. 6-10 shows and is used to be presented at the three-layer metal layer signal of storage array top and several embodiment of power line wiring;
Figure 11-14 shows and is used to be presented at the three-layer metal layer signal of row decoder top and several embodiment of power line wiring;
Figure 15 and 16 shows several embodiment of the wiring of the three-layer metal layer signal that is used to be presented at the column decoder top and power line.
Embodiment
On storage array, row decoder and/or column decoder, used the three-layer metal layer in the following examples.Usually can adopt wide power line at these embodiment, this will improve the distribution and the stability of power.By the description of following accompanying drawing, the various advantages of described embodiment will become obvious.
Fig. 6 shows and utilizes three-layer metal signal and power line to be laid in first embodiment of storage array top.Similar to prior art, the first metal layer comprises NWE, PX, LIO holding wire and power line P1.Second metal level comprises CSL and GIO holding wire, and does not have power line.The 3rd metal level comprises the power line P3 perpendicular to the P1 power line that forms with the first metal layer.It is wideer than the P2 power line that forms with second metal level in the prior art that the P3 power line can be made, and this is because CSL and GIO line can not competed metal 3 zones that are positioned at the storage array top.Although for the sake of clarity there is not described feature shown in Figure 6, the part of P3 line even can be located immediately at CSL and GIO line top.In the middle of being present in the gap being connected of power line P1, the P3 line is positioned at the top of the P1 line with identical voltage there, and can use through hole contact (the direct connection between the 3rd metal and first metal) or the weld pad (not shown) of intermediate layer P2 to be connected to metal 1.Therefore, can and improve power division with the resistance that reduces and lay the P3 line.Therefore, can also improve interval between CSL and the GIO line, reduce to disturb and also improve signal velocity owing to lack the P2 trace.
Fig. 7 shows and utilizes three-layer metal layer signal and power line to be laid in second embodiment of storage array top.In this embodiment, the P1 line is not present on the metal 1, and the P2 line that is parallel to CSL and GIO on the metal 2 distributes power to the storage array circuit.The P3 line is laid on the metal 3, and described P3 line is connected perpendicular to the P2 line and with the P2 line, and the P3 line and the P2 line that have same voltage level there intersect.It is thinner relatively that the P2 line can keep, and the P3 line can be made relative broad so that effectively electric current is transported to the near zone that needs it.
Fig. 8 shows and utilizes three-layer metal layer signal and power line to be laid in the 3rd embodiment of storage array top.In this embodiment, thin P1 power line and thin P2 power line intersect.P1 and P2 line with same voltage level are connected to each other in their intersections.The P3 power line of broad is parallel to the P2 line to be laid, and generally with the P2 line overlap with same voltage level.Because P3 and P2 line are overlapping along their length directions, so the connection between these two lines can be made into long raceway groove, or the through hole that reduces more continually.The structure of P3/P2 has the lower impedance of per unit length, and accounts for less space at the metal level of sharing with CSL and GIO.
Fig. 9 shows and utilizes three-layer metal layer signal and power line to be laid in the 4th embodiment of storage array top.In this embodiment, metal 1 comprises and is parallel to the thin P1 power line that the NEW line is arranged.Metal 2 comprises perpendicular to the P1 power line and is parallel to CSL and the thin P2 power line of GIO line layout.At the place, crosspoint of P2 power line and the P1 power line with same voltage level, described two power lines link to each other.Metal 3 comprises the wide relatively P3 power line that is parallel to the P1 power line, and preferably P3 power line cloth is set as and can makes the P3 power line and have a following P1 line overlap of being positioned at of same voltage level.At the place, crosspoint of P3 power line and the P2 power line with same voltage level, described two power lines link to each other.
Figure 10 shows and uses three-layer metal layer signal and power line to be laid in the 5th embodiment of storage array top.This embodiment is similar (Fig. 8) to the 3rd embodiment, but the GIO line is laid on the metal 3 rather than on the metal 2.This is a kind of attractive selection so, because P2 and P3 line can serve as the single wire with the impedance that reduces together, allows the P3 width littler and be holding wire leaving space on the metal 3.Therefore, the bigger reduction coupling noise thereby the line-spacing between the CSL can become.
Preferably but not necessarily be, in conjunction with one of aforesaid embodiment, can also be provided for the different embodiment of arranging signal and power line above row decoder.Figure 11 shows the embodiment of first row decoder.On the first metal layer, provide thin relatively power line PVINT1, PVSS1 so that the row decoder circuit below being positioned at provides power.For example, PVINT1 and PVSS1 power line are set as from the top towards the exterior lateral area of row decoder region R D1 and extend to the bottom, leave be arranged in the RD1 top interior section so that at the first metal laying signal wire S1.The holding wire S2 of other row decoder is formed on second metal, extends perpendicular to PVINT1, PVSS1 and S1 line.On the 3rd metal, relatively the power line PVINT3 of broad and PVSS3 are parallel to the S2 line and extend, and each bar PVINT3 and PVSS3 and one or more holding wire S2 are overlapping.PVINT3 and PVINT1 overlapping and not with the S2 overlapping, between these two power lines, form and connect.Similarly, PVSS3 and PVSS1 overlapping and not with the S2 overlapping, between these two power lines, form and connect.Described connection can comprise the partially filled through hole that metal 2 is arranged, but does not have continuous metal 2 power lines to exist in this embodiment.Described connection can directly constitute (passing through the contact) between metal 3 and metal 1.Advantageously, the described setting allows on the metal 2 additional space launching or to increase the number of line S2, and also provides power division by metal 3 power lines, and described metal 3 power lines have the cross section that many bigger than metal 2 power lines of prior art.
Figure 12 shows the embodiment with similar second row decoder of Figure 11, but adopted be parallel on metal 2 that holding wire S2 extends and in the outside of holding wire S2 additional supply line PVINT2 and PVSS2.At the overlapping of PVINT2 and PVINT1, between these two power lines, form connection, and between PVSS2 and PVSS1, form similar connection.PVINT3 and PVINT2 overlapping (and also can be overlapping with one or more holding wire S2) be in the overlapping formation PNINT3 of described two lines and the connection between the PVINT2.Described connection can be the raceway groove that prolongs or a series of more through hole of reduction that separates along PVINT3 and PVINT2 length direction.Existence similarly is provided with and is connected between PVSS3 and PVSS2.
Figure 13 shows the embodiment with the similar the third line decoder of Figure 11.Yet, above row decoder region R D1, PVINT1 and PVSS1 being set in central authorities, holding wire S1 is positioned at the outside of PVINT1 and PVSS1.Here, on second metal level, there are not PVINT2 and PVSS2.
Figure 14 shows the embodiment with the similar fourth line decoder of Figure 12.Yet, above row decoder region R D1, PVINT1 and PVSS1 being set in central authorities, holding wire S1 is positioned at the outside of PVINT1 and PVSS1.Here, have PVINT2 and PVSS2 having on second metal level of holding wire S2.
Preferably but not necessarily, in conjunction with an aforesaid embodiment, can also be provided for the different embodiment of arranging signal and power line on column decoder.Figure 15 shows the embodiment of first column decoder, and described execution mode for example uses the embodiment of the Figure 10 with the GIO line that is arranged on the metal 3.Column decoder 20 ' uses holding wire S1, power line PVINT1 and the PVSS1 that is arranged on the metal 1, and is arranged at holding wire S2, power line PVINT2 and PVSS2 on the metal 2 of metal 1 top.Yet, on metal 3, on described column decoder, extend towards peripheral I/O circuit (not shown) at the 3 GIO lines of the metal above the storage array (coming to provide power) for storage array with unshowned optional metal 3 power lines.
Figure 16 shows the embodiment with the similar secondary series encoder of Figure 15, and wherein the GIO line is connecting up above the row encoder on the metal 3.But, only striding across this row encoder, every GIO line all is connected to the GIO line by through hole, and described GIO line extends on storage array on metal 2 continuously, for example paints as Fig. 6-9.
One of ordinary skill in the art will recognize that the wiring alternative that to imagine in more other overall frameworks that fall into described embodiment.Do not discuss absolute live width and space as yet, because these all are the function of device and arts demand usually.So little modification and implementation detail also contains in an embodiment of the present invention, and is intended to fall in the scope of claim.
The above embodiments are exemplary.Although specification is mentioned the embodiment of " ", " ", " another " or " some " in a plurality of positions, this does not mean that each such quoting all is meant same embodiment, and perhaps described feature only can be applied to single embodiment.
The application requires in the priority of the korean patent application P2004-74730 of the korean patent application P2004-40542 of submission on June 3rd, 2004 and submission on September 17th, 2004, and its disclosed full content is incorporated in this for your guidance.
Claims (47)
1. a semiconductor dynamic random access memory device comprises:
Memory cell array, comprise the row/row pattern of the cell block of repetition, each cell block comprise time memory cell array with described relevant sensor amplifier part and the inferior word line driver part of memory cell array;
First, second and the 3rd patterned metal layer are arranged at described memory cell array top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many parallel local input, every input/output line is coupled to a plurality of sensor amplifier parts that are arranged as delegation in the cell block,
Many first power lines for memory cell array provides power, are parallel to described local input and extend, and
Many main word lines, on be parallel to described local input and extend, every main word line is connected to a plurality of word line driver parts that are arranged as delegation in the cell block;
The wherein said second patterned metal layer trace comprises many parallel column selection lines, and every column selection line links to each other with the I/O door in the cell block;
Wherein said the 3rd patterned metal layer trace comprises many articles the 3rd power lines, for memory cell array provides power; And
Wherein the described trace in one deck at least of the described second and the 3rd patterned metal layer also comprises many overall input/output lines, be parallel to described column selection line and extend, every overall input/output line is connected on a plurality of cell blocks and optionally many local input is multiplexed on that overall input/output line.
2. semiconductor dynamic random access memory device according to claim 1 is parallel to described column selection line and extends on wherein said the 3rd power line.
3. semiconductor dynamic random access memory device according to claim 2, the wherein said second patterned metal layer trace comprise that also many second source lines provide power for memory cell array, are parallel to described column selection line on the described second source line and extend.
4. semiconductor dynamic random access memory device according to claim 3 wherein is positioned on every the 3rd power line on the corresponding second source line and coupled.
5. semiconductor dynamic random access memory device according to claim 4 wherein has than the bigger width of width that is positioned at following second source line on every the 3rd power line.
6. semiconductor dynamic random access memory device according to claim 4, wherein all overall input/output lines are present on the 3rd patterned metal layer.
7. semiconductor dynamic random access memory device according to claim 1 extends perpendicular to described column selection line on wherein said the 3rd power line.
8. semiconductor dynamic random access memory device according to claim 7, the metal level trace of wherein said second composition comprises that also a plurality of second source lines provide power for memory cell array, is parallel to described column selection line on the described second source line and extends.
9. semiconductor dynamic random access memory device according to claim 8, at least one of wherein said the 3rd power line is connected with the intersection point place of second source line below being positioned at described the 3rd power line with at least one of second source line.
10. semiconductor dynamic random access memory device according to claim 7 wherein is positioned on corresponding first power line also coupled at least one described the 3rd power line.
11. semiconductor dynamic random access memory device according to claim 10 has than the bigger width of width that is positioned at the first following power line on wherein said at least one 3rd power lines.
12. semiconductor dynamic random access memory device according to claim 1, also comprise column decoder, be positioned at the periphery of described memory cell array, be connected at least some described column selection lines, wherein at least some described overall input/output lines are across described column decoder and be laid on the 3rd patterned metal layer trace across the column decoder place at them at least.
13. semiconductor dynamic random access memory device according to claim 12, wherein said at least some described overall input/output lines are laid on the metal level trace of the 3rd composition at least at them across described storage array place.
14. semiconductor dynamic random access memory device according to claim 12, wherein said at least some described overall input/output lines are laid on the metal level trace of second composition across described storage array place at them at least.
15. semiconductor dynamic random access memory device according to claim 1, wherein all overall input/output lines are present on described second patterned metal layer.
16. semiconductor dynamic random access memory device according to claim 15, the metal level trace of wherein said second composition comprises that also many second source lines provide power for memory cell array, is parallel to described column selection line on described a plurality of second source lines and extends.
17. semiconductor dynamic random access memory device according to claim 16 extends perpendicular to described column selection line on wherein said many articles the 3rd power lines.
18. semiconductor dynamic random access memory device according to claim 17, wherein at least one described the 3rd power line on be positioned at one first corresponding power line top and coupled.
19. semiconductor dynamic random access memory device according to claim 18, wherein the described connection between the 3rd power line above one first power line of correspondence is present in the through hole at least one, and described through hole allows directly one of corresponding first power line of contact of at least one 3rd power lines.
20. a semiconductor dynamic random access storage dynamic random access memory device comprises:
Memory cell array, comprise the row/row pattern of the cell block of repetition, each cell block comprise time memory cell array with described relevant sensor amplifier part and the inferior word line driver part of memory cell array;
First, second and the 3rd patterned metal layer are arranged at described memory cell array top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many parallel local input, every input/output line is coupled to a plurality of sensor amplifier parts that are arranged as delegation in the cell block, and
Many main word lines, on be parallel to described local input and extend, every main word line is connected to a plurality of word line driver parts that are arranged as delegation in the cell block;
The wherein said second patterned metal layer trace comprises:
Many parallel column selection lines, every column selection line links to each other with the I/O door in the cell block;
Many second source lines, for memory cell array provides power, described many second source line parallels extend in described column selection line; With
Many overall input/output lines are parallel to described column selection line and extend, and every overall input/output line is connected on a plurality of cell blocks and optionally many local input is multiplexed on that overall input/output line; And
Wherein said the 3rd patterned metal layer trace comprises many articles the 3rd power lines, for memory cell array provides power.
21. being parallel to described column selection line, semiconductor dynamic random access memory device according to claim 20, wherein said the 3rd power line extend.
22. semiconductor dynamic random access memory device according to claim 21 wherein is positioned on the corresponding second source line on every the 3rd power line, and coupled.
23. semiconductor dynamic random access memory device according to claim 22 wherein has than the bigger width of width that is positioned at following second source line on every the 3rd power line.
24. semiconductor dynamic random access memory device according to claim 20, wherein said first patterned metal layer also comprises many first power lines, for memory cell array provides power.
25. semiconductor dynamic random access memory device according to claim 20 extends perpendicular to described column selection line on wherein said the 3rd power line.
26. semiconductor dynamic random access memory device according to claim 25, wherein at least one described the 3rd power line on be positioned on one the first corresponding power line, and coupled.
27. a semiconductor dynamic random access storage dynamic random access memory device comprises:
Memory cell array, comprise the row/row pattern of the cell block of repetition, each cell block comprise time memory cell array with described relevant sensor amplifier part and the inferior word line driver part of memory cell array;
First, second and the 3rd patterned metal layer are arranged at described memory cell array top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many parallel local input, every input/output line is coupled to a plurality of sensor amplifier parts that are arranged as delegation in the cell block,
Many first power lines for memory cell array provides power, are parallel to described local input and extend, and
Many main word lines, on be parallel to described local input and extend, every main word line is connected to a plurality of word line driver parts that are arranged as delegation in the cell block;
The wherein said second patterned metal layer trace comprises:
Many parallel column selection lines, every column selection line links to each other with the I/O door in the cell block;
Many second source lines, for memory cell array provides power, described many second source line parallels extend in described column selection line; With
Many overall input/output lines are parallel to described column selection line and extend, and every overall input/output line is connected on a plurality of cell blocks and optionally many local input is multiplexed on that overall input/output line; And
The metal level trace of wherein said the 3rd composition comprises a plurality of the 3rd power lines, for memory cell array provides power, every the 3rd power line is positioned at a corresponding second source line top respectively, and has the bigger track width of track width that is positioned at following second source line than described.
28. a semiconductor dynamic random access storage dynamic random access memory device comprises:
Memory cell array, comprise the row/row pattern of the cell block of repetition, each cell block comprise time memory cell array with described relevant sensor amplifier part and the inferior word line driver part of memory cell array;
First, second and the 3rd patterned metal layer are arranged at described memory cell array top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many parallel local input, every input/output line is coupled to a plurality of sensor amplifier parts that are arranged as delegation in the cell block,
Many first power lines for memory cell array provides power, are parallel to described local input and extend, and
Many main word lines, on be parallel to described local input and extend, every main word line is connected to a plurality of word line driver parts that are arranged as delegation in the cell block;
The wherein said second patterned metal layer trace comprises:
Many second source lines, for memory cell array provides power, described many second source line parallels extend in described column selection line, and
The metal level trace of wherein said the 3rd composition comprises:
Many parallel column selection lines, every column selection line is connected to a plurality of sensor amplifier parts that are arranged as row in the cell block;
Many overall input/output lines are parallel to described column selection line and extend, and every overall input/output line is connected to a plurality of cell blocks optionally many local input multichannels are exported on that overall input/output line.
29. a semiconductor dynamic random access memory device comprises:
Row decoder produces the signal on many main word lines, and comprises a plurality of control circuits;
First, second and the 3rd patterned metal layer are arranged at described row decoder top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many first holding wires, every first holding wire connect the one of predetermined of described control circuit and
Many first power lines provide power, are parallel to described first holding wire and extend;
The wherein said second patterned metal layer trace comprises many parallel secondary signal lines, arranges perpendicular to described first holding wire;
Wherein said the 3rd patterned metal layer trace comprises many articles the 3rd power lines, and power is provided, and described the 3rd power line is parallel to described secondary signal line arrangement and is positioned at least some described secondary signal lines tops.
30. semiconductor dynamic random access memory device according to claim 29 comprises also and described row decoder adjacent memory unit array that wherein at least some described first power lines provide power for described memory cell array.
31. semiconductor dynamic random access memory device according to claim 29 comprises also and described row decoder adjacent memory unit array that wherein at least some described the 3rd power lines provide power for described memory cell array.
32. semiconductor dynamic random access memory device according to claim 29, the wherein said second patterned metal layer trace also comprises the many second source lines that power is provided, described second source line parallel extends in described secondary signal line, has the width narrower than the width of described the 3rd power line on described each bar of second source line.
33. device is established in semiconductor dynamic random access storage according to claim 32, wherein at least one described the 3rd power line is positioned at least one described second source line.
34. semiconductor dynamic random access memory device according to claim 32, wherein at least one described first power line extends across 1/2nd places, center of described each control circuit.
35. semiconductor dynamic random access memory device according to claim 29, wherein at least one described first power line extends across 1/2nd places, center of described each control circuit.
36. a semiconductor dynamic random access memory device comprises:
Row decoder produces the signal on many main word lines, and comprises a plurality of control circuits;
First, second and the 3rd patterned metal layer are arranged at described row decoder top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
The wherein said first patterned metal layer trace comprises:
Many first holding wires, every first holding wire connect the one of predetermined of described control circuit and
Many first power lines provide power, are parallel to described first holding wire and extend;
The wherein said second patterned metal layer trace comprises:
Many parallel secondary signal lines, described secondary signal line extends perpendicular to described first holding wire; And
Many second source lines provide power, and described second source line parallel extends in described secondary signal line; And
Wherein said the 3rd patterned metal layer trace comprises a plurality of the 3rd power lines that power is provided, and described the 3rd power line is parallel to described secondary signal line and extends, and is positioned at the top of at least some described secondary signal lines and second source line.
37. semiconductor dynamic random access memory device according to claim 36, wherein, above described each decoder element, one in described first power line provides internal work voltage, and another of described first power line provides ground voltage.
38. according to the described semiconductor dynamic random access memory device of claim 37, wherein on described each decoder element, described described first power line and described first power line setting adjacent one another are that ground voltage is provided that internal work voltage is provided, the outside that at least one described first holding wire is positioned at described decoder element top and first power line of described internal work voltage is provided, and another described first holding wire is positioned at the described decoder element top and the outside that described first power line of ground voltage is provided at least.
39. according to the described semiconductor dynamic random access memory device of claim 37, wherein on described each decoder element, article at least two, described first holding wire setting adjacent one another are, provide described first power line of described internal work voltage to be positioned at the outside of those holding wires, and provide described first power line of described ground voltage to be positioned at the outside of those holding wires at opposite side in a side.
40. a semiconductor dynamic random access memory device comprises:
Memory cell array;
Column decoder is positioned at the periphery of described memory cell array;
First, second and the 3rd patterned metal layer are arranged at described column decoder top, and each patterned metal layer comprises many traces; With
Insulating barrier is arranged on around the described patterned metal layer so that insulate described trace, the hole in a described insulating barrier of the electrical connection that wherein is provided for being set up to described trace;
Wherein said the 3rd patterned metal layer trace comprises the overall input/output line that a plurality of and described memory cell array links to each other.
41. according to the described semiconductor dynamic random access memory device of claim 40, the memory cell array enterprising row wiring of wherein said overall input/output line above the metal level trace of described second composition, described overall input/output line link to each other with the overall input/output line of the 3rd patterned metal layer above described column decoder respectively.
42. according to the described semiconductor dynamic random access memory device of claim 40, wherein said the 3rd patterned metal layer overall situation input/output line connects up above described memory cell array as the 3rd patterned metal layer trace.
43. a method of laying power supply and holding wire on the dynamic random access memory array, described method comprises:
The main power source trace is provided on the 3rd metal level;
Described main power source trace is connected on the secondary source trace at least one of the first metal layer and second metal level, described secondary source trace has the track width littler than main power source trace; And
Local input and word line are provided on described the first metal layer.
44., also be included on described second metal level column selection line be provided according to the described method of claim 43.
45., also be included on described second metal level overall input/output line be provided according to the described method of claim 44.
46., also be included on described the 3rd metal level overall input/output line be provided according to the described method of claim 44.
47. a method of arranging power supply and holding wire on the dynamic random access memory row decoder, described method comprises:
The main power source trace is provided on the 3rd metal level;
Described main power source trace is connected on the secondary source trace at least one of the first metal layer and second metal level, described secondary source trace has the track width littler than main power source trace; And
On described first and second metal levels, provide holding wire.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR40542/04 | 2004-06-03 | ||
| KR20040040542 | 2004-06-03 | ||
| KR74730/04 | 2004-09-17 | ||
| US11/134,855 | 2005-05-19 |
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| CN1722443A CN1722443A (en) | 2006-01-18 |
| CN100424877C true CN100424877C (en) | 2008-10-08 |
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| CNB2005100817846A Active CN100424877C (en) | 2004-06-03 | 2005-06-03 | Semiconductor memory device and method of arranging signal and power lines thereof |
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|---|---|
| KR (1) | KR100689814B1 (en) |
| CN (1) | CN100424877C (en) |
| IT (1) | ITMI20051011A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7808804B2 (en) | 2006-11-10 | 2010-10-05 | Samsung Electronics Co., Ltd. | Power line layout |
| CN105825881B (en) * | 2015-01-09 | 2019-01-01 | 旺宏电子股份有限公司 | Memory body |
| KR102646847B1 (en) * | 2016-12-07 | 2024-03-12 | 삼성전자주식회사 | Semiconductor memory devices, methods of operating semiconductor memory devices and memory systems |
| US10304497B2 (en) * | 2017-08-17 | 2019-05-28 | Micron Technology, Inc. | Power supply wiring in a semiconductor memory device |
| KR102335107B1 (en) * | 2017-10-16 | 2021-12-03 | 삼성전자 주식회사 | Nonvolatile memory device including row decoder |
| CN112558669B (en) * | 2020-12-10 | 2022-05-31 | 无锡中微亿芯有限公司 | FPGA distributed power supply network with self-test adjustable function |
| CN114530174B (en) * | 2022-01-21 | 2024-08-09 | 长江先进存储产业创新中心有限责任公司 | Memory and memory system |
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|---|---|---|---|---|
| US5930166A (en) * | 1996-12-06 | 1999-07-27 | Samsung Electronics, Co. Ltd. | Semiconductor memory device with triple metal layer |
| US5936875A (en) * | 1996-11-28 | 1999-08-10 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices including overlapping power lines and bit lines |
| US6175516B1 (en) * | 1998-07-28 | 2001-01-16 | Hitachi, Ltd. | Semiconductor device |
| US6664634B2 (en) * | 2001-03-15 | 2003-12-16 | Micron Technology, Inc. | Metal wiring pattern for memory devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100655068B1 (en) * | 2000-09-14 | 2006-12-08 | 삼성전자주식회사 | semiconductor device having advanced signal line layout |
-
2004
- 2004-09-17 KR KR1020040074730A patent/KR100689814B1/en active IP Right Grant
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2005
- 2005-05-30 IT IT001011A patent/ITMI20051011A1/en unknown
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5936875A (en) * | 1996-11-28 | 1999-08-10 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices including overlapping power lines and bit lines |
| US5930166A (en) * | 1996-12-06 | 1999-07-27 | Samsung Electronics, Co. Ltd. | Semiconductor memory device with triple metal layer |
| US6175516B1 (en) * | 1998-07-28 | 2001-01-16 | Hitachi, Ltd. | Semiconductor device |
| US6664634B2 (en) * | 2001-03-15 | 2003-12-16 | Micron Technology, Inc. | Metal wiring pattern for memory devices |
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| Publication number | Publication date |
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| CN1722443A (en) | 2006-01-18 |
| KR20050115196A (en) | 2005-12-07 |
| KR100689814B1 (en) | 2007-03-08 |
| ITMI20051011A1 (en) | 2005-12-04 |
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