CN109817153B - Gate driving unit, gate driving method, gate driving circuit and display device - Google Patents
Gate driving unit, gate driving method, gate driving circuit and display device Download PDFInfo
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- CN109817153B CN109817153B CN201910301068.6A CN201910301068A CN109817153B CN 109817153 B CN109817153 B CN 109817153B CN 201910301068 A CN201910301068 A CN 201910301068A CN 109817153 B CN109817153 B CN 109817153B
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Abstract
The invention provides a gate driving unit, a gate driving method, a gate driving circuit and a display device. The grid driving unit comprises a pull-up node reset circuit, a pull-up node pull-down circuit and a control circuit; the control circuit is used for controlling the grid source voltage of a transistor connected with a pull-up node in the pull-up node reset circuit to be within a first preset voltage range and controlling the grid source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range in an output stage. The invention can well keep the potential of the pull-up node in the output stage and ensure the driving capability of the grid driving unit.
Description
Technical Field
The present invention relates to the field of display driving technologies, and in particular, to a gate driving unit, a gate driving method, a gate driving circuit, and a display device.
Background
When the existing gate driving unit works, when a pulse signal at an input end arrives, a pull-up node is charged, then when the potential of an input signal is set to be low, the potential of the pull-up node is kept, and when the row clock signal arrives, the potential of the pull-up node is further pulled up due to bootstrap action. However, in this real process, since there are many transistors electrically connected to the pull-up node, and in the case of the conventional GOA (Gate On Array, Gate driver circuit On the Array substrate) architecture design, the Gate-source voltage Vgs of the transistor connected to the pull-up node is generally above 0V (taking the transistor as an n-type transistor as an example), the potential drop of the pull-up node caused by the leakage current of the transistor is not negligible. The level of the potential of the pull-up node directly determines whether the output transistor is sufficiently turned on, and the drop of the potential of the pull-up node directly causes the output capability of the output transistor to be reduced, so that the driving capability of the gate driving unit cannot be ensured.
Disclosure of Invention
The present invention is directed to a gate driving unit, a gate driving method, a gate driving circuit and a display device, which solve the problem in the prior art that the driving capability of the gate driving unit cannot be ensured because the potential of a pull-up node cannot be maintained at the output stage.
In order to achieve the above object, the present invention provides a gate driving unit, which includes a pull-up node reset circuit, a pull-up node pull-down circuit, and a control circuit;
the control circuit is used for controlling the grid source voltage of a transistor connected with a pull-up node in the pull-up node reset circuit to be within a first preset voltage range and controlling the grid source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range in an output stage.
In implementation, a transistor connected with a pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
the transistor connected with the pull-up node in the pull-up node reset circuit is a p-type transistor, and the first predetermined voltage range is greater than or equal to 0.
In implementation, a transistor connected to a pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
and a transistor connected with the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to 0.
In practice, the pull-up node reset circuit includes a pull-up node reset transistor;
a control electrode of the pull-up node reset transistor is connected with a reset end, a first electrode of the pull-up node reset transistor is connected with the pull-up node, and a second electrode of the pull-up node reset transistor is connected with a first voltage end;
the control circuit comprises a voltage supply circuit;
the voltage supply circuit is used for supplying a first voltage to the first voltage terminal, so that in an output stage, the grid-source voltage of the pull-up node reset transistor is within a first preset voltage range.
In practice, the pull-up node pull-down circuit includes a pull-up node pull-down transistor;
a control electrode of the pull-up node pull-down transistor is connected with a pull-down node, a first electrode of the pull-up node pull-down transistor is connected with the pull-up node, and a second electrode of the pull-up node pull-down transistor is connected with a second voltage end;
the control circuit comprises a voltage supply circuit; the voltage supply circuit is used for supplying a second voltage to the second voltage end, so that in an output stage, the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range; and/or the presence of a gas in the gas,
the control circuit comprises a voltage control circuit; the voltage control circuit is used for controlling the voltage of the pull-down node in an output stage so that the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range.
In implementation, the gate driving unit further includes a pull-down node control circuit, and the pull-down node control circuit is configured to control the pull-down node to communicate with a third voltage end under the control of an input signal input by an input end;
the control circuit comprises a voltage control circuit; the voltage control circuit is used for providing a third voltage to a third voltage end, so that in the output stage, the voltage of the pull-down node is the third voltage.
The invention also provides a gate driving method applied to the gate driving unit, and the gate driving method comprises the following steps:
in the output stage, the control circuit controls the grid-source voltage of a transistor connected with the pull-up node in the pull-up node reset circuit to be within a first preset voltage range, and controls the grid-source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range.
In implementation, a transistor connected with a pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
the transistor connected with the pull-up node in the pull-up node reset circuit is a p-type transistor, and the first predetermined voltage range is greater than or equal to 0.
In implementation, a transistor connected to a pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
and a transistor connected with the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to 0.
The invention also provides a gate driving circuit which comprises the multi-stage gate driving unit.
The invention also provides a display device which comprises the grid drive circuit.
Compared with the prior art, the gate driving unit, the gate driving method, the gate driving circuit and the display device control and reduce the leakage current of the transistor connected with the pull-up node in the pull-up node reset circuit and the leakage current of the transistor connected with the pull-up node in the pull-up node pull-down circuit in the output stage, so that the potential of the pull-up node can be well maintained in the output stage, and the driving capability of the gate driving unit is ensured.
Drawings
Fig. 1 is a structural diagram of a gate driving unit according to an embodiment of the present invention;
fig. 2A is a waveform diagram of the potential of a pull-up node PU in a conventional gate driving unit;
fig. 2B is a waveform diagram of a gate driving signal output by a conventional gate driving unit;
fig. 3 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the present invention;
FIG. 5 is a circuit diagram of a first embodiment of a gate driving unit according to the present invention;
FIG. 6A is a waveform diagram of the potential of the pull-up node PU in the first embodiment of the gate driving unit according to the present invention;
fig. 6B is a waveform diagram of the gate driving signal outputted by the first embodiment of the gate driving unit according to the present invention;
fig. 7 is a circuit diagram of a second embodiment of the gate driving unit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
As shown in fig. 1, the gate driving unit according to the embodiment of the present invention includes a pull-up node reset circuit 11, a pull-up node pull-down circuit 12, and a control circuit 13;
the control circuit 13 is configured to, in an output stage, control a gate-source voltage of a transistor connected to a pull-up node in the pull-up node reset circuit 11 to be within a first predetermined voltage range, and control a gate-source voltage of a transistor connected to a pull-up node in the pull-up node pull-down circuit 12 to be within a second predetermined voltage range, so as to, in the output stage, control the transistor connected to the pull-up node in the pull-up node reset circuit 11 to be completely turned off, and control a leakage current of the transistor connected to the pull-up node in the pull-up node reset circuit 11 to be reduced, and, in the output stage, control the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 to be completely turned off, and control a leakage current of the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 to be reduced.
In the output stage, the gate driving unit according to the embodiment of the present invention controls and reduces the leakage current of the transistor connected to the pull-up node in the pull-up node reset circuit 11, and controls and reduces the leakage current of the transistor connected to the pull-up node in the pull-up node pull-down circuit 12, so that the potential of the pull-up node can be well maintained in the output stage, and the driving capability of the gate driving unit is ensured.
In the prior art, as shown in fig. 2A, since the leakage current existing in the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 and/or the transistor connected to the pull-up node in the pull-up node reset circuit 11 is large in the output stage S2, the potential holding capability of the pull-up node PU is poor, and the power of the PU is in a state of leakage voltage drop, which directly results in that the rise time Tr of the gate driving signal output by the gate driving unit and the fall time Tf of the gate driving signal are increased, and the gate driving capability is reduced.
Fig. 2B is a waveform diagram of a gate driving signal output from the gate driving signal output terminal OUT1 in the related art.
According to a specific embodiment, the transistor connected to the pull-up node in the pull-up node reset circuit may be an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
the transistor connected to the pull-up node in the pull-up node reset circuit may be a p-type transistor, and the first predetermined voltage range is greater than or equal to 0.
According to another specific embodiment, the transistor connected to the pull-up node in the pull-up node pull-down circuit may be an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
the transistor connected to the pull-up node in the pull-up node pull-down circuit may be a p-type transistor, and the second predetermined voltage range is greater than or equal to 0.
Specifically, the pull-up node reset circuit may include a pull-up node reset transistor;
a control electrode of the pull-up node reset transistor is connected with a reset end, a first electrode of the pull-up node reset transistor is connected with the pull-up node, and a second electrode of the pull-up node reset transistor is connected with a first voltage end;
the control circuit comprises a voltage supply circuit;
the voltage supply circuit is used for supplying a first voltage to the first voltage terminal, so that in an output stage, the grid-source voltage of the pull-up node reset transistor is within a first preset voltage range.
In a specific implementation, the pull-up node reset circuit may include a pull-up node reset transistor, and the control circuit may include a voltage supply circuit configured to supply a first voltage to the second pole of the pull-up node reset terminal, so that a gate-source voltage of the pull-up node reset transistor is within a first predetermined voltage range during the output phase.
Specifically, the pull-up node pull-down circuit may include a pull-up node pull-down transistor;
a control electrode of the pull-up node pull-down transistor is connected with a pull-down node, a first electrode of the pull-up node pull-down transistor is connected with the pull-up node, and a second electrode of the pull-up node pull-down transistor is connected with a second voltage end;
the control circuit comprises a voltage supply circuit; the voltage supply circuit is used for supplying a second voltage to the second voltage end, so that in an output stage, the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range; and/or the presence of a gas in the gas,
the control circuit comprises a voltage control circuit; the voltage control circuit is used for controlling the voltage of the pull-down node in an output stage so that the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range.
In a specific implementation, the pull-up node pull-down circuit may include a pull-up node pull-down transistor, and the control circuit may include a voltage supply circuit configured to supply a second voltage to a second pole of the pull-up node pull-down transistor, so that a gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range during the output phase;
in a specific implementation, the pull-up node pull-down circuit may include a pull-up node pull-down transistor, and the control circuit may include a voltage control circuit configured to control a voltage of the pull-down node during the output phase, so that a gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range during the output phase.
Specifically, the gate driving unit according to the embodiment of the present invention may further include a pull-down node control circuit, where the pull-down node control circuit is configured to control the pull-down node to communicate with a third voltage terminal under the control of an input signal input at the input terminal;
when the control circuit comprises a voltage control circuit, the voltage control circuit is configured to provide a third voltage to a third voltage terminal, so that the voltage of the pull-down node is the third voltage in the output stage.
As shown in fig. 3, on the basis of the embodiment of the gate driving unit shown in fig. 1, the pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B; the control circuit includes a voltage supply circuit 131;
the gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of M15 is connected to the second reset terminal TGOA _ RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of the M8A is connected to the first pull-down node PD _ a, the drain of the M8A is connected to the pull-up node PU, and the source of the M8A is connected to the first low voltage terminal;
the gate of the M8B is connected to the second pull-down node PD _ B, the drain of the M8B is connected to the pull-up node PU, and the source of the M8B is connected to the first low voltage terminal;
the voltage providing circuit 131 is connected to the first low voltage terminal and is configured to provide the first low voltage VGL, so that the gate-source voltage of M2, the gate-source voltage of M15, the gate-source voltage of M8A, and the gate-source voltage of M8B are all less than or equal to 0 in the output phase, so that M2, M15, M8A, and M8B are all completely turned off in the output phase, and the leakage current of M2, the leakage current of M15, the leakage current of M8A, and the leakage current of M8B are reduced.
In the embodiment shown in fig. 3, the first voltage terminal and the second voltage terminal are both the first low voltage terminal, but not limited thereto;
in the embodiment shown in fig. 3, M2, M15, M8A and M8B are all NMOS transistors (NMOS transistors), but not limited thereto.
As shown in fig. 4, on the basis of the embodiment of the gate driving unit shown in fig. 1, the gate driving unit according to the embodiment of the present invention further includes a pull-down node control circuit 14; the pull-down nodes comprise a first pull-down node PD _ A and a second pull-down node PD _ B;
the pull-down node control circuit 14 is configured to control the first pull-down node PD _ a to be communicated with a third low-voltage end and control the second pull-down node PD _ B to be communicated with the third low-voltage end under the control of an INPUT signal INPUT by an INPUT end INPUT;
the pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B;
the gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of M15 is connected to the second reset terminal TGOA _ RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of the M8A is connected with the first pull-down node PD _ A, the drain of the M8A is connected with the pull-up node PU, and the source of the M8A is connected with the second low-voltage end;
the gate of the M8B is connected to the second pull-down node PD _ B, the drain of the M8B is connected to the pull-up node PU, and the source of the M8B is connected to the second low voltage terminal; the second low-voltage end is used for inputting a second low voltage LVGL;
the control circuit includes a voltage supply circuit 131 and a voltage control circuit 132;
the voltage supply circuit 131 is connected with the first low voltage end and is used for supplying the first low voltage VGL, so that the gate-source voltage of the M2 and the gate-source voltage of the M15 are both less than or equal to 0 in the output stage, so that the M2 and the M15 are both completely turned off in the output stage, and the leakage current of the M2 and the leakage current of the M15 are reduced;
the voltage control circuit 132 is configured to provide a third low voltage LLVGL to a third low voltage terminal, so that in the output stage, the voltage of the first pull-down node PD _ a is the third low voltage LLVGL, and the voltage of the second pull-down node PD _ B is the third low voltage LLVGL;
the third low voltage LLVGL is lower than the second low voltage LVGL, so that the gate-source voltage of M8A is less than or equal to 0 and the gate-source voltage of M8B is less than or equal to 0 in the output stage, so that both M8A and M8B are completely turned off in the output stage, and the leakage current of M8A and the leakage current of M8B are reduced.
In the embodiment shown in fig. 4, the first voltage terminal is a first low voltage terminal, the second voltage terminal is a second low voltage terminal, and the third voltage terminal is a third low voltage terminal, but not limited thereto.
In the embodiment shown in fig. 4, M2, M15, M8A and M8B are all NMOS transistors, but not limited thereto.
Specifically, the pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor;
a control electrode of the first pull-down node control transistor is connected with the input end, a first electrode of the first pull-down node control transistor is connected with the first pull-down node, and a second electrode of the first pull-down node control transistor is connected with a third voltage end;
the control electrode of the second pull-down node control transistor is connected with the input end, the first electrode of the second pull-down node control transistor is connected with the second pull-down node, and the second electrode of the second pull-down node control transistor is connected with the third voltage end.
Specifically, the gate driving unit according to the embodiment of the present invention may further include an input circuit, a first pull-down control circuit, a second pull-down control circuit, a gate driving signal output circuit, and a carry signal output circuit, wherein,
the input circuit is used for controlling the communication between the pull-up node and the input end under the control of the input end;
the first pull-down control circuit is used for controlling the communication between the first control voltage end and a first pull-down node under the control of a first control voltage input by the first control voltage end and controlling the potential of the first pull-down node under the control of the voltage of the pull-up node;
the second pull-down control circuit is used for controlling the communication between the second control voltage end and a second pull-down node under the control of a second control voltage input by a second control voltage end, and controlling the potential of the second pull-down node under the control of the voltage of the pull-up node;
the grid driving signal output circuit is used for controlling the connection between the grid driving signal output end and a clock signal end under the control of the electric potential of a pull-up node, controlling the connection between the grid driving signal output end and a second low-voltage end under the control of the electric potential of a first pull-down node, controlling the connection between the grid driving signal output end and a second low-voltage end under the control of the electric potential of a second pull-down node, and controlling the connection between the grid driving signal output end and the first low-voltage end under the control of a third reset signal input by a third reset end;
the carry signal output circuit is used for controlling the carry signal output end to be connected with the clock signal end under the control of the electric potential of the pull-up node, controlling the carry signal output end to be communicated with the first low-voltage end under the control of the electric potential of the first pull-down node, and controlling the carry signal output end to be communicated with the first low-voltage end under the control of the electric potential of the second pull-down node.
In particular implementations, the input circuit may include an input transistor;
a control electrode and a first electrode of the input transistor are both connected with the input end, and a second electrode of the input transistor is connected with the pull-up node;
the first pull-down control circuit comprises a first control transistor and a second control transistor;
a control electrode of the first control transistor is connected with the first control voltage end, a first electrode of the first control transistor is connected with the first control voltage end, and a second electrode of the first control transistor is connected with the first pull-down node;
a control electrode of the second control transistor is connected with the pull-up node, a first electrode of the second control transistor is connected with the first pull-down node, and a second electrode of the second control transistor is connected with a second low-voltage end;
the second pull-down control circuit comprises a third control transistor and a fourth control transistor;
a control electrode of the third control transistor is connected with the second control voltage terminal, a first electrode of the third control transistor is connected with the second control voltage terminal, and a second electrode of the third control transistor is connected with the second pull-down node;
a control electrode of the fourth control transistor is connected with the pull-up node, a first electrode of the fourth control transistor is connected with the second pull-down node, and a second electrode of the fourth control transistor is connected with the second low-voltage end;
the grid driving signal output circuit comprises a first output transistor, a first output pull-down transistor, a second output pull-down transistor, an output reset transistor and a storage capacitor;
a control electrode of the first output transistor is connected with the pull-up node, a first electrode of the first output transistor is connected with the clock signal end, and a second electrode of the first output transistor is connected with a grid electrode driving signal output end;
a control electrode of the first output pull-down transistor is connected with the first pull-down node, a first electrode of the first output pull-down transistor is connected with the gate drive signal output end, and a second electrode of the first output pull-down transistor is connected with the first low-voltage end;
a control electrode of the second output pull-down transistor is connected with the second pull-down node, a first electrode of the second output pull-down transistor is connected with the gate drive signal output end, and a second electrode of the second output pull-down transistor is connected with the first low-voltage end;
the control electrode of the output reset transistor is connected with the third reset end, the first electrode of the output reset transistor is connected with the grid drive signal output end, and the second electrode of the output reset transistor is connected with the first low-voltage end;
the carry signal output circuit comprises a second output transistor, a third output pull-down transistor and a fourth output pull-down transistor;
a control electrode of the second output transistor is connected with the pull-up node, a first electrode of the second output transistor is connected with the clock signal end, and a second electrode of the second output transistor is connected with a carry signal output end;
a control electrode of the third output pull-down transistor is connected with the first pull-down node, a first electrode of the third output pull-down transistor is connected with the carry signal output end, and a second electrode of the third output pull-down transistor is connected with the second low-voltage end;
and the control electrode of the fourth output pull-down transistor is connected with the second pull-down node, the first electrode of the fourth output pull-down transistor is connected with the carry signal output end, and the second electrode of the fourth output pull-down transistor is connected with the second low-voltage end.
The gate driving unit according to the present invention is illustrated by two specific embodiments.
As shown in fig. 5, the first embodiment of the gate driving unit according to the present invention includes a pull-up node reset circuit 11, a pull-up node pull-down circuit 12, a pull-down node control circuit 14, an input circuit, a first pull-down control circuit, a second pull-down control circuit, a gate driving signal output circuit, a carry signal output circuit, and a control circuit;
the pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B; the control circuit includes a voltage supply circuit (the voltage supply circuit is not shown in fig. 5);
the gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of M15 is connected to the second reset terminal TGOA _ RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of the M8A is connected to the first pull-down node PD _ a, the drain of the M8A is connected to the pull-up node PU, and the source of the M8A is connected to the first low voltage terminal;
the gate of the M8B is connected to the second pull-down node PD _ B, the drain of the M8B is connected to the pull-up node PU, and the source of the M8B is connected to the first low voltage terminal;
the pull-down node control circuit 14 includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
the gate of the first pull-down node control transistor M7A is connected to the INPUT terminal INPUT, the drain of the first pull-down node control transistor M7A is connected to the first pull-down node PD _ a, and the source of the first pull-down node control transistor M7A is connected to the second low voltage terminal; the second low-voltage end is used for inputting a second low voltage LVGL;
the gate of the second pull-down node control transistor M7B is connected to the INPUT terminal INPUT, the drain of the second pull-down node control transistor M7B is connected to the second pull-down node PD _ B, and the source of the second pull-down node control transistor M7B is connected to the second low voltage terminal;
the input circuit includes an input transistor M1;
the gate and the drain of the INPUT transistor M1 are both connected to the INPUT terminal INPUT, and the source of the INPUT transistor M1 is connected to the pull-up node PU;
the first pull-down control circuit includes a first control transistor M5A and a second control transistor M6A;
the gate of the first control transistor M5A is connected to the first control voltage terminal, the drain of the first control transistor M5A is connected to the first control voltage terminal, and the second pole of the first control transistor M5A is connected to the first pull-down node PD _ a; the first control voltage end is used for inputting a first control voltage VDD _ A;
the gate of the second control transistor M6A is connected to the pull-up node PU, the drain of the second control transistor M6A is connected to the first pull-down node PD _ a, and the source of the second control transistor M6A is connected to the second low voltage terminal;
the second pull-down control circuit includes a third control transistor M5B and a fourth control transistor M6B;
a gate of the third control transistor M5B is connected to the second control voltage terminal, a drain of the third control transistor M5B is connected to the second control voltage terminal, and a source of the third control transistor M5B is connected to the second pull-down node PD _ B; the second control voltage end is used for inputting a second control voltage VDD _ B;
the gate of the fourth control transistor M6B is connected to the pull-up node PU, the drain of the fourth control transistor M6B is connected to the second pull-down node PD _ B, and the second pole of the fourth control transistor M6B is connected to the second low voltage terminal;
the gate driving signal output circuit includes a first output transistor M3, a first output pull-down transistor M13A, a second output pull-down transistor M13B, an output reset transistor M4, and a storage capacitor Cs;
the gate of the first output transistor M3 is connected to the pull-up node PU, the drain of the first output transistor M3 is connected to the clock signal terminal, and the source of the first output transistor M3 is connected to the gate drive signal output terminal OUT 1; the clock signal end is used for inputting a clock signal CLK;
the gate of the first output pull-down transistor M13A is connected to the first pull-down node PD _ a, the drain of the first output pull-down transistor M13A is connected to the gate driving signal output terminal OUT1, and the source of the first output pull-down transistor M13A is connected to the first low voltage terminal;
the gate of the second output pull-down transistor M13B is connected to the second pull-down node PD _ B, the drain of the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1, and the source of the second output pull-down transistor M13B is connected to the first low voltage terminal;
the gate of the output reset transistor M4 is connected to the third reset terminal RST _2, the drain of the output reset transistor M4 is connected to the gate driving signal output terminal OUT1, and the source of the output reset transistor M4 is connected to the first low voltage terminal;
the carry signal output circuit includes a second output transistor M11, a third output pull-down transistor M12A, and a fourth output pull-down transistor M12B;
the gate of the second output transistor M11 is connected to the pull-up node PU, the drain of the second output transistor M11 is connected to the clock signal terminal, and the source of the second output transistor M11 is connected to the carry signal output terminal OUT _ C;
the gate of the third output pull-down transistor M12A is connected to the first pull-down node PD _ a, the drain of the third output pull-down transistor M12A is connected to the carry signal output terminal OUT _ C, and the source of the third output pull-down transistor M12A is connected to the second low voltage terminal;
the gate of the fourth output pull-down transistor M12B is connected to the second pull-down node PD _ B, the drain of the fourth output pull-down transistor M12B is connected to the carry signal output terminal OUT _ C, and the source of the fourth output pull-down transistor M12B is connected to the second low voltage terminal;
the voltage supply circuit is connected with the first low voltage end and is used for supplying the first low voltage VGL, so that in an output stage, the grid-source voltage of M2, the grid-source voltage of M15, the grid-source voltage of M8A and the grid-source voltage of M8B are all less than or equal to 0, so that in an output stage, M2, M15, M8A and M8B are all completely turned off, and the leakage current of M2, the leakage current of M15, the leakage current of M8A and the leakage current of M8B are reduced.
In the first embodiment of the gate driving unit shown in fig. 5 of the present invention, all the transistors are NMOS transistors, but not limited thereto.
In operation of the first embodiment of the gate driving unit shown in fig. 5 of the present invention, the voltage supplying circuit supplies the first low voltage VGL to the first low voltage end, so that in the output stage, the gate-source voltage of M2, the gate-source voltage of M15, the gate-source voltage of M8A, and the gate-source voltage of M8B are all less than or equal to 0, so that in the output stage, M2, M15, M8A, and M8B are all completely turned off, and the leakage current of M2, the leakage current of M15, the leakage current of M8A, and the leakage current of M8B are reduced.
In the operation of the first embodiment of the gate driving unit shown in fig. 5 of the present invention, in the output stage, the gate potential of M15 and the gate potential of M2 are both VGL, the gate potential of M8A and the gate potential of M8B are slightly higher than LVGL, the source potential of M15, the source potential of M2, the source potential of M8A, and the source potential of M8B are all VGL, the voltage providing circuit provides VGL, VGL is higher than LVGL, so that the gate-source voltage of M15 and the gate-source voltage of M2 are equal to 0, and the gate-source voltage of M8A and the gate-source voltage of M8B are all lower than 0, so as to reduce the leakage current of M15, the leakage current of M2, the leakage current of M8A, and the leakage current of M8B.
In specific implementation, VGL may be-8V, and LVGL may be-11V, but not limited thereto.
In operation of the first embodiment of the gate driving unit shown in fig. 5 of the present invention, as shown in fig. 6A, the potential of PU can be kept at a high potential during the output stage S2.
Also, in operation of the first embodiment of the gate driver of the present invention as shown in fig. 5, fig. 6B is a waveform diagram of the gate driving signal output from OUT 1.
As can be seen from fig. 6B, the rise time Tr of the gate driving signal is reduced and the fall time Tf of the gate driving signal is reduced as compared with fig. 2B.
As shown in fig. 7, the second embodiment of the gate driving unit according to the present invention includes a pull-up node reset circuit 11, a pull-up node pull-down circuit 12, a pull-down node control circuit 14, an input circuit, a first pull-down control circuit, a second pull-down control circuit, a gate driving signal output circuit, a carry signal output circuit, and a control circuit; the control circuit includes a voltage supply circuit and a voltage control circuit (the voltage supply circuit and the voltage control circuit are not shown in fig. 7);
the pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B;
the gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of M15 is connected to the second reset terminal TGOA _ RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage end is used for inputting a first low voltage VGL;
the gate of the M8A is connected to the first pull-down node PD _ a, the drain of the M8A is connected to the pull-up node PU, and the source of the M8A is connected to the first low voltage terminal;
the gate of the M8B is connected to the second pull-down node PD _ B, the drain of the M8B is connected to the pull-up node PU, and the source of the M8B is connected to the first low voltage terminal;
the voltage supply circuit is connected with the first low voltage end and is used for supplying the first low voltage VGL, so that the grid-source voltage of M2 and the grid-source voltage of M15 are less than or equal to 0 in an output stage, and the M2 and the M15 are completely turned off in the output stage, so that the leakage current of M2 and the leakage current of M15 are reduced;
the pull-down node control circuit 14 includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
the gate of the first pull-down node control transistor M7A is connected to the INPUT terminal INPUT, the drain of the first pull-down node control transistor M7A is connected to the first pull-down node PD _ a, and the source of the first pull-down node control transistor M7A is connected to the third low voltage terminal; the third low voltage end is used for inputting a third low voltage LLVGL;
the gate of the second pull-down node control transistor M7B is connected to the INPUT terminal INPUT, the drain of the second pull-down node control transistor M7B is connected to the second pull-down node PD _ B, and the source of the second pull-down node control transistor M7B is connected to the third low voltage terminal;
the voltage control circuit is used for providing the third low voltage LLVGL for the third low voltage end, so that the grid-source voltage of M8A and the grid-source voltage of M8B are less than or equal to 0 in an output stage;
the input circuit includes an input transistor M1;
the gate and the drain of the INPUT transistor M1 are both connected to the INPUT terminal INPUT, and the source of the INPUT transistor M1 is connected to the pull-up node PU;
the first pull-down control circuit includes a first control transistor M5A and a second control transistor M6A;
the gate of the first control transistor M5A is connected to the first control voltage terminal, the drain of the first control transistor M5A is connected to the first control voltage terminal, and the second pole of the first control transistor M5A is connected to the first pull-down node PD _ a; the first control voltage end is used for inputting a first control voltage VDD _ A;
the gate of the second control transistor M6A is connected to the pull-up node PU, the drain of the second control transistor M6A is connected to the first pull-down node PD _ a, and the source of the second control transistor M6A is connected to the second low voltage terminal;
the second pull-down control circuit includes a third control transistor M5B and a fourth control transistor M6B;
a gate of the third control transistor M5B is connected to the second control voltage terminal, a drain of the third control transistor M5B is connected to the second control voltage terminal, and a source of the third control transistor M5B is connected to the second pull-down node PD _ B; the second control voltage end is used for inputting a second control voltage VDD _ B;
the gate of the fourth control transistor M6B is connected to the pull-up node PU, the drain of the fourth control transistor M6B is connected to the second pull-down node PD _ B, and the second pole of the fourth control transistor M6B is connected to the second low voltage terminal;
the gate driving signal output circuit includes a first output transistor M3, a first output pull-down transistor M13A, a second output pull-down transistor M13B, an output reset transistor M4, and a storage capacitor Cs;
the gate of the first output transistor M3 is connected to the pull-up node PU, the drain of the first output transistor M3 is connected to the clock signal terminal, and the source of the first output transistor M3 is connected to the gate drive signal output terminal OUT 1; the clock signal end is used for inputting a clock signal CLK;
the gate of the first output pull-down transistor M13A is connected to the first pull-down node PD _ a, the drain of the first output pull-down transistor M13A is connected to the gate driving signal output terminal OUT1, and the source of the first output pull-down transistor M13A is connected to the first low voltage terminal;
the gate of the second output pull-down transistor M13B is connected to the second pull-down node PD _ B, the drain of the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1, and the source of the second output pull-down transistor M13B is connected to the first low voltage terminal;
the gate of the output reset transistor M4 is connected to the third reset terminal RST _2, the drain of the output reset transistor M4 is connected to the gate driving signal output terminal OUT1, and the source of the output reset transistor M4 is connected to the first low voltage terminal;
the carry signal output circuit includes a second output transistor M11, a third output pull-down transistor M12A, and a fourth output pull-down transistor M12B;
the gate of the second output transistor M11 is connected to the pull-up node PU, the drain of the second output transistor M11 is connected to the clock signal terminal, and the source of the second output transistor M11 is connected to the carry signal output terminal OUT _ C;
the gate of the third output pull-down transistor M12A is connected to the first pull-down node PD _ a, the drain of the third output pull-down transistor M12A is connected to the carry signal output terminal OUT _ C, and the source of the third output pull-down transistor M12A is connected to the second low voltage terminal;
the gate of the fourth output pull-down transistor M13A is connected to the second pull-down node PD _ B, the drain of the fourth output pull-down transistor M13A is connected to the carry signal output terminal OUT _ C, and the source of the fourth output pull-down transistor M13A is connected to the second low voltage terminal.
In the second embodiment of the gate driving unit shown in fig. 7 of the present invention, all the transistors are NMOS transistors, but not limited thereto.
In the second embodiment of the gate driving unit shown in fig. 7 of the present invention, when operating, the voltage supply circuit supplies the first low voltage VGL to the first low voltage terminal, so that the gate-source voltage of M2 and the gate-source voltage of M15 are both equal to 0 in the output stage, so that M2 and M15 are completely turned off in the output stage, and the leakage current of M2 and the leakage current of M15 are reduced.
In the second embodiment of the gate driving unit shown in fig. 7 of the present invention, when operating, the voltage control circuit provides the third low voltage LLVGL to the third low voltage end, where LLVGL is smaller than LVGL, so that the potential of PD _ a and the potential of PD _ B are slightly higher than LLVGL in the output stage, and further, the gate-source voltage of M8A and the gate-source voltage of M8B are smaller than 0 in the output stage, so as to reduce the leakage current of M8A and the leakage current of M8B.
In specific implementation, the LLVGL can be-15V, but not limited thereto.
The gate driving method according to the embodiment of the present invention is applied to the gate driving unit, and includes:
in the output stage, the control circuit controls the grid-source voltage of a transistor connected with the pull-up node in the pull-up node reset circuit to be within a first preset voltage range, and controls the grid-source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range.
In the gate driving method according to the embodiment of the invention, in the output stage, the leakage current of the transistor connected with the pull-up node in the pull-up node reset circuit is controlled to be reduced, and the leakage current of the transistor connected with the pull-up node in the pull-up node pull-down circuit is controlled to be reduced, so that the potential of the pull-up node can be well maintained in the output stage, and the driving capability of the gate driving unit is ensured.
Specifically, a transistor connected to a pull-up node in the pull-up node reset circuit may be an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
the transistor connected to the pull-up node in the pull-up node reset circuit may be a p-type transistor, and the first predetermined voltage range is greater than or equal to 0.
Specifically, a transistor connected to the pull-up node in the pull-up node pull-down circuit may be an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
and a transistor connected with the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to 0.
The gate driving circuit according to the embodiment of the invention comprises a plurality of stages of gate driving units.
The display device provided by the embodiment of the invention comprises the gate drive circuit.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. A grid driving unit is characterized by comprising a pull-up node reset circuit, a pull-up node pull-down circuit and a control circuit;
the control circuit is used for controlling the grid-source voltage of a transistor connected with a pull-up node in the pull-up node reset circuit to be within a first preset voltage range and controlling the grid-source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range in an output stage;
a transistor connected with a pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
a transistor connected with a pull-up node in the pull-up node reset circuit is a p-type transistor, and the first preset voltage range is greater than or equal to 0;
a transistor connected with a pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
a transistor connected with a pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to 0;
the pull-up node pull-down circuit comprises a pull-up node pull-down transistor;
a control electrode of the pull-up node pull-down transistor is connected with a pull-down node, a first electrode of the pull-up node pull-down transistor is connected with the pull-up node, and a second electrode of the pull-up node pull-down transistor is connected with a second voltage end;
the control circuit comprises a voltage supply circuit; the voltage supply circuit is used for supplying a second voltage to the second voltage end, so that in an output stage, the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range; and/or the presence of a gas in the gas,
the control circuit comprises a voltage control circuit; the voltage control circuit is used for controlling the voltage of the pull-down node in an output stage so that the grid-source voltage of the pull-up node pull-down transistor is in a second preset voltage range.
2. The gate drive unit of claim 1, wherein the pull-up node reset circuit comprises a pull-up node reset transistor;
a control electrode of the pull-up node reset transistor is connected with a reset end, a first electrode of the pull-up node reset transistor is connected with the pull-up node, and a second electrode of the pull-up node reset transistor is connected with a first voltage end;
the control circuit comprises a voltage supply circuit;
the voltage supply circuit is used for supplying a first voltage to the first voltage terminal, so that in an output stage, the grid-source voltage of the pull-up node reset transistor is within a first preset voltage range.
3. The gate driving unit of claim 1, further comprising a pull-down node control circuit for controlling communication between the pull-down node and a third voltage terminal under control of an input signal inputted from the input terminal;
the control circuit comprises a voltage control circuit; the voltage control circuit is used for providing a third voltage to a third voltage end, so that in the output stage, the voltage of the pull-down node is the third voltage.
4. A gate driving method applied to the gate driving unit as claimed in any one of claims 1 to 3, the gate driving method comprising:
in the output stage, the control circuit controls the grid-source voltage of a transistor connected with a pull-up node in the pull-up node reset circuit to be within a first preset voltage range, and controls the grid-source voltage of a transistor connected with the pull-up node in the pull-up node pull-down circuit to be within a second preset voltage range;
a transistor connected with a pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
a transistor connected with a pull-up node in the pull-up node reset circuit is a p-type transistor, and the first preset voltage range is greater than or equal to 0;
a transistor connected with a pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
and a transistor connected with the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to 0.
5. A gate drive circuit comprising a plurality of stages of gate drive units as claimed in any one of claims 1 to 3.
6. A display device comprising the gate driver circuit according to claim 5.
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| CN108389539A (en) * | 2018-03-15 | 2018-08-10 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108877682A (en) * | 2018-07-18 | 2018-11-23 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN109166600A (en) * | 2018-10-26 | 2019-01-08 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN109192238A (en) * | 2018-10-30 | 2019-01-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
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