CN108829374B - Pseudo-random sequence generator circuit - Google Patents
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- CN108829374B CN108829374B CN201810834556.9A CN201810834556A CN108829374B CN 108829374 B CN108829374 B CN 108829374B CN 201810834556 A CN201810834556 A CN 201810834556A CN 108829374 B CN108829374 B CN 108829374B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
- G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention is applicable to the field of pseudo-random sequence generators, and provides a pseudo-random sequence generator circuit, which comprises a shift register module, a feedback logic module and a 0 row module, which are connected with the shift register module, and a power supply electrically connected with the shift register module, the feedback logic module and the 0 row module; the technical problem that the pseudo-random sequence generator cannot generate pseudo-random sequences with various lengths is solved.
Description
Technical Field
The invention belongs to the field of pseudo-random sequence generators, and particularly relates to a pseudo-random sequence generator circuit.
Background
A pseudo-random sequence is a periodic sequence with some random nature, with a predetermined certainty and repeatability, that can be repeatedly generated and reproduced. At present, the widely used pseudo-random sequence is obtained by filtering a periodic sequence generated by a digital circuit. The digital circuit for generating the pseudo-random sequence mainly comprises a linear feedback shift register and discrete components. The nature of the pseudo-random sequence is determined by the number of stages of the shift register, the initial state, the feedback logic, and the clock. After the number of stages and the clock of the shift register are determined, the output sequence is completely determined by the initial state of the shift register and the feedback logic.
Disclosure of Invention
The invention aims to provide a pseudo-random sequence generator circuit, which aims to solve the technical problem that a pseudo-random sequence generator cannot generate pseudo-random sequences with various lengths.
The invention is realized in such a way that the pseudo-random sequence generator circuit comprises a shift register module, a feedback logic module and a 0 row module which are connected with the shift register module, and a power supply which is electrically connected with the shift register module, the feedback logic module and the 0 row module;
the shift register module: the method comprises the steps of setting an initial state of a pseudo-random sequence generator and generating an output pseudo-random sequence;
the feedback logic module: for controlling the pseudo-random sequence generator to generate pseudo-random sequences of different lengths;
the row 0 module: for excluding the pseudo-random sequence generator from generating all 0 pseudo-random sequences;
the power supply: for providing the required voltages for the individual modules.
The invention further adopts the technical scheme that: the shift register module comprises a shift register U1, a shift register U2, a dial switch S3, a control switch S1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R9, wherein a 1 pin of the shift register U1 is respectively connected with a 1 pin of the shift register U2, one end of the resistor R1 and one end of the control switch S1, a 3 pin of the shift register U1 is respectively connected with one end of the resistor R9 and 8 pins of the dial switch S2, a 4 pin of the shift register U1 is respectively connected with one end of the resistor R2 and 7 pins of the dial switch S2, 5 pins of the shift register U1 are respectively connected with one end of the resistor R3 and 6 pins of the dial switch S2 pins, 6 pins of the shift register U1 is respectively connected with one end of the resistor R4 and 5 pins of the dial switch S2, the 10 pins of the shift register U1 are connected with the 10 pins of the shift register U2, the 2 pins of the shift register U2 are respectively connected with one end of the resistor R5 and the 8 pins of the dial switch S3, the 3 pins of the shift register U2 are respectively connected with one end of the resistor R6 and the 7 pins of the dial switch S3, the 4 pins of the shift register U2 are respectively connected with one end of the resistor R7 and the 6 pins of the dial switch S3, the 5 pins of the shift register U2 are respectively connected with one end of the resistor R8 and the 5 pins of the dial switch S3, the other end of the resistor R1, the other end of the resistor R2, the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8, the other end of the resistor R9, the 9 pin of the shift register U1 and the 9 pin of the shift register U2 are all connected with the power supply, and the other end of the control switch S1, the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S2 and the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S3 are all connected with GND.
The invention further adopts the technical scheme that: the feedback logic module comprises a feedback stage switch S4, an exclusive-OR gate U3A, an exclusive-OR gate U3B, an exclusive-OR gate U3C, an exclusive-OR gate U7A, an exclusive-OR gate U7B, an exclusive-OR gate U7C and an exclusive-OR gate U7D, wherein the 1 pin of the feedback stage switch S4 is connected with the 15 pin of the shift register U1, the 2 pin of the feedback stage switch S4 is connected with the 14 pin of the shift register U1, the 3 pin of the feedback stage switch S4 is connected with the 13 pin of the shift register U1, the 4 pin of the feedback stage switch S4 is connected with the 12 pin of the shift register U1, the 5 pin of the feedback stage switch S4 is connected with the 15 pin of the shift register U2, the 6 pin of the feedback stage switch S4 is connected with the 14 pin of the shift register U2, the 7 pin of the feedback stage switch S4 is connected with the 13 pin of the shift register U2, the 8 pin of the feedback stage switch S4 is connected with the 12 pin of the shift register U2, the 9 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7D, the 10 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7D, the 11 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7C, the 12 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7C, the 13 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7B, the 14 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7B, the 15 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7A, the 16 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7A, the output end of the exclusive-OR gate U7D is connected with the 2 nd input end of the exclusive-OR gate U3B, the output end of the exclusive-or gate U7C is connected with the 1 st input end of the exclusive-or gate U3B, the output end of the exclusive-or gate U7B is connected with the 2 nd input end of the exclusive-or gate U3A, the output end of the exclusive-or gate U7A is connected with the 1 st input end of the exclusive-or gate U3B, the output end of the exclusive-or gate U3B is connected with the 2 nd input end of the exclusive-or gate U3C, the output end of the exclusive-or gate U3A is connected with the 1 st input end of the exclusive-or gate U3C, and the output end of the exclusive-or gate U3C is connected with the 2 pin of the shift register U1.
The invention further adopts the technical scheme that: the row 0 module comprises an OR gate U4A, an OR gate U4B, an OR gate U4C, an OR gate U5A, an OR gate U5B, an OR gate U5C, an OR gate U5D and an NOT gate U6A, wherein the 1 st input end of the OR gate U4A is connected with the 15 pin of the shift register U2, the 2 nd input end of the OR gate U4A is connected with the 14 pin of the shift register U2, the 1 st input end of the OR gate U4B is connected with the 13 pin of the shift register U2, the 2 nd input end of the OR gate U4B is connected with the 12 pin of the shift register U4C, the output end of the OR gate U4A is connected with the 1 st terminal of the OR gate U4C, the 1 st input end of the OR gate U5A is connected with the 12 pin of the shift register U1, the 2 nd input end of the OR gate U5A is connected with the 13 pin of the OR gate U1, the output end of the OR gate U5B is connected with the output terminal of the OR gate U5C 1, the output end of the OR gate 5D is connected with the output terminal of the OR gate 5C 1, and the output end of the OR gate 5D is connected with the output terminal of the OR gate 5C is connected with the output terminal of the U5C 1.
The beneficial effects of the invention are as follows: the 2 groups of 4-bit dial switches are utilized to replace single initial state setting, the initial state can be flexibly set according to requirements, the number is not required to be manually set again, and the feedback logic module is reasonably set through the switches according to different requirements of the generated sequence length, so that the output of a plurality of pseudo-random sequences with different lengths is realized.
Drawings
FIG. 1 is a block diagram of a pseudo-random sequence generator circuit provided by an embodiment of the present invention;
fig. 2 is an electrical schematic diagram of a pseudo-random sequence generator circuit according to an embodiment of the present invention.
Detailed Description
1-2 illustrate a pseudo-random sequence generator circuit provided by the invention, the pseudo-random sequence generator circuit comprises a shift register module, a feedback logic module and a row 0 module which are connected with the shift register module, and a power supply which is electrically connected with the shift register module, the feedback logic module and the row 0 module;
the shift register module: the method comprises the steps of setting an initial state of a pseudo-random sequence generator and generating an output pseudo-random sequence;
the feedback logic module: for controlling the pseudo-random sequence generator to generate pseudo-random sequences of different lengths;
the row 0 module: for excluding the pseudo-random sequence generator from generating all 0 pseudo-random sequences;
the power supply: for providing the required voltages for the individual modules.
The shift register module comprises a shift register U1, a shift register U2, a dial switch S3, a control switch S1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R9, wherein a 1 pin of the shift register U1 is respectively connected with a 1 pin of the shift register U2, one end of the resistor R1 and one end of the control switch S1, a 3 pin of the shift register U1 is respectively connected with one end of the resistor R9 and 8 pins of the dial switch S2, a 4 pin of the shift register U1 is respectively connected with one end of the resistor R2 and 7 pins of the dial switch S2, 5 pins of the shift register U1 are respectively connected with one end of the resistor R3 and 6 pins of the dial switch S2 pins, 6 pins of the shift register U1 is respectively connected with one end of the resistor R4 and 5 pins of the dial switch S2, the 10 pins of the shift register U1 are connected with the 10 pins of the shift register U2, the 2 pins of the shift register U2 are respectively connected with one end of the resistor R5 and the 8 pins of the dial switch S3, the 3 pins of the shift register U2 are respectively connected with one end of the resistor R6 and the 7 pins of the dial switch S3, the 4 pins of the shift register U2 are respectively connected with one end of the resistor R7 and the 6 pins of the dial switch S3, the 5 pins of the shift register U2 are respectively connected with one end of the resistor R8 and the 5 pins of the dial switch S3, the other end of the resistor R1, the other end of the resistor R2, the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8, the other end of the resistor R9, the 9 pin of the shift register U1 and the 9 pin of the shift register U2 are all connected with the power supply, and the other end of the control switch S1, the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S2 and the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S3 are all connected with GND. The initial state is set through the dial switch S2 and the dial switch S3, the right shift output is determined (the specific logic function is determined by S0=1 and S1=0 of 9 pins and 10 pins of the shift register U1 and the shift register U2), and after power-on, the shift register U1 and the shift register U2 continuously shift right under the action of clock signals to generate an output sequence.
The feedback logic module comprises a feedback stage number switch S4, an exclusive-or gate U3A, an exclusive-or gate U3B, an exclusive-or gate U3C, an exclusive-or gate U7A, an exclusive-or gate U7B, an exclusive-or gate U7C and an exclusive-or gate U7D, wherein the 1 pin of the feedback stage number switch S4 is connected with the 15 pin of the shift register U1, the 2 pin of the feedback stage number switch S4 is connected with the 14 pin of the shift register U1, the 3 pin of the feedback stage number switch S4 is connected with the 13 pin of the shift register U1, the 4 pin of the feedback stage number switch S4 is connected with the 12 pin of the shift register U1, the 5 pin of the feedback stage number switch S4 is connected with the 15 pin of the shift register U2, the 6 pin of the feedback stage number switch S4 is connected with the 14 pin of the shift register U2, the 7 pin of the feedback stage number switch S4 is connected with the 13 pin of the shift register U2, the 8 pin of the feedback stage number switch S4 is connected with the 12 pin of the shift register U2, and the 4 is connected with the 9 th input end of the exclusive-or gate 7The 1 st input end of the exclusive-or gate U7D is connected with the 10 pin of the feedback series switch S4, the 2 nd input end of the exclusive-or gate U7C is connected with the 11 pin of the feedback series switch S4, the 1 st input end of the exclusive-or gate U7C is connected with the 12 pin of the feedback series switch S4, the 2 nd input end of the exclusive-or gate U7B is connected with the 13 pin of the feedback series switch S4, the 1 st input end of the exclusive-or gate U7B is connected with the 14 pin of the feedback series switch S4, the 15 pin of the feedback series switch S4 is connected with the 2 nd input end of the exclusive-or gate U7A, the 16 pin of the feedback series switch S4 is connected with the 1 st input end of the exclusive-or gate U7A, the output end of the exclusive-or gate U7D is connected with the 2 nd input end of the exclusive-or gate U3B, the output end of the exclusive-or gate U7C is connected with the 1 st input end of the exclusive-or gate U3B, and the output end of the exclusive-or gate U7B is connected with the 1 st input end of the exclusive-or gate U3B. First, to generate a period of 2 n The longest sequence of-1 (n is the number of stages of the shift register), requires that the characteristic polynomial of the pseudo-random sequence generator must be an n-degree primitive polynomial (obtainable by a look-up table). According to the length requirement of the sequence to be generated, the feedback logic relation is determined by 8-ary representation coefficients of the corresponding primitive polynomials, the number of stages participating in feedback is determined by selecting a feedback stage number switch S4, and then the feedback is sent to an exclusive OR gate 4070 (U7A, U7B, U7C, U7D and U3A, U3B, U C), and after the exclusive OR is finished, the feedback logic relation is sent to 2 pins (right shift serial input end DSR) of a shift register U1.
The row 0 module comprises an OR gate U4A, an OR gate U4B, an OR gate U4C, an OR gate U5A, an OR gate U5B, an OR gate U5C, an OR gate U5D and an NOT gate U6A, wherein the 1 st input end of the OR gate U4A is connected with the 15 pin of the shift register U2, the 2 nd input end of the OR gate U4A is connected with the 14 pin of the shift register U2, the 1 st input end of the OR gate U4B is connected with the 13 pin of the shift register U2, the 2 nd input end of the OR gate U4B is connected with the 12 pin of the shift register U4C, the output end of the OR gate U4A is connected with the 1 st terminal of the OR gate U4C, the 1 st input end of the OR gate U5A is connected with the 12 pin of the shift register U1, the 2 nd input end of the OR gate U5A is connected with the 13 pin of the OR gate U1, the output end of the OR gate U5B is connected with the output terminal of the OR gate U5C 1, the output end of the OR gate 5D is connected with the output terminal of the OR gate 5C 1, and the output end of the OR gate 5D is connected with the output terminal of the OR gate 5C is connected with the output terminal of the U5C 1. Note that when all 0 s are output, the bank 0 circuit is set. The 12, 13, 14 and 15 pins of the shift register U1 and the 12, 13, 14 and 15 pins of the shift register U2 are combined into a row 0 circuit by the or gate 4071 (including U4A, U4B, U C and U5A, U5B, U5C, U5D), the not gate (U6A) and the final output is sent to the operation mode control terminals S1 of the shift register U1 and the shift register U2. When the output is not 0, S1 can be ensured to be always kept to be 0 (the circuit is set to be high level S0) and is in a continuous right shift mode; when the output is all 0, 8 0 outputs are 0 through OR gate 4071, then become 1 through NOT gate 4069, make operation mode control end S1 be 1, at this time the circuit is in the number sending mode, send the initial state that has set for before again into the input, realize the self-starting when all 0 outputs.
The 2 groups of 4-bit dial switches are utilized to replace single initial state setting, the initial state can be flexibly set according to requirements, the number is not required to be manually set again, and a feedback logic module is reasonably set through the switches according to different requirements of the generated sequence length, so that the output of a plurality of pseudo-random sequences with different lengths is realized, and the generation of the pseudo-random sequences with the lengths of 3, 7, 15, 31, 63, 127 and 255 can be realized.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (3)
1. A pseudo-random sequence generator circuit, characterized by: the pseudo-random sequence generator circuit comprises a shift register module, a feedback logic module and a 0 row module which are connected with the shift register module, and a power supply which is electrically connected with the shift register module, the feedback logic module and the 0 row module;
the shift register module: the method comprises the steps of setting an initial state of a pseudo-random sequence generator and generating an output pseudo-random sequence;
the feedback logic module: for controlling the pseudo-random sequence generator to generate pseudo-random sequences of 3, 7, 15, 31, 63, 127, 255 for a total of 7 lengths;
the feedback logic module comprises a feedback stage switch S4, an exclusive-OR gate U3A, an exclusive-OR gate U3B, an exclusive-OR gate U3C, an exclusive-OR gate U7A, an exclusive-OR gate U7B, an exclusive-OR gate U7C and an exclusive-OR gate U7D, wherein the 1 pin of the feedback stage switch S4 is connected with the 15 pin of the shift register U1, the 2 pin of the feedback stage switch S4 is connected with the 14 pin of the shift register U1, the 3 pin of the feedback stage switch S4 is connected with the 13 pin of the shift register U1, the 4 pin of the feedback stage switch S4 is connected with the 12 pin of the shift register U1, the 5 pin of the feedback stage switch S4 is connected with the 15 pin of the shift register U2, the 6 pin of the feedback stage switch S4 is connected with the 14 pin of the shift register U2, the 7 pin of the feedback stage switch S4 is connected with the 13 pin of the shift register U2, the 8 pin of the feedback stage switch S4 is connected with the 12 pin of the shift register U2, the 9 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7D, the 10 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7D, the 11 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7C, the 12 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7C, the 13 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7B, the 14 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7B, the 15 pin of the feedback level switch S4 is connected with the 2 nd input end of the exclusive-OR gate U7A, the 16 pin of the feedback level switch S4 is connected with the 1 st input end of the exclusive-OR gate U7A, the output end of the exclusive-OR gate U7D is connected with the 2 nd input end of the exclusive-OR gate U3B, the output end of the exclusive-or gate U7C is connected with the 1 st input end of the exclusive-or gate U3B, the output end of the exclusive-or gate U7B is connected with the 2 nd input end of the exclusive-or gate U3A, the output end of the exclusive-or gate U7A is connected with the 1 st input end of the exclusive-or gate U3B, the output end of the exclusive-or gate U3B is connected with the 2 nd input end of the exclusive-or gate U3C, the output end of the exclusive-or gate U3A is connected with the 1 st input end of the exclusive-or gate U3C, and the output end of the exclusive-or gate U3C is connected with the 2 pin of the shift register U1;
the row 0 module: for excluding the pseudo-random sequence generator from generating all 0 pseudo-random sequences;
the power supply: for providing the required voltages for the individual modules.
2. The pseudo-random sequence generator circuit of claim 1, wherein said shift register module comprises a shift register U1, a shift register U2, a dial switch S3, a control switch S1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9, wherein a 1 pin of said shift register U1 is connected to a 1 pin of said shift register U2, one end of said resistor R1 and one end of said control switch S1, a 3 pin of said shift register U1 is connected to one end of said resistor R9 and an 8 pin of said dial switch S2, a 4 pin of said shift register U1 is connected to one end of said resistor R2 and 7 of said dial switch S2, a 5 pin of said shift register U1 is connected to one end of said resistor R3 and another end of said resistor R2, a 5 pin of said shift register U2 is connected to said pin of said resistor R6 of said shift register U1, a 5 pin of said shift register U2 is connected to said pin of said resistor R2, a 5 pin of said shift register U2 is connected to said one end of said resistor R2, a 5 pin of said 3 pin of said shift register U2 is connected to said pin of said resistor R2, and another end of said resistor R2 is connected to said pin of said resistor R2, respectively, and said pin of said pin is connected to said pin of said 3 of said resistor 3 is connected to said resistor R2, said resistor R3 is connected to said one end of said resistor R3, and said 7 is connected to said 7, respectively, said one end of said pin is connected to said 3, said one end of said resistor R3 and said 3 is connected, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8, the other end of the resistor R9, the 9 pin of the shift register U1 and the 9 pin of the shift register U2 are all connected with the power supply, and the other end of the control switch S1, the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S2 and the 1 pin, the 2 pin, the 3 pin and the 4 pin of the dial switch S3 are all connected with GND.
3. The pseudo-random sequence generator circuit according to claim 2, wherein said bank 0 module comprises an or gate U4A, an or gate U4B, an or gate U4C, an or gate U5A, an or gate U5B, an or gate U5C, an or gate U5D, and an nor gate U6A, wherein the 1 st input of said or gate U4A is connected to the 15 pin of said shift register U2, the 2 nd input of said or gate U4A is connected to the 14 pin of said shift register U2, the 1 st input of said or gate U4B is connected to the 13 pin of said shift register U2, the 2 nd input of said or gate U4B is connected to the 12 pin of said shift register U2, the output of said or gate U4A is connected to the 1 st terminal of said or gate U4C, the 1 st input of said or gate U4B is connected to the 12 pin of said shift register U1, the 13 pin of said or gate U5A is connected to the output of said or gate U5B, the output of said or gate 5B is connected to the 1 st terminal of said or gate U5C, the output of said or gate 5B is connected to the 1 st terminal of said or gate 5C is connected to the output terminal of said or gate 5C, the output of said or gate 5B is connected to the 1 st terminal of said or gate 5C.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4719643A (en) * | 1984-12-24 | 1988-01-12 | Gte Communication Systems Corporation | Pseudo random framing generator circuit |
| CN102736892A (en) * | 2012-07-08 | 2012-10-17 | 安徽建筑工业学院 | Nonlinear pseudorandom sequence generator |
| CN103440119A (en) * | 2013-07-08 | 2013-12-11 | 中国航空无线电电子研究所 | M sequence generator-based primitive polynomial pseudo-random sequence generator |
| CN204856461U (en) * | 2015-08-12 | 2015-12-09 | 中国电子科技集团公司第四十一研究所 | Optional pseudo -random signal generator of data bits |
| CN105302521A (en) * | 2015-11-04 | 2016-02-03 | 上海电机学院 | FPGA based pseudo code generation circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7487194B2 (en) * | 2006-04-05 | 2009-02-03 | Peter Lablans | Binary and n-valued LFSR and LFCSR based scramblers, descramblers, sequence generators and detectors in Galois configuration |
-
2018
- 2018-07-26 CN CN201810834556.9A patent/CN108829374B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4719643A (en) * | 1984-12-24 | 1988-01-12 | Gte Communication Systems Corporation | Pseudo random framing generator circuit |
| CN102736892A (en) * | 2012-07-08 | 2012-10-17 | 安徽建筑工业学院 | Nonlinear pseudorandom sequence generator |
| CN103440119A (en) * | 2013-07-08 | 2013-12-11 | 中国航空无线电电子研究所 | M sequence generator-based primitive polynomial pseudo-random sequence generator |
| CN204856461U (en) * | 2015-08-12 | 2015-12-09 | 中国电子科技集团公司第四十一研究所 | Optional pseudo -random signal generator of data bits |
| CN105302521A (en) * | 2015-11-04 | 2016-02-03 | 上海电机学院 | FPGA based pseudo code generation circuit |
Non-Patent Citations (2)
| Title |
|---|
| 伪随机序列发生器的研究与实现;孙淑琴 等;《吉林大学学报》;第22卷(第3期);第185-188页 * |
| 基于74LS194的m序列发生器设计;吴海涛 等;《肇庆学院学报》;第31卷(第5期);第11-15页 * |
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|---|---|
| CN108829374A (en) | 2018-11-16 |
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