JP6697776B2 - Unique information generator - Google Patents

Description

  The present invention relates to a unique information generating device, and more particularly to a unique information generating device that generates difficult-to-copy unique information based on physical characteristics.

  BACKGROUND ART Conventionally, it is known to use a PUF (Physically Unclonable Function) technology for generating unique information that is difficult to copy based on physical characteristics, such as for authenticating electronic devices. Reference 1).

  That is, in a circuit based on the PUF technology (hereinafter referred to as a PUF circuit), even if the circuits are manufactured in the same manufacturing process with the same layout configuration, physical characteristics (transmission signal Utilizing the fact that delay time, wiring capacitance, element characteristics, etc. are slightly different, an output of 1 to several bits (response and The process of returning (call) is repeated multiple times while changing the challenge pattern to generate a response composed of multiple bit responses.

  The relationship between the challenge and the response has the reproducibility that the same PUF circuit always returns the same response to the same challenge. On the other hand, since PUF circuits having the same circuit configuration but different physical characteristics have different physical characteristics, there is randomness (uniqueness) between them, in which responses having no correlation with each other are returned to the same challenge. The above-mentioned difference in physical characteristics is caused by uncontrollable manufacturing variations as described above, and is difficult to copy. Therefore, the response output from the PUF circuit can be used as unique information (ID) that is difficult to copy.

  Thus, for example, when a PUF circuit is mounted on a semiconductor integrated circuit or other electronic device, the response output when a known challenge is input to the mounted PUF circuit becomes the unique information of the electronic device, and therefore the challenge. Whether or not the response obtained when is input is the unique information of the original value can be used for authenticity determination of the electronic device by comparing it with the unique information of the original value registered in advance. The unique information generated by such a PUF circuit is likened to biometric information such as a human fingerprint.

  However, the above PUF circuit tries to obtain different responses from the same circuit configuration by utilizing variations in physical characteristics. There is a problem that the number of challenges is required and the throughput is low. Therefore, in order to solve this problem, a Pseudo-LFSR PUF (hereinafter, PL-PUF) simulating the structure of an LFSR (Linear Feedback Shift Register) has been proposed (for example, see Non-Patent Document 1). ).

FIG. 8 shows a circuit diagram of an example of the PL-PUF circuit. A PL-PUF circuit based on the PL-PUF technology shown in the figure uses a feedback polynomial "x ¹²⁸ +x ¹²⁶ +x ¹⁰¹ +x ⁹⁹ +1" by 128 core circuits 100 and three adders 200 shown by rectangles. The circuit configuration imitates a satisfactory LFSR. The core circuit 100 has a configuration in which an output terminal of an inverter 102 is connected to one input terminal of a 2-input 1-output selector 101. An oscillation operation/stop control signal is input as a select signal to the selector 101, and one of the two input terminals is supplied with the signal Din from the core circuit 100 or the adder 200 at the preceding stage via the inverter 102. , 128-bit challenge 1-bit Dinit is input to the other input terminal.

  The PL-PUF circuit controls the selector 101 of each core circuit 100 by a timing control signal from a counter (not shown) so that the selector 101 of each core circuit 100 outputs the input signal as it is. A circuit is configured to start an oscillating operation, and then a selector 101 of each core circuit 100 is turned off by a timing control signal output at the time when the counter counts a fixed number of external clocks (that is, when the counter oscillates for a fixed time). The oscillation is stopped by controlling and breaking the feedback loop, and the response of each core circuit 100 at that time is held in the register.

  In this way, the output values D[1] to D[128] of each core circuit 100 when oscillating for a certain period of time are determined based on the physical characteristics of the core circuit 100, the adder 200, and the signal lines connecting them. However, the physical characteristics are values peculiar to the PL-PUF circuit due to uncontrollable manufacturing variations that inevitably occur. Therefore, the PL-PUF circuit outputs the output values D[1] to D[128] as unique information (response) that is difficult to copy. In this PL-PUF circuit, the output value changes by changing the oscillation time (cycle number) to be operated. In the PL-PUF circuit of FIG. 8, a 128-bit input (challenge) to a 128-bit output value (response) is obtained, and for example, a high throughput of 3 Gbps or more is obtained at an operating frequency of 24 MHz.

JP, 2011-198317, A

Yohei Hori et al., “Pseudo-LFSR PUF:A Compact,Efficient and Reliable Physical Unclonable Function”,in Proc.ReConFig2011,pp.223-228,2011

  Here, the physical characteristics of the ring-structured circuit element including the core circuit 100 and the adder 200 that configure the PL-PUF circuit, and the signal lines that connect them are plural due to the uncontrollable manufacturing variations that inevitably occur. Although slightly different among the PL-PUF circuits, the same PL-PUF circuit always outputs the same unique information for the same challenge (reproducible). However, when the power supply voltage of the PL-PUF circuit fluctuates, the operating speed of the PL-PUF circuit changes and the synchronization between the oscillation signal and the control signal is lost. As a result, even if the same challenge is input to the same PL-PUF circuit, the power supply voltage is changed. The original unique information (response) with the same value as before the fluctuation cannot be obtained (reproducibility cannot be obtained), and an error occurs in the outputted unique information. FIG. 9 shows a characteristic diagram of an example of the power supply voltage fluctuation vs. output error rate of the PL-PUF circuit. As shown in FIG. 9, when the power supply voltage fluctuates by 10 mV, an error rate of 46.5% is generated and unique information is generated.

  Therefore, it is important to take measures against fluctuations in the power supply voltage of the PL-PUF circuit in order to reduce the error rate. As one of the conventionally known methods as a measure against the fluctuation of the power supply voltage, there is a method of detecting the power supply voltage fluctuation by an analog circuit or the like and feeding back the detection result to a circuit for compensating the power supply voltage. However, this method cannot be applied to a circuit that requires strict timing control, such as a PL-PUF circuit, because the delay required for feedback is not small.

  Further, there is also known a configuration as described in Japanese Patent Laid-Open No. 2005-269196 in which a timing generation circuit is placed under a power supply to take measures against fluctuations in the power supply voltage. However, the purpose of this measure against fluctuation is to disperse the spectrum of the electromagnetic wave radiation by changing the timing of the clock so as to avoid the concentration of the spectrum at a specific frequency. There is no purpose for performance improvement. In addition, since the spectral dispersion of electromagnetic wave radiation need only be dispersed indiscriminately, it is inappropriate to use it as a measure against fluctuations in the power supply voltage of the PL-PUF circuit.

  The present invention has been made in view of the above points, and when a circuit simulating the structure of a linear feedback shift register is used to generate unique information that is difficult to copy based on the physical characteristics of the constituent circuit elements, the power supply voltage is It is an object of the present invention to provide a unique information generating device that can generate unique information with good reproducibility even if it changes.

  In order to achieve the above object, the unique information generating device of the present invention uses a circuit configuration imitating the structure of a linear feedback shift register to generate unique information of a plurality of bits that is difficult to copy based on the physical characteristics of the constituent circuit elements. The information generation circuit that outputs the information generation circuit and the first and second timing signals generated to the information generation circuit are supplied, and the generation unique information at the operation time point after an arbitrary set time has elapsed from the start of the operation of the information generation circuit It is characterized by including a timing generation circuit held by the generation circuit and a power supply voltage source for supplying a common operation power supply voltage to the information generation circuit and the timing generation circuit.

  Here, in the above information generating circuit of the present invention, the start and stop of the oscillating operation are controlled by the first timing signal, and an oscillation imitating a structure of a linear feedback shift register that oscillates and outputs a plurality of bits of unique information during operation A circuit and a register for holding a plurality of bits of unique information output from the oscillator circuit when the second timing signal is input are provided. This information generation circuit is a circuit based on the PL-PUF technology.

  Further, the above timing signal generation circuit in the present invention includes a first timing signal generation unit that generates a first timing signal having a predetermined logical value by inputting a trigger signal from the outside and starts the operation of the information generation circuit. And a second timing signal generation section for generating a second timing signal at a time point when an arbitrary set time has elapsed from the operation start time point of the information generation circuit and holding the unique information generated by the information generation circuit. And

  Further, the first timing signal generating section in the present invention has at least a ring oscillator that starts an oscillating operation and outputs the first timing signal from the time of input of the trigger signal, and the second timing signal. The generation unit monitors whether or not the oscillation operation time of the ring oscillator reaches an arbitrary set time, and outputs a second timing signal when the set time is reached, and a sequential circuit that outputs an arbitrary set time to the sequential circuit. And at least a setting unit for setting.

  Further, the first timing signal generating section in the present invention is an input/output section that outputs the external trigger signal as it is as the first timing signal, and the second timing signal generating section is input. A delay circuit unit that generates delay signals having a plurality of different delay times based on the trigger signal and outputs the delay signals in parallel, and a plurality of delay signals that are output in parallel from the delay circuit unit. And a selection circuit section for selecting a delay signal having a delay time corresponding to an arbitrary set time after outputting the signal and outputting the selected delay signal as a second timing signal.

  According to the present invention, since the power supply voltages of the information generation circuit and the timing generation circuit are the same, when the power supply voltage of the information generation circuit fluctuates, the power supply voltage of the timing generation circuit also fluctuates by the same amount. It is possible to generate the unique information having the same value as the previous normal time, and suppress the deterioration of reproducibility due to the fluctuation of the power supply voltage.

1 is a schematic configuration diagram of an embodiment of a unique information generating device according to the present invention. FIG. 3 is a circuit diagram of an embodiment of a PL-PUF circuit that constitutes a part of the unique information generation device according to the present invention. FIG. 6 is a circuit diagram of a first embodiment of a response acquisition timing generation circuit that constitutes another part of the unique information generation device according to the present invention. FIG. 6 is a circuit diagram of a second embodiment of a response acquisition timing generation circuit that constitutes another part of the unique information generation device according to the present invention. 6 is a flowchart for explaining the operation of the unique information generation device according to the present invention. 6 is a timing chart for explaining the effect of the unique information generation device according to the present invention. FIG. 9 is a characteristic diagram showing an example of power supply voltage fluctuation vs. output error rate of the PL-PUF circuit of the present invention and an example of power supply voltage fluctuation vs. output error rate of a conventional PL-PUF circuit. It is a circuit diagram of an example of a PL-PUF circuit. It is a characteristic view of an example of the power supply voltage fluctuation and the output error rate of the conventional PL-PUF circuit.

First, an embodiment of the unique information generating apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration diagram of an embodiment of a unique information generating apparatus according to the present invention. In the figure, the unique information generation device 10 of the present embodiment is provided with a response acquisition timing generation circuit 12 that supplies a response acquisition timing signal to the PL-PUF circuit 11, and the power supply voltage of the response acquisition timing generation circuit 12 is PL-. The power supply voltage source 13 has the same power supply voltage as the PUF circuit 11.

  The PL-PUF circuit 11 is a known circuit based on the PL-PUF technology, which uses a circuit simulating the structure of an LFSR to generate unique information of a plurality of bits that is difficult to copy based on the physical characteristics of its constituent circuit elements. And constitutes the information generating circuit of the present invention. The response acquisition timing generation circuit 12 operates by being supplied with the same power supply voltage from the power supply voltage source 13 that supplies a power supply voltage to the PL-PUF circuit 11, and generates a response acquisition timing signal and supplies it to the PL-PUF circuit 11. Then, the circuit for controlling the operation constitutes the timing generation circuit of the present invention.

  According to the unique information generation device 10 of the present embodiment, the PL-PUF circuit 11 outputs a plurality of bits when the oscillation operation is performed for an arbitrary set time based on the response acquisition timing signal supplied from the response acquisition timing generation circuit 12. The value (PUF response) is output as unique information (ID). Here, when the power supply voltage supplied from the power supply voltage source 13 to the PL-PUF circuit 11 changes by ΔV, the oscillation operation speed of the PL-PUF circuit 11 changes, but the power supply voltage of the response acquisition timing generation circuit 12 also has the same value. Since ΔV fluctuates, the response acquisition timing signal also changes in synchronization with the change in oscillation operation speed. As a result, according to the unique information generating apparatus 10 of the present embodiment, it is possible to suppress the change in the PUF response and reduce the error rate of the generated unique information.

Next, the configurations of the PL-PUF circuit 11 and the response acquisition timing generation circuit 12 that configure the unique information generation device 10 of the present exemplary embodiment will be described in more detail.
FIG. 2 shows a circuit diagram of an embodiment of a PL-PUF circuit which constitutes a part of the unique information generating apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. 2, in the PL-PUF circuit 11, as in the PL-PUF circuit shown in FIG. 8, 128 core circuits C1 to C128 and three adders A1 to A3 form a feedback polynomial "x ¹²⁸ +x". Oscillation circuit 111 having a circuit configuration imitating an LFSR satisfying " ¹²⁶ +x ¹⁰¹ +x ⁹⁹ +1" and responses R[1] to R[128] that are outputs of core circuits C1 to C12 (output value D[ in FIG. 8 1] to D[128]).

  The core circuits C1 to C128 have the same circuit configuration, and as shown in FIG. 2, for example, the core circuits C128 and C127 each include one inverter I128 and I127 and one two-input one-output selector S128 and S127. The outputs of the core circuits C1 and C128 of the preceding stage are supplied to one input terminal 1 of the selectors S128 and S127 via the inverters I128 and I127, and the other input terminal 0 corresponds to one bit of the 128-bit challenge. Challenges C[128] and C[127] are supplied. Further, the same select signal SEL is supplied from the response acquisition timing generation circuit 12 to the selectors of the core circuits C1 to C128. The register 112 holds the 128-bit responses R[1] to R[128] output from the oscillation circuit 111 when the capture signal Cap is supplied from the response acquisition timing generation circuit 12, and uses it as a PUF response. Output. The select signal SEL corresponds to the first timing signal in the present invention, and the capture signal Cap corresponds to the second timing signal in the present invention.

  FIG. 3 is a circuit diagram of a first embodiment of a response acquisition timing generation circuit which constitutes another part of the unique information generation device according to the present invention. 3, the response acquisition timing generation circuit 12A of this embodiment corresponds to the response acquisition timing generation circuit 12 of FIG. 1, and includes a ring oscillator 121, a delay circuit 122, a sequential circuit 123, a register 124, and timing adjustment. It is composed of a circuit 125 and a selector 126, which operate with a power supply voltage from the same power supply voltage source (not shown) as the PL-PUF circuit 11.

  In the ring oscillator 121, one 2-input NAND circuit and a plurality of inverters are connected in series, and the output terminal of the final-stage inverter among the plurality of inverters is connected to the plurality of inverters through the 2-input NAND circuit. A ring circuit structure is connected to the input terminal of the first-stage inverter, and a 2-input NAND circuit is used for a period in which a high-level (hereinafter, logic “1”) activation trigger signal is input to the other input terminal of the 2-input NAND circuit. It oscillates at a constant cycle according to the number of circuits and inverters.

  The delay circuit 122 has a configuration in which three flip-flops (FFs) are connected in cascade, the output signal of the ring oscillator 121 is commonly supplied to the clock terminals of these three FFs, and the data input of the first-stage FF is input. The start trigger signal supplied to the terminal is delayed by three cycles of the output signal of the ring oscillator 121 and output from the output terminal of the FF at the final stage as the select signal SEL. The delay circuit 122 enables the minimum value of the time from when the select signal SEL becomes logical “1” until the capture signal Cap output from the selector 126 described later becomes logical “1” to be “0”. It is a delay register for, but can be omitted.

  The sequential circuit 123 is a counter that outputs a signal of logic “1” at the time when the output signal of the ring oscillator 121 is counted by an arbitrary set value set by the register 124. That is, the sequential circuit 123 outputs a signal (capture signal) of logic “1” when the oscillation time of the ring oscillator 121 reaches the time corresponding to the set value. The register 124 supplies an arbitrary set value that determines the oscillation time of the ring oscillator 121 to the sequential circuit 123, and also supplies a select signal to the selector 126.

  The timing adjustment circuit 125 is configured such that a plurality of inverters are connected in series, and an output is extracted from a predetermined number of inverters among the plurality of inverters, and the capture signal supplied from the sequential circuit 123 is output to the inverters. It outputs as a plurality of delay signals that are delayed by different times by utilizing the individual delay times. In other words, the timing adjustment circuit 125 outputs the capture signal of logic “1” output from the sequential circuit 123 when the oscillation time of the ring oscillator 121 reaches the time corresponding to the set value to a plurality of delays having different delay times. Output as a signal. There is also a capture signal of logic "1" which is directly supplied from the sequential circuit 123 to the selector 126 without being delayed. The timing adjustment circuit 125 is a delay circuit for adjusting the timing of setting the logic of the capture signal Cap to “1” in units smaller than the oscillation cycle of the ring oscillator 121, and can be omitted.

  The selector 126 selects one capture signal selected by the select signal supplied from the register 124 from among a plurality of capture signals supplied from the timing adjustment circuit 125 and having different delay times, and sets it as a final capture signal Cap. Output. The capture signal Cap is supplied to the register 112 shown in FIG. 2 as a holding control signal.

  FIG. 4 is a circuit diagram of a second embodiment of the response acquisition timing generation circuit which constitutes another part of the unique information generation device according to the present invention. 4, a response acquisition timing generation circuit 12B of this embodiment corresponds to the response acquisition timing generation circuit 12 of FIG. 1, and n delay circuits 128-1 each composed of a plurality of inverters connected in series, 128-2, 128-3,..., 128-n, a selector 129, and a register 130, which are connected to the PL-PUF circuit 11 from the same power supply voltage source (not shown). Operates with the power supply voltage. Further, the n delay circuits 128-1, 128-2, 128-3,..., 128-n are connected in series to form an n-stage delay circuit group. , And outputs the PL-PUF start trigger signal delayed by τ, 2τ, 3τ,..., Nτ (where τ is a delay circuit 128-1, 128-2, 128-3, ..., 128-n individual delay times). Therefore, the delay circuit 128-n at the final stage outputs the PL-PUF start trigger signal delayed by nτ. The delay times of the delay circuits 128-1, 128-2, 128-3,..., 128-n may not be the same τ but may be different. The delay circuits 128-1, 128-2, 128-3,..., 128-n form the delay circuit section in the present invention.

  The selector 129 is supplied in parallel with n delayed PL-PUF activation trigger signals delayed by the delay circuits 128-1, 128-2, 128-3,..., 128-n and having different delay times. , One delay signal selected by the select signal from the register 130 among these delay signals is output as the capture signal Cap. The selector 129 and the register 130 make up the selection circuit unit in the present invention. The capture signal Cap is supplied to the register 112 shown in FIG. 2 as a holding control signal. The PL-PUF activation trigger signal supplied to the delay circuit 128-1 in the first stage is also supplied as it is to the selectors in the core circuits C1 to C128 in the PL-PUF circuit 11 in FIG. The oscillation operation of the PL-PUF circuit 11 is controlled.

  In the register 130, the logic of the capture signal Cap output from the selector 129 becomes “1” from the time when the select signal SEL becomes logic “1” (that is, the time when the PL-PUF circuit 11 starts the oscillation operation). From the delay circuits 128-1, 128-2, 128-3,..., 128-n so that the delay time up to the time (that is, the response holding time of the PL-PUF circuit 11) becomes an arbitrary set time. A value for causing the selector 129 to select one delay signal of the delay signals is stored in advance.

Next, the operation of the exemplary embodiment of the unique information generating apparatus according to the present invention will be described in detail with reference to the schematic configuration diagram of FIG. 1, the circuit diagrams of FIGS. 2 to 4, and the flowchart of FIG.
First, in the initial state, the PL-PUF activation signal is set to the low level (hereinafter, logic “0”), which causes the response acquisition timing generation circuit 12 (the delay circuit 122 of FIG. 3 and the input of FIG. 4) to output the signal. The select signal SEL fetched is set to logic "0", and the capture signal Cap output from the selector 126 of FIG. 3 and the selector 129 of FIG. 4 is also set to logic "0" (step ST1 of FIG. 5). ). As a result, all the selectors such as C127 and C128 in the core circuits C1 to C128 forming the PL-PUF circuit 11 are set to the input selection state of the terminal 0, and the ring circuit is not formed, so that the oscillation operation is stopped. ..

  Subsequently, the 128-bit challenge C[128:1] having a desired value is input to the PL-PUF circuit 11 (step ST2 in FIG. 5). At this time, the selectors in the core circuits C1 to C128 configuring the PL-PUF circuit 11 are in a state of selectively outputting the challenge C[128:1] that is input, as can be seen from FIG. , The response R[128:1] supplied to the register 112 in the PL-PUF circuit 11 is equal to the challenge C[128:1].

  Then, the PL-PUF activation trigger signal is set to logic "1" (step ST3 in FIG. 5). As a result, the ring oscillator 121 in the response acquisition timing generation circuit 12A shown in FIG. 3 forms a feedback loop and starts an oscillating operation, and the select signal SEL extracted from the delay circuit 122 is set to logic "1" after a predetermined time. (Step ST3 of FIG. 5). Further, in the response acquisition timing generation circuit 12B shown in FIG. 4, the select signal SEL taken out from the input is immediately set to the logic "1" (step ST3 in FIG. 5). On the other hand, when the PL-PUF activation trigger signal is set to logic "1", all the selectors in the core circuits C1 to C128 configuring the PL-PUF circuit 11 in FIG. Since the ring circuit is configured by the PL-PUF circuit 11, the PL-PUF circuit 11 starts the oscillation operation. During this oscillation operation, the response R[128:1] output from the core circuits C1 to C128 continues to change depending on the variation in the physical characteristics of the circuit and the oscillation time.

  In the case where the response acquisition timing generation circuit 12 is the timing acquisition generation circuit 12A shown in FIG. 3, when the oscillation time of the ring oscillator 121 reaches an arbitrary set value held in the register 124, the sequential circuit 123 causes the logic “1”. Signal (capture signal) is directly output to the selector 126, and is output to the selector 126 through the timing adjustment circuit 125 as a plurality of delay signals having different delay times. The selector 126 selects one of the input non-delayed capture signal and the plurality of delayed capture signals according to an arbitrary set value held in the register 124, and finally captures the logic "1". The signal is output as the signal Cap (step ST4 in FIG. 5).

  Further, when the response acquisition timing generation circuit 12 is the timing acquisition generation circuit 12B shown in FIG. 4, after the oscillation operation of the PL-PUF circuit 11 is started, the delay circuits 128-1, 128-2, 128-3,... .. Of 128-n, the output of a predetermined delay circuit that outputs a delay signal of logic "1" just when the oscillation time reaches an arbitrary set value based on the value held in the register 130 The delay signal is selected by the selector 129 and output as the final capture signal Cap of logic "1" (step ST4 in FIG. 5).

  The register 112 in the PL-PUF circuit 11 shown in FIG. 2 has a response acquisition timing generation circuit 12 (12A in FIG. 3 and 12B in FIG. 4) at the time when an arbitrary set time elapses as described above after the oscillation operation starts. Is supplied with a capture signal Cap of logic "1" as a holding control signal, holds the response R[128:1] output from the core circuits C1 to C128 at the time of input, and holds the held 128-bit response R [128:1] is output as a response signal (step ST5 in FIG. 5).

  The 128-bit response signal is unique information indicating a 128-bit challenge C[128:1], a variation in the physical characteristics of the PL-PUF circuit 11, and a value depending on the oscillation time. Further, the value of the 128-bit response signal is always the same value in the case of the same PL-PUF circuit 11 if the challenge has the same value and the same oscillation time (reproducibility). On the other hand, since the physical characteristics are different between a plurality of PL-PUF circuits having the same circuit configuration but different, even if they are operated for the same oscillation time for the same challenge, random values (uniqueness) are obtained. Sex).

  According to the unique information generation device 10 of the present embodiment and the example as described above, the power supply voltage of the response acquisition timing generation circuit 12 (12A, 12B) is supplied from the same power supply voltage source 13 as the power supply voltage of the PL-PUF circuit 11. Therefore, even if the power supply voltage of the PL-PUF circuit 11 fluctuates, the change of the PUF response is suppressed, and the error rate of the generated unique information can be reduced. The effect will be described in detail with reference to the timing chart of FIG.

Conventionally, when the PL-PUF circuit is in the normal state, the select signal SEL becomes the logic "1" at time t ₀ as shown in FIG. 6C, so that the oscillation operation is started at time t ₀ and a certain time elapses. At time t ₁ , the capture signal Cap changes from the logic “0” to the logic “1” as shown in FIG. 7C, and the response output from the PL-PUF circuit schematically shown in FIG. It is assumed that, out of R, a response having a value r ₈ is output as a response. In this case, in the conventional PL-PUF circuit, the select signal SEL becomes logic “1” at time t ₀ as shown in FIG. 6D, and even if the power supply voltage fluctuates after starting the oscillation operation, the time t has elapsed. _{At 1} , the capture signal Cap changes from logic "0" to logic "1" as shown in FIG.

That is, conventionally, since the response acquisition timing is generated by the external clock, the response acquisition timing is constant regardless of the fluctuation of the power supply voltage. However, since the oscillation speed of the PL-PUF circuit slows (or increases) due to the fluctuation of the power supply voltage, the response R output from the PL-PUF circuit is, for example, as shown schematically in FIG. Unlike the conventional method, the value of the response obtained at the time when the capture signal Cap changes to the logic "1" at time t ₁ becomes a value r ₇ different from the normal time, as shown in FIG.

On the other hand, in the present invention, when PL-PUF circuit is normal, starts the oscillation operation select signal SEL is at time t ₀ at time t ₀ by a logic "1" as shown in FIG. 6 (E) , The capture signal Cap changes from the logic “0” to the logic “1” at time t ₁ when an arbitrary set time elapses, and the PL-PUF schematically shown in FIG. Among the responses R output from the circuit, the response with the value r ₈ is output as a response as in the conventional case. Also in the present invention, as shown in FIG. 6(F), the PL-PUF circuit starts the oscillating operation when the select signal SEL becomes the logic “1” at time t ₀ , and when the power supply voltage fluctuates, it becomes different from the conventional one. Similarly, the oscillation speed becomes slower (or faster), and the response R output from the PL-PUF circuit is different from that at the normal time, as schematically shown in FIG. 6B, for example.

However, in the present invention, since the power supply voltages of the PL-PUF circuit 11 and the response acquisition timing generation circuit 12 are the same, when the power supply voltage of the PL-PUF circuit 11 changes, the power supply voltage of the response acquisition timing generation circuit 12 also changes. The time fluctuates by the same amount, and as a result, the time at which the capture signal Cap changes from the logic "0" to the logic "1" becomes t ₂ as shown in FIG. 6(F), which is later than the conventional t ₁ . This time t ₂ is the time at which the response R having the value r ₈ is output from the PL-PUF circuit in which the power supply voltage has changed. Therefore, in the present invention, even if the response R output from the PL-PUF circuit in which the power supply voltage has changed is different from the normal time shown schematically in FIG. It can be acquired as a response output, and a change in PUF response can be suppressed. That is, in the present invention, the unique information can be generated with good reproducibility even if the power supply voltage of the PL-PUF circuit 11 changes.

  FIG. 7 is a characteristic diagram showing an example of the power supply voltage fluctuation vs. output error rate of the PL-PUF circuit of the present invention and an example of the power supply voltage fluctuation vs. output error rate of the conventional PL-PUF circuit. In the same figure, the solid line I shows the characteristic of an example of the power supply voltage fluctuation vs. output error rate of the PL-PUF circuit of the present invention, and the error rate of the response output when the power supply voltage fluctuates by 100 mV is 4.6%. This is the error rate of the response output when the power supply voltage fluctuates by 10 mV in the characteristic (same as the characteristic of FIG. 8) of the example of the power supply voltage variation vs. output error rate of the conventional PL-PUF circuit shown by the solid line II in FIG. Compared with 46.5%, it shows that the error rate is significantly improved.

  The present invention is not limited to the above-described embodiments and examples. For example, the feedback polynomial of the PL-PUF circuit may be a polynomial other than that of the examples, and the number of bits of challenge and response may be the examples. It is not limited to. The information generation circuit in the present invention has a circuit configuration imitating the structure of a linear feedback shift register, and this circuit configuration is not limited to the strict linear feedback shift register (LFSR) shown in FIG. A feedback shift register having a non-linear configuration by slightly modifying the configuration from that of FIG. 2 is also included.

  The unique information generating apparatus according to the present invention is mounted on an electronic device, generates unique information of the electronic device, and compares the unique information with unique information of an original value registered in advance to use for authenticity determination of the electronic device. be able to. The unique information generated by the unique information generating device according to the present invention can also be used as a secret key or random number in the security system.

10 Unique Information Generation Device 11 PL-PUF Circuits 12, 12A, 12B Response Acquisition Timing Generation Circuit 13 Power Supply Voltage Source 100, C1-C128 Core Circuits 101, 126, 129, S127, S128 Selector 102, I127, I128 Inverter 111 Oscillation Circuit 112, 124, 130 Register 121 Ring oscillator 122, 128-1 to 128-n Delay circuit 123 Sequential circuit 125 Timing adjustment circuit 200 A1, A2, A3 Adder

Claims (3)

An information generating circuit that generates and outputs a plurality of unique bits of hard-to-copy unique information based on the physical characteristics of the constituent circuit elements by a circuit configuration imitating the structure of a linear feedback shift register
A timing signal generation circuit that supplies first and second timing signals to the information generation circuit;
And a power supply voltage source for supplying the information generating circuit and the supply voltage for operating the hand Common to said timing signal generating circuit,
The information generation circuit,
An oscillation circuit simulating the structure of the linear feedback shift register that controls the start and stop of the oscillation operation by the first timing signal and that oscillates and outputs the plurality of bits of unique information during the operation.
A register that holds the plurality of bits of unique information output from the oscillation circuit when the second timing signal is input,
The timing signal generation circuit,
A first timing signal generation unit that receives the activation trigger signal of the information generation circuit and outputs the activation trigger signal as it is as the first timing signal;
A delay circuit section that generates delay signals having a plurality of different delay times based on the activation trigger signal and outputs the delay signals in parallel;
From the plurality of delay signals output in parallel from the delay circuit section, one delay signal having a delay time corresponding to the arbitrary set time after the output of the first timing signal is selected to select the first delay signal. And a second timing signal generation unit having a selection circuit unit that outputs the second timing signal . The second timing signal generator is
The unique information generation device according to claim 1, further comprising a register that holds a selection value for selecting a delayed signal having one of the delay times .   3. The unique information generation device according to claim 1, wherein the information generation circuit is a circuit based on PL-PUF technology.

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