CN108766383B

CN108766383B - Shift register unit, shift register circuit and display device

Info

Publication number: CN108766383B
Application number: CN201810602101.4A
Authority: CN
Inventors: 许卓; 吴海龙; 白雅杰; 朱海鹏; 冉敏; 梁鹏; 张智
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Priority date: 2018-06-12
Filing date: 2018-06-12
Publication date: 2020-12-11
Anticipated expiration: 2038-06-12
Also published as: CN108766383A; US11443706B2; US20220005428A1; WO2019237889A1

Abstract

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, and a display device. The shift register unit comprises an input module, a compensation module, an output module, a pull-down control module, a pull-down module and a reset module. In the working process of the pixel driving circuit, if the pixel corresponding to the shift register unit has abnormal display, a compensation signal can be provided to the pull-up node through the compensation module according to the specific condition of the abnormal display so as to change the voltage of the pull-up node and further change the delay time of the waveform of the signal passing through the switching element in the output module connected with the pull-up node, namely, the delay time of the scanning signal output by the shift register unit is improved, the charging rate of the pixel corresponding to the shift register unit is further improved, the uniformity of the pixel display brightness is ensured, and the adverse phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like are eliminated.

Description

Shift register unit, shift register circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, and a display device.

Background

Since liquid crystal displays (liquid crystal displays) have the advantages of low radiation, small size, and low power consumption, they have gradually replaced conventional cathode ray tube displays (cathode ray tube displays), and thus are widely used in information products such as notebook computers, Personal Digital Assistants (PDAs), flat panel televisions, or mobile phones. The conventional lcd displays images by driving pixels on a panel using an external gate driving chip, but in order to reduce the number of elements and reduce the manufacturing cost, it has been developed recently to directly fabricate a shift register unit structure on a display panel, i.e., to supply scan signals to a plurality of rows of pixels through a shift register circuit including a plurality of shift register units.

At present, a shift register circuit including a plurality of cascaded shift register units is often used to supply scan signals to pixels of different rows. However, in the working process of a plurality of cascaded shift register units, due to factors such as long-time work, ambient temperature, instability of manufacturing process, or large resistance of a scanning line between a certain stage of shift register unit and a corresponding pixel, delay time (i.e., rising time and falling time) of scanning signals output by the output end of a part of shift register units or scanning signals transmitted to the pixels is different, so that charging rates of pixels in each row are different to some extent, and further, display brightness of pixels in each row is different, and adverse phenomena such as an X-thin dark line, an H-BLOCK (horizontal direction BLOCK display), a horizontal stripe and the like occur.

Therefore, it is desirable to provide a shift register unit or a shift register circuit that can ensure that the charging rates of the pixels in each row are the same.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a shift register unit, a shift register circuit, and a display device, which overcome at least some of the problems that the delay time (i.e., the rise time and the fall time) of the scanning signal output by the shift register unit or the scanning signal transmitted to the pixels is different, so that the charging rate of the pixels in each row is different, and the display brightness of the pixels in each row is different.

According to an aspect of the present disclosure, there is provided a shift register unit including:

the input module is connected with a pull-up node and used for providing signals to the pull-up node;

the compensation module is connected with the pull-up node and used for transmitting a compensation signal to the pull-up node;

the output module is connected with a pull-up node, an output end and a first phase clock signal end and used for responding to a signal of the pull-up node and transmitting a signal of the first phase clock signal end to the output end;

the pull-down control module is connected with a first signal end, a pull-down control node, a pull-down node, the pull-up node and a second signal end, and is used for responding to a signal of the pull-up node, transmitting a signal of the second signal end to the pull-down node and the pull-down control node, and responding to a signal of the first signal end, and transmitting a signal of the first signal end to the pull-down control node and the pull-down node;

the pull-down module is connected with the pull-up node, the pull-down node, the output end and the second signal end and is used for responding to the signal of the pull-down node and transmitting the signal of the second signal end to the pull-up node and the output end;

the reset module is connected with the reset end, the second signal end and the pull-up node and used for responding to the signal of the reset end to transmit the signal of the second signal end to the pull-up node.

In one exemplary embodiment of the present disclosure,

the input module includes:

the control end and the first end of the first switch element are connected with the input end, and the second end of the first switch element is connected with the pull-up node;

the compensation module includes:

and a control end of the tenth switching element is connected with the input end, a first end of the tenth switching element is connected with the compensation end, and a second end of the tenth switching element is connected with the pull-up node.

In one exemplary embodiment of the present disclosure,

the input module includes:

the control end of the first switch element is connected with the input end, the first end of the first switch element is connected with the first signal end, and the second end of the first switch element is connected with the pull-up node;

the compensation module includes:

In one exemplary embodiment of the present disclosure,

the input module includes:

the compensation module includes:

a tenth switching element having a first terminal connected to the compensation terminal and a second terminal connected to the pull-up node;

an eleventh switching element, wherein a control terminal and a first terminal are connected to the second phase clock signal terminal, and a second terminal is connected to the control terminal of the tenth switching element;

and a control end of the twelfth switching element is connected with the pull-down node, a first end of the twelfth switching element is connected with a second end of the eleventh switching element, and a second end of the twelfth switching element is connected with the second signal end.

In one exemplary embodiment of the present disclosure,

the input module includes:

the compensation module includes:

a tenth switching element having a first end connected to the compensation end;

an eleventh switching element, wherein a control terminal and a first terminal are connected to the compensation terminal, and a second terminal is connected to the control terminal of the tenth switching element;

a first end of the second storage capacitor is connected with the second end of the tenth switching element, and a second end of the second storage capacitor is connected with the pull-up node;

In one exemplary embodiment of the present disclosure,

the output module includes:

a control end of the second switch element is connected with the pull-up node, a first end of the second switch element is connected with the first phase clock signal end, and a second end of the second switch element is connected with the output end;

the first end of the first storage capacitor is connected with the pull-up node, and the second end of the first storage capacitor is connected with the output end;

the pull-down control module includes:

a third switching element having a control terminal and a first terminal connected to the first signal terminal, and a second terminal connected to the pull-down control node;

a fourth switching element having a control terminal connected to the pull-down control node, a first terminal connected to the first signal terminal, and a second terminal connected to the pull-down node;

a fifth switching element having a control terminal connected to the pull-up node, a first terminal connected to the pull-down control node, and a second terminal connected to the second signal terminal;

a control end of the sixth switching element is connected with the pull-up node, a first end of the sixth switching element is connected with the pull-down node, and a second end of the sixth switching element is connected with the second signal end;

the pull-down module includes:

a control end of the seventh switching element is connected with the pull-down node, a first end of the seventh switching element is connected with the pull-up node, and a second end of the seventh switching element is connected with the second signal end;

a control end of the eighth switching element is connected with the pull-down node, a first end of the eighth switching element is connected with the output end, and a second end of the eighth switching element is connected with the second signal end;

the reset module includes:

and a control end of the ninth switch element is connected with the reset end, a first end of the ninth switch element is connected with the pull-up node, and a second end of the ninth switch element is connected with the second signal end.

According to an aspect of the present disclosure, there is provided a shift register circuit including:

n cascaded shift register cells as claimed in any one of the preceding claims, wherein:

and respectively providing signals for the second signal ends of the shift register units according to the display states of the pixels corresponding to the shift register units at all levels.

In an exemplary embodiment of the present disclosure, the pull-down module of the shift register unit includes a first pull-down module and a second pull-down module, and the second signal terminal includes a first sub-signal terminal and a second sub-signal terminal; wherein:

the first pull-down module is connected to the pull-down node, the output end and the first sub-signal end, and is configured to respond to a signal of the pull-down node to transmit a signal of the first sub-signal end to the output end;

the second pull-down module is connected to a pull-down node, a pull-up node and the second sub-signal end, and is configured to respond to a signal of the pull-down node to transmit a signal of the second sub-signal end to the pull-up node;

and the reset module of the shift register unit is connected with a reset end, the pull-up node and the second sub-signal end and is used for responding to a signal of the reset end to transmit a signal of the second sub-signal end to the pull-up node.

In an exemplary embodiment of the present disclosure, the signals of the first sub-signal terminal include first to nth signals;

the providing signals for the second signal ends of the shift register units according to the display states of the pixels corresponding to the shift register units at each level respectively comprises:

according to the cascade relation of the shift register units, the first sub-signal ends of the shift register units from the first stage to the Nth stage receive the Nth signal to the first signal in sequence;

and according to the cascade relation of the shift register units, the second sub-signal ends of the shift register units from the first pole to the Nth stage all receive the first signal.

In an exemplary embodiment of the present disclosure, the signals of the first sub-signal terminal include first to N + 1-th signals;

according to the cascade relation of the shift register units, the first sub-signal ends of the shift register units from the first stage to the Nth stage receive the (N + 1) th signal to the second signal in sequence;

and according to the cascade relation of the shift register units, the second sub-signal ends of the shift register units from the first stage to the Nth stage sequentially receive the Nth signal to the first signal.

According to an aspect of the present disclosure, there is provided a display device including the shift register unit according to any one of the above and the shift register circuit according to any one of the above.

The present disclosure provides a shift register unit, a shift register circuit and a display device. The shift register unit comprises an input module, a compensation module, an output module, a pull-down control module, a pull-down module and a reset module. In the working process of the pixel driving circuit, if the pixel corresponding to the shift register unit has abnormal display, a compensation signal can be provided to the pull-up node through the compensation module according to the specific condition of the abnormal display so as to change the voltage of the pull-up node and further change the delay time of the waveform of the signal passing through the switching element in the output module connected with the pull-up node, namely, the delay time of the scanning signal output by the shift register unit is improved, the charging rate of the pixel corresponding to the shift register unit is further improved, the uniformity of the pixel display brightness is ensured, and the adverse phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like are eliminated. The shift register circuit comprises N cascaded shift register units, and provides signals for the second signal ends of the shift register units according to the display states of the pixels corresponding to the shift register units. In the working process of the shift register circuit, if the pixels corresponding to a certain level or several levels of shift register units are abnormal in display, differentiated signals are respectively provided to the second signal ends of the corresponding shift register units according to the abnormal display condition of each pixel so as to respectively change the holding voltage of each corresponding pixel, so that the difference of the charging rates of the corresponding pixels is compensated, the uniformity of the display brightness of the pixels is further ensured, and the adverse phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like are eliminated.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

fig. 1 is a first schematic structural diagram of a shift register unit provided in an exemplary embodiment of the present disclosure;

fig. 2 is a schematic diagram of a relationship between a signal of a gate of a switching element and a delay time of a signal passing through the switching element provided in an exemplary embodiment of the present disclosure;

fig. 3 is a schematic structural diagram ii of a shift register unit provided in an exemplary embodiment of the present disclosure;

fig. 4 is a schematic structural diagram three of a shift register unit provided in an exemplary embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a shift register unit provided in an exemplary embodiment of the present disclosure;

FIG. 6 is a schematic illustration of compensation for an X-thin dark line provided in an exemplary embodiment of the present disclosure;

FIG. 7 is a schematic illustration of compensation for an H-BLOCK provided in an exemplary embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating a relationship between a leakage current of a switching element and an off signal in a scan signal output from a shift register unit provided in an exemplary embodiment of the present disclosure;

FIG. 9 is a first schematic diagram of a shift register circuit provided in an exemplary embodiment of the present disclosure;

FIG. 10 is a schematic illustration of compensating for horizontal striations provided in an exemplary embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a shift register unit provided in an exemplary embodiment of the present disclosure;

fig. 12 is a second schematic structural diagram of a shift register circuit provided in an exemplary embodiment of the present disclosure;

fig. 13 is a schematic structural diagram three of a shift register circuit provided in an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

The present exemplary embodiment provides a shift register unit, which may include: input module, compensation module, output module, pull-down control module, pull-down module, reset module, wherein:

In the working process of the pixel driving circuit, if the pixel corresponding to the shift register unit has abnormal display, a compensation signal can be provided to the pull-up node through the compensation module according to the specific condition of the abnormal display so as to change the voltage of the pull-up node and further change the delay time of the waveform of the signal passing through the switching element in the output module connected with the pull-up node, namely, the delay time of the scanning signal output by the shift register unit is improved, the charging rate of the pixel corresponding to the shift register unit is further improved, the uniformity of the pixel display brightness is ensured, and the adverse phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like are eliminated.

Next, the specific structure and connection mode of each block in the shift register unit will be described in detail in four embodiments below.

The first embodiment is as follows: as shown in fig. 1, the shift register unit may include: the input module 110, the compensation module 120, the output module 130, the pull-down control module 140, the pull-down module 150, and the reset module 160, wherein:

the input module 110 may include:

a first switch element T1, having a control terminal and a first terminal connected to the INPUT terminal INPUT, and a second terminal connected to the pull-up node PU;

the compensation module 120 may include:

and a tenth switching element T10, having a control terminal connected to the INPUT terminal INPUT, a first terminal connected to the compensation terminal fed, and a second terminal connected to the pull-up node PU.

The output module 130 may include:

a second switch element T2, having a control end connected to the pull-up node PU, a first end connected to the first phase clock signal end CKL, and a second end connected to the output end G;

a first storage capacitor C1, having a first end connected to the pull-up node PU and a second end connected to the output terminal G;

the pull-down control module 140 may include:

a third switching element T3 having a control terminal and a first terminal connected to the first signal terminal VGH, and a second terminal connected to the pull-down control node PDCN;

a fourth switching element T4, having a control end connected to the pull-down control node PDCN, a first end connected to the first signal end VGH, and a second end connected to the pull-down node PD;

a fifth switching element T5, having a control terminal connected to the pull-up node PU, a first terminal connected to the pull-down control node PDCN, and a second terminal connected to the second signal terminal VGL;

a sixth switching element T6, having a control end connected to the pull-up node PU, a first end connected to the pull-down node PD, and a second end connected to the second signal end VGL;

the pull-down module 150 may include:

a seventh switching element T7, having a control end connected to the pull-down node PD, a first end connected to the pull-up node PU, and a second end connected to the second signal end VGL;

an eighth switching element T8, having a control end connected to the pull-down node PD, a first end connected to the output end G, and a second end connected to the second signal end VGL;

the reset module 160 may include:

and a ninth switching element T9 having a control terminal connected to the RESET terminal RESET, a first terminal connected to the pull-up node PU, and a second terminal connected to the second signal terminal VGL.

In the present exemplary embodiment, the first to tenth switching elements (T1 to T10) may correspond to first to tenth switching transistors, respectively, each having a control terminal, a first terminal, and a second terminal. Specifically, the control terminal of each switching transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or the control terminal of each switching transistor may be a gate, the first terminal may be a drain, and the second terminal may be a source. In addition, each of the switching transistors may be an enhancement transistor or a depletion transistor, and this exemplary embodiment is not particularly limited thereto. In addition, each switch transistor may be an N-type transistor or a P-type transistor, which is not particularly limited in the present exemplary embodiment.

The operation of the shift register unit in fig. 1 will be described below by taking an example in which all the switching elements are N-type thin film transistors. Since the switching elements are all N-type thin film transistors, on signals of all the switching elements are high level signals, and off signals of all the switching elements are low level signals.

In the pixel holding stage, the signal of the RESET terminal RESET, the signal of the INPUT terminal INPUT, and the signal of the second signal terminal VGL are all low level signals, and the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are all high level signals. At this time, the third switching element T3 is turned on by the signal of the first signal terminal VGH, and transmits the signal of the first signal terminal VGH to the pull-down control node PDCN. The fourth switching element T4 is turned on by the pull-down control node PDCN, and transmits the signal of the first signal terminal VGH to the pull-down node PD. The seventh switching element T7 and the eighth switching element T8 are turned on by a signal transmitted to the first signal terminal VGH of the pull-down node PD, and transmit a signal of the second signal terminal VGL to the pull-up node PU and the output terminal G, so that the pull-up node PU and the output terminal G are continuously denoised by the signal of the second signal terminal VGL. Meanwhile, the fifth switching element T5, the sixth switching element T6, and the second switching element T2 are turned off by a signal transmitted to the second signal terminal VGL of the pull-up node PU, the first switching element T1 and the tenth switching element T10 are turned off by a signal of the INPUT terminal INPUT, and the ninth switching element T9 is turned off by a signal of the RESET terminal RESET. At this time, the scan signal output by the output terminal G is a signal of the second signal terminal VGL, i.e. a low level signal.

In the charging phase, the signal of the INPUT terminal INPUT and the signal of the first signal terminal VGH are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the first phase clock signal terminal CKL are all low level signals. At this time, the first switching element T1 and the tenth switching element T10 are turned on by the signal of the INPUT terminal INPUT, the signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed are transmitted to the pull-up node PU, the signal of the pull-up node PU is a parallel signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed at this time, the first storage capacitor C1 is charged by the parallel signal, the fifth switching element T5 and the sixth switching element T6 are turned on by the signal of the pull-up node PU, the signal of the second signal terminal VGL is transmitted to the pull-down node PD and the pull-down control node PDCN, and the seventh switching element T7 and the eighth switching element T8 are turned off by the signal of the second signal terminal VGL transmitted to the pull-down node PD. The second switch element T2 is turned on by the signal of the pull-up node PU to transmit the signal of the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is a low level signal, the scan signal output by the output terminal G is a low level signal.

In the bootstrap phase, the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the INPUT terminal INPUT are all low level signals. The second switching element T2 is turned on by the first storage capacitor C1, that is, the second switching element T2 is turned on by the parallel signal of the signal stored at the INPUT terminal INPUT of the first storage capacitor C1 and the compensation signal at the compensation terminal fed, and transmits the signal at the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is a high level signal, the output scan signal of the output terminal G is a high level signal. In addition, the potential of the pull-up node PU is bootstrapped from the parallel signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed to the sum of the parallel signal of the INPUT terminal INPUT and the signal of the compensation terminal fed and the signal of the first phase clock signal terminal CKL due to the bootstrap action of the first storage capacitor C1.

In the RESET phase, the signal of the RESET terminal RESET and the signal of the first signal terminal VGH are high level signals, and the signal of the second signal terminal VGL, the signal of the INPUT terminal INPUT and the signal of the first phase clock signal terminal CKL are all low level signals. The ninth switching element T9 is turned on by a signal of the RESET terminal RESET, transmits a signal of the second signal terminal VGL to the pull-up node PU, RESETs the pull-up node PU, and since the signal of the pull-up node PU is a low level signal at this time, the fifth switching element T5 and the sixth switching element T6 are turned off, the third switching element T3 and the fourth switching element T4 are turned on by the signal of the first signal terminal VGH, transmits the signal of the first signal terminal VGH to the pull-down node PD, the seventh switching element T7 and the eighth switching element T8 are turned on by the signal of the first signal terminal VGH, transmits the signal of the second signal terminal VGL to the pull-up node PU and the output terminal G, and at this time, the scan signal output by the output terminal G is a signal of the second signal terminal VGL, that is, a low level signal.

Fig. 2 shows the relationship between the delay time of the signal Vg passing through the gate (i.e., control terminal) of the switching element and the signal Vg of the gate of the switching element when the switching element is an N-type transistor, and it can be seen from the figure that the larger the signal Vg passing through the gate (i.e., control terminal) of the switching element, the shorter the delay time of the signal output through the switching element. Further, the charging rate applied to the pixel is higher as the delay time of the signal is shorter, and the charging rate applied to the pixel is lower as the delay time of the signal is longer. Therefore, the charging rate applied to the pixel is higher as the signal Vg at the gate (i.e., control terminal) of the switching element is larger, and the charging rate applied to the pixel is lower as the signal Vg at the gate (i.e., control terminal) of the switching element is smaller.

Based on the above principle, in the process of the shift register unit operating, in the charging phase, the signal transmitted to the pull-up node PU and the signal stored in the first storage capacitor C1 are parallel signals of the signal at the INPUT terminal INPUT and the compensation signal at the compensation terminal fed. Based on this, when the pixel corresponding to the shift register unit has no display abnormality, the compensation signal at the compensation terminal fed is set to be the same as the signal at the INPUT terminal INPUT, so that in the charging phase, the signal at the pull-up node PU and the signal stored in the first storage capacitor C1 are still the signal at the INPUT terminal INPUT (i.e. the signal at the control terminal of the second switch element T2 is still the signal at the INPUT terminal INPUT), and it is ensured that the added compensation module 120 does not affect the shift register unit. When the pixel corresponding to the shift register unit has display abnormality, the magnitude of the compensation signal INPUT by the compensation terminal FEED is determined according to the specific situation of the display abnormality, so that in the charging stage, the parallel signal of the signal transmitted to the pull-up node PU and the INPUT terminal INPUT stored in the first storage capacitor C1 and the compensation signal of the compensation terminal FEED is changed, and further the delay time of the signal of the first phase clock signal terminal CKL passing through the second switch element T2 is changed, that is, the delay time of the scanning signal output by the shift register unit is improved, and further the charging rate of the pixel corresponding to the shift register unit is improved, thereby ensuring the uniformity of the pixel display brightness, and eliminating the bad phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like.

Example two: as shown in fig. 3, the shift register unit may include: the input module 110, the compensation module 120, the output module 130, the pull-down control module 140, the pull-down module 150, and the reset module 160, wherein:

the input module 110 may include:

a first switch element T1, having a control terminal connected to the INPUT terminal INPUT, a first terminal connected to the first signal terminal VGH, and a second terminal connected to the pull-up node PU;

the compensation module 120 may include:

The output module 130 may include:

the pull-down control module 140 may include:

the pull-down module 150 may include:

the reset module 160 may include:

The operation of the shift register unit in fig. 3 will be described below by taking an example in which all the switching elements are N-type thin film transistors. Since the switching elements are all N-type thin film transistors, on signals of all the switching elements are high level signals, and off signals of all the switching elements are low level signals.

In the pixel holding stage, the signal of the RESET terminal RESET, the signal of the INPUT terminal INPUT, and the signal of the second signal terminal VGL are all low level signals, and the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are all high level signals. At this time, the third switching element T3 is turned on by the signal of the first signal terminal VGH, and transmits the signal of the first signal terminal VGH to the pull-down control node PDCN. The fourth switching element T4 is turned on by the pull-down control node PDCN, and transmits the signal of the first signal terminal VGH to the pull-down node PD. The seventh switching element T7 and the eighth switching element T8 are turned on by a signal transmitted to the first signal terminal VGH of the pull-down node PD, and transmit a signal of the second signal terminal VGL to the pull-up node PU and the output terminal G, so that the pull-up node PU and the output terminal G are continuously denoised by the signal of the second signal terminal VGL. Meanwhile, the fifth switching element T5, the sixth switching element T6, and the second switching element T2 are turned off by a signal transmitted to the second signal terminal VGL of the pull-up node PU, the first switching element T1 and the tenth switching element T10 are turned off by a signal of the INPUT terminal INPUT, and the ninth switching element T9 is turned off by a signal of the RESET terminal RESET. It should be noted that the scan signal output by the output terminal G is a signal of the second signal terminal VGL, i.e. a low level signal.

In the charging phase, the signal of the INPUT terminal INPUT and the signal of the first signal terminal VGH are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the first phase clock signal terminal CKL are all low level signals. At this time, the first switching element T1 and the tenth switching element T10 are turned on by the signal of the INPUT terminal INPUT, the signal of the first signal terminal VGH and the compensation signal of the compensation terminal fed are transmitted to the pull-up node PU, the signal of the pull-up node PU is a parallel signal of the first signal terminal VGH and the compensation signal of the compensation terminal fed at this time, the first storage capacitor C1 is charged by the parallel signal, the fifth switching element T5 and the sixth switching element T6 are turned on by the pull-up node PU, the signal of the second signal terminal VGL is transmitted to the pull-down node PD and the pull-down control node PDCN, and the seventh switching element T7 and the eighth switching element T8 are turned off by the signal of the second signal terminal VGL transmitted to the pull-down node PD. The second switch element T2 is turned on by the signal of the pull-up node PU to transmit the signal of the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is a low level signal, the scan signal output by the output terminal G is a low level signal.

In the bootstrap phase, the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are both high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the INPUT terminal INPUT are all low level signals. The second switching element T2 is turned on by the first storage capacitor C1, that is, the second switching element T2 is turned on by the parallel signal of the signal stored in the first signal terminal VGH of the first storage capacitor C1 and the compensation signal at the compensation terminal fed, and transmits the signal at the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is at a high level, the output scan signal of the output terminal G is at a high level. In addition, the potential of the pull-up node PU is bootstrapped from the parallel signal of the first signal terminal VGH and the compensation signal of the compensation terminal fed to the sum of the parallel signal of the first signal terminal VGH and the compensation signal of the compensation terminal fed and the signal of the first phase clock signal terminal CKL due to the bootstrap action of the first storage capacitor C1.

In the RESET phase, the signal of the RESET terminal RESET and the signal of the first signal terminal VGH are high level signals, and the signal of the second signal terminal VGL, the signal of the INPUT terminal INPUT and the signal of the first phase clock signal terminal CKL are all low level signals. The ninth switching element T9 is turned on by a signal of the RESET terminal RESET, transmits a signal of the second signal terminal VGL to the pull-up node PU, RESETs the pull-up node PU, and since the signal of the pull-up node PU is a low level signal at this time, the fifth switching element T5 and the sixth switching element T6 are turned off, the third switching element T3 and the fourth switching element T4 are turned on by the signal of the first signal terminal VGH, transmits the signal of the first signal terminal VGH to the pull-down node PD, the seventh switching element T7 and the eighth switching element T8 are turned on by the signal of the first signal terminal VGH, transmits the signal of the second signal terminal VGL to the pull-up node PU and the output terminal G, and at this time, the scan signal output by the output terminal G is a low level signal.

Since the relationship between the signal of the gate (i.e., the control terminal) of the switching element and the charging rate of the pixel is described above, it is not described herein again.

Based on the above principle, in the process of the shift register unit operating, in the charging phase, the signal transmitted to the pull-up node PU and the signal stored in the first storage capacitor C1 are parallel signals of the signal of the first signal terminal VGH and the compensation signal output by the compensation terminal fed. Based on this, when the display abnormality does not occur in the pixel corresponding to the shift register unit, the compensation signal at the compensation terminal fed is set to be the same as the signal at the first signal terminal VGH, so that in the charging phase, the signal at the pull-up node PU and the signal stored in the first storage capacitor C1 are still the signal at the first signal terminal VGH (i.e., the signal at the control terminal of the second switch element T2 is still the signal at the first signal terminal VGH), and it is ensured that the newly added compensation module 120 does not affect the shift register unit. When the pixel corresponding to the shift register unit has display abnormality, the magnitude of the compensation signal input by the compensation terminal FEED is determined according to the specific situation of the display abnormality, so that in the charging stage, the parallel signal of the signal transmitted to the pull-up node PU and the signal stored to the first signal terminal VGH of the first storage capacitor C1 and the compensation signal of the compensation terminal FEED is changed, and further the delay time of the signal passing through the first phase clock signal terminal CKL of the second switch element T2 is changed, that is, the delay time of the scanning signal output by the shift register unit is improved, and further the charging rate of the pixel corresponding to the shift register unit is improved, thereby ensuring the uniformity of the pixel display brightness, and eliminating the bad phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like.

Example three: as shown in fig. 4, the shift register unit may include: the input module 110, the compensation module 120, the output module 130, the pull-down control module 140, the pull-down module 150, and the reset module 160, wherein:

the input module 110 may include:

the compensation module 120 may include:

a tenth switching element T10 having a first terminal connected to the compensation terminal fed and a second terminal connected to the pull-up node PU;

an eleventh switching element T11 having a control terminal and a first terminal connected to the second phase clock signal terminal CKLB, and a second terminal connected to the control terminal of the tenth switching element T10;

and a twelfth switching element T12 having a control terminal connected to the pull-down node PD, a first terminal connected to the second terminal of the eleventh switching element T11, and a second terminal connected to the second signal terminal VGL.

The output module 130 may include:

the pull-down control module 140 may include:

the pull-down module 150 may include:

the reset module 160 may include:

In the present exemplary embodiment, the first to twelfth switching elements (T1 to T12) may correspond to first to twelfth switching transistors, respectively, each having a control terminal, a first terminal, and a second terminal. Specifically, the control terminal of each switching transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or the control terminal of each switching transistor may be a gate, the first terminal may be a drain, and the second terminal may be a source. In addition, each of the switching transistors may be an enhancement transistor or a depletion transistor, and this exemplary embodiment is not particularly limited thereto. In addition, each switch transistor may be an N-type transistor or a P-type transistor, which is not particularly limited in the present exemplary embodiment.

The operation of the shift register unit in fig. 4 will be described below by taking an example in which all the switching elements are N-type thin film transistors. Since the switching elements are all N-type thin film transistors, on signals of all the switching elements are high level signals, and off signals of all the switching elements are low level signals. It should be noted that the signal of the first phase clock signal terminal CKL and the signal of the second phase clock signal terminal CKLB are the same-frequency reverse signals.

In the pixel holding stage, the signal of the RESET terminal RESET, the signal of the INPUT terminal INPUT, the signal of the second signal terminal VGL, and the signal of the second phase clock signal terminal CKLB are all low level signals, and the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are all high level signals. At this time, the third switching element T3 is turned on by the signal of the first signal terminal VGH, and transmits the signal of the first signal terminal VGH to the pull-down control node PDCN. The fourth switching element T4 is turned on by the pull-down control node PDCN, and transmits the signal of the first signal terminal VGH to the pull-down node PD. The seventh switching element T7, the eighth switching element T8, and the twelfth switching element T12 are turned on by the signal transmitted to the first signal terminal VGH of the pull-down node PD, and the signal of the second signal terminal VGL is transmitted to the pull-up node PU, the output terminal G, and the control terminal of the tenth switching element T10, so that the noise of the pull-up node PU and the output terminal G is continuously reduced by the signal of the second signal terminal VGL. Meanwhile, the fifth switching element T5, the sixth switching element T6, and the second switching element T2 are turned off by a signal transmitted to the second signal terminal VGL of the pull-up node PU, the first switching element T1 is turned off by a signal of the INPUT terminal INPUT, the ninth switching element T9 is turned off by a signal of the RESET terminal RESET, and the eleventh switching element T11 is turned off by a signal of the second phase clock signal terminal CKLB. Since the signal of the second signal terminal VGL is at a low level, the scan signal output by the output terminal G is a low level signal.

In the charging phase, the signal of the INPUT terminal INPUT, the signal of the first signal terminal VGH, and the signal of the second phase clock signal terminal CKLB are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL, and the signal of the first phase clock signal terminal CKL are all low level signals. At this time, the first switching element T1 is turned on, the signal of the INPUT terminal INPUT is transmitted to the pull-up node PU, and at the same time, the eleventh switching element is turned on by the signal of the second phase clock signal terminal CKLB, the signal of the second phase clock signal terminal CKLB is transmitted to the control terminal of the tenth switching element T10, so as to turn on the tenth switching element T10, the compensation signal of the compensation terminal fed is transmitted to the pull-up node PU, and the signal of the pull-up node PU is a parallel signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed, and the first storage capacitor C1 is charged by the parallel signal. The fifth and sixth switching elements T5 and T6 are turned on by the pull-up node PU, transmit the signal of the second signal terminal VGL to the pull-down node PD and the pull-down control node PDCN, and the seventh switching element T7, the eighth switching element T8, and the twelfth switching element T12 are turned off by the signal transmitted to the second signal terminal VGL of the pull-down node PD. The second switch element T2 is turned on by the signal of the pull-up node PU to transmit the signal of the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is a low level signal, the scan signal output by the output terminal G is a low level signal.

In the bootstrap phase, the signal of the first signal terminal VGH, the signal of the first phase clock signal terminal CKL, the signal of the RESET terminal RESET, the signal of the second signal terminal VGL, the signal of the INPUT terminal INPUT, and the signal of the second phase clock signal terminal CKLB are all low level signals. The second switching element T2 is turned on by the first storage capacitor C1, that is, the second switching element T2 is turned on by the parallel signal of the signal stored at the INPUT terminal INPUT of the first storage capacitor C1 and the compensation signal at the compensation terminal fed, and transmits the signal at the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is at a high level, the output scan signal of the output terminal G is at a high level. In addition, the potential of the pull-up node PU is bootstrapped from the parallel signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed to the sum of the parallel signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed and the signal of the first phase clock signal terminal CKL due to the bootstrap action of the first storage capacitor C1.

In the RESET phase, the signal of the RESET terminal RESET, the signal of the first signal terminal VGH, and the signal of the second phase clock signal terminal CKLB are all high level signals, and the signal of the second signal terminal VGL, the signal of the INPUT terminal INPUT, and the signal of the first phase clock signal terminal CKL are all low level signals. The ninth switching element T9 is turned on by a signal of the RESET terminal RESET, transmits a signal of the second signal terminal VGL to the pull-up node PU, RESETs the pull-up node PU, and since the signal of the pull-up node PU is a low level signal at this time, the fifth switching element T5 and the sixth switching element T6 are turned off, the third switching element T3 and the fourth switching element T4 are turned on by the signal of the first signal terminal VGH, transmits the signal of the first signal terminal VGH to the pull-down node PD, the seventh switching element T7, the eighth switching element T8, and the twelfth switching element T12 are turned on by the signal of the first signal terminal VGH, transmits the signal of the second signal terminal VGL to the pull-up node PU, the output terminal G, and the control terminal of the tenth switching element T10, and at this time, the scan signal output by the output terminal G is a low level signal.

Example four: as shown in fig. 5, the shift register unit may include: the input module 110, the compensation module 120, the output module 130, the pull-down control module 140, the pull-down module 150, and the reset module 160, wherein:

the input module 110 may include:

the compensation module 120 may include:

a tenth switching element T10 having a first terminal connected to the compensation terminal fed;

an eleventh switching element T11 having a control terminal connected to the compensation terminal fed at a first terminal and a control terminal connected to the control terminal of the tenth switching element T10 at a second terminal;

a second storage capacitor C2 having a first terminal connected to the second terminal of the tenth switching element T10 and a second terminal connected to the pull-up node PU;

The output module 130 may include:

the pull-down control module 140 may include:

the pull-down module 150 may include:

the reset module 160 may include:

The operation of the shift register unit in fig. 5 will be described below by taking an example in which all the switching elements are N-type thin film transistors. Since the switching elements are all N-type thin film transistors, on signals of all the switching elements are high level signals, and off signals of all the switching elements are low level signals.

In the pixel holding stage, the signal of the RESET terminal RESET, the signal of the INPUT terminal INPUT, and the signal of the second signal terminal VGL are all low level signals, and the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are all high level signals. At this time, the third switching element T3 is turned on by the signal of the first signal terminal VGH, and transmits the signal of the first signal terminal VGH to the pull-down control node PDCN. The fourth switching element T4 is turned on by the pull-down control node PDCN, and transmits the signal of the first signal terminal VGH to the pull-down node PD. The seventh switching element T7, the eighth switching element T8, and the twelfth switching element T12 are turned on by the signal transmitted to the first signal terminal VGH of the pull-down node PD, and the signal of the second signal terminal VGL is transmitted to the pull-up node PU, the output terminal G, and the control terminal of the tenth switching element T10, so that the noise of the pull-up node PU and the output terminal G is continuously reduced by the signal of the second signal terminal VGL, and the tenth switching element T10 is turned off. Meanwhile, the fifth switching element T5, the sixth switching element T6, and the second switching element T2 are turned off by a signal transmitted to the second signal terminal VGL of the pull-up node PU, the first switching element T1 is turned off by a signal of the INPUT terminal INPUT, the ninth switching element T9 is turned off by the RESET terminal RESET, and the eleventh switching element T11 is turned on by a compensation signal of the compensation terminal fed. Since the signal of the second signal terminal VGL is at a low level at this time, the scan signal output by the output terminal G is a low level signal.

In the charging phase, the signal of the INPUT terminal INPUT and the signal of the first signal terminal VGH are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the first phase clock signal terminal CKL are all low level signals. At this time, the first switching element T1 is turned on, the signal of the INPUT terminal INPUT is transmitted to the pull-up node PU and charges the first storage capacitor C1, and at the same time, the eleventh switching element is turned on by the compensation signal of the compensation terminal fed, and transmits the compensation signal of the compensation terminal fed to the control terminal of the tenth switching element T10 to turn on the tenth switching element T10 and transmit the compensation signal of the compensation terminal fed to the first terminal of the second storage capacitor C2, and at this time, the signal of the INPUT terminal INPUT and the compensation signal of the compensation terminal fed charge the second storage capacitor C2. The fifth and sixth switching elements T5 and T6 are turned on by the pull-up node PU, transmit the signal of the second signal terminal VGL to the pull-down node PD and the pull-down control node PDCN, and the seventh switching element T7, the eighth switching element T8, and the twelfth switching element T12 are turned off by the signal transmitted to the second signal terminal VGL of the pull-down node PD. The second switch element T2 is turned on by the signal of the pull-up node PU to transmit the signal of the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is a low level signal, the scan signal output by the output terminal G is a low level signal.

In the bootstrap phase, the signal of the first signal terminal VGH and the signal of the first phase clock signal terminal CKL are high level signals, and the signal of the RESET terminal RESET, the signal of the second signal terminal VGL and the signal of the INPUT terminal INPUT are all low level signals. If the compensation signal at the compensation terminal fed is consistent with the signal at the charging stage, i.e. no change occurs, the second switch element T2 is turned on by the first storage capacitor C1, i.e. the second switch element T2 is turned on by the signal stored at the INPUT terminal INPUT of the first storage capacitor C1 at the charging stage, so as to transmit the signal at the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is at a high level, the output scan signal of the output terminal G is at a high level. In addition, the potential of the pull-up node PU is bootstrapped from the signal of the INPUT terminal INPUT to the sum of the signal of the INPUT terminal INPUT and the signal of the first phase clock signal terminal CKL due to the bootstrap action of the first storage capacitor C1. If the compensation signal of the compensation terminal fed is not consistent with the signal in the charging phase, that is, if the compensation signal of the compensation terminal fed is changed, the variation of the compensation signal of the compensation terminal fed is bootstrapped to the pull-up node PU due to the bootstrap effect of the second storage capacitor C2, and at this time, the signal of the pull-up node PU becomes the sum of the signal of the INPUT terminal INPUT and the variation of the compensation signal of the compensation terminal fed. At this time, the second switching element T2 is turned on by the sum of the variation of the INPUT signal and the compensation signal, and transmits the signal of the first phase clock signal terminal CKL to the output terminal G. Since the signal of the first phase clock signal terminal CKL is at a high level, the output scan signal of the output terminal G is at a high level. In addition, the potential of the pull-up node PU is bootstrapped from the sum of the signal of the INPUT terminal INPUT and the variation of the compensation signal of the compensation terminal fed to the sum of the signal of the INPUT terminal INPUT, the variation of the compensation signal of the compensation terminal fed, and the signal of the first phase clock signal terminal CKL due to the bootstrap action of the first storage capacitor C1.

In the RESET phase, the signal of the RESET terminal RESET and the signal of the first signal terminal VGH are both high level signals, and the signal of the second signal terminal VGL, the signal of the INPUT terminal INPUT and the signal of the first phase clock signal terminal CKL are all low level signals. The ninth switching element is turned on by a signal of the RESET terminal RESET, the signal of the second signal terminal VGL is transmitted to the pull-up node PU, the pull-up node PU is RESET, since the signal of the pull-up node PU is a low level signal at this time, the fifth switching element T5 and the sixth switching element T6 are turned off, the third switching element T3 and the fourth switching element T4 are turned on by the signal of the first signal terminal VGH, the signal of the first signal terminal VGH is transmitted to the pull-down node PD, the seventh switching element T7, the eighth switching element T8 and the twelfth switching element T12 are turned on by the signal of the first signal terminal VGH, the signal of the second signal terminal VGL is transmitted to the pull-up node PU, the output terminal G and the control terminal of the tenth switching element T10, and at this time, the scan signal output by the output terminal G is a low level signal.

Based on the above principle, in the process of the operation of the shift register unit, when the pixel corresponding to the shift register unit does not have display abnormality, the compensation signal of the compensation terminal fed may be set to be the same as the signal of the INPUT terminal INPUT, and the signal is kept unchanged, so that in the charging stage, the signal of the pull-up node PU is the signal of the INPUT terminal INPUT, and at the bootstrapping stage, the signal of the pull-up node PU is the sum of the signal of the INPUT terminal INPUT and the signal of the first phase clock signal terminal CKL, thereby ensuring that the newly added compensation module 120 does not affect the shift register unit. When the pixel corresponding to the shift register unit has display abnormality, in the bootstrap stage, the variation of the compensation signal INPUT by the compensation terminal fed may be determined according to the specific condition of the display abnormality, and the magnitude of the compensation signal INPUT by the compensation terminal fed may be changed according to the variation to bootstrap the variation to the pull-up node PU through the second storage capacitor, so that the signal of the pull-up node is the sum of the signal of the INPUT terminal INPUT and the variation of the compensation signal of the compensation terminal fed, that is, the signal of the pull-up node PU is changed, and further the delay time of the signal of the first phase clock signal terminal CKL through the second switching element T2 is changed, that is, the delay time of the scan signal output by the shift register unit is improved, and further the charging rate of the pixel corresponding to the shift register unit is improved, the uniformity of the pixel display luminance is ensured, and the X-thin dark line is eliminated, H-BLOCK, horizontal striations, etc.

It should be noted that, in the fourth embodiment, no matter how much or how much the specific value of the compensation signal of the compensation terminal fed is changed, the value thereof must be ensured to turn on the eleventh switching element.

It should be noted that, in the above embodiments, all the switching elements are N-type thin film transistors; however, those skilled in the art can easily obtain a shift register unit in which all the switching elements are P-type thin film transistors according to the shift register unit provided in the present disclosure, and since all the switching elements are P-type thin film transistors, the on signals of all the switching elements are low level. The adoption of the all-P type thin film transistor has the following advantages: for example, strong noise suppression; for example, low level is easy to realize in charge management because of low level conduction; for example, the P-type thin film transistor has simple manufacturing process and relatively low price; such as better stability of the P-type thin film transistor, etc.

Of course, the shift register unit provided in the present disclosure may also be changed to a CMOS (Complementary Metal Oxide Semiconductor) circuit, etc., and is not limited to the shift register unit provided in this embodiment, and is not described herein again.

In summary, the charging rate of the pixel corresponding to the shift register unit can be adjusted by adjusting the signal of the pull-up node in the shift register unit. Specifically, for bright stripes, and the switching elements in the shift register unit are all N-type transistors, the delay time of the scanning signal can be increased by reducing the signal of the pull-up node in the shift register unit, and then the charging rate of the pixel corresponding to the scanning signal is reduced, so that the brightness of the pixel is reduced, and the bright stripes are eliminated; for dark fringes, the delay time of scanning signals can be reduced by increasing signals of pull-up nodes in the shift register unit, and further the charging rate of pixels corresponding to the delay time is increased, so that the brightness of the pixels is improved, and the dark fringes are eliminated. It should be noted that, for the shift register unit whose switching elements are P-type transistors, the adjustment principle is the same as that of the shift register unit whose switching elements are N-type transistors, and therefore, the details are not described here.

A schematic diagram of the compensation of the X-thin dark line is shown in fig. 6. The display panel 600 before compensation in fig. 6 has three regions, respectively: the normal area 601, the first dark stripe 602, and the second dark stripe 603, wherein the second dark stripe 603 has a lower brightness than the first dark stripe 602. Next, a process of removing dark fringes will be described by taking an example in which all the switching elements in the shift register unit corresponding to the pixels in the display panel are N-type transistors. The high level of the signal at the first phase clock signal terminal is VH. For the first dark fringe 602, the signal of the pull-up node VPU2 in the shift register unit corresponding to the pixel in the first dark fringe 602 in the charging phase can be set to VH2 through the compensation terminal, and VH2 is larger than the signal VH1 in the charging phase of the pull-up node VPU1 in the shift register unit corresponding to the pixel in the normal area 601, meanwhile, in the bootstrapping phase, the signal of the pull-up node VPU2 in the shift register unit corresponding to the pixel in the first dark fringe 602 is bootstrapped to VH2+ VH under the effect of the signal of the first phase clock signal terminal, so as to reduce the delay time of the scan signal 620 output by the shift register unit corresponding to the pixel in the first dark fringe 602, increase the charging rate of the pixel in the first dark fringe 602, and increase the brightness of the first dark fringe 602, so as to eliminate the first dark fringe 602. For the second dark fringe 603, the signal of the pull-up node VPU3 in the shift register unit corresponding to the pixel in the second dark fringe 603 in the charging phase can be set to VH3 through the compensation terminal, and VH3 is larger than the signal VH2 in the charging phase of the pull-up node VPU2 in the shift register unit corresponding to the pixel in the first dark fringe 602, meanwhile, in the bootstrapping phase, the signal of the pull-up node VPU3 in the shift register unit corresponding to the pixel in the second dark fringe 603 is bootstrapped to VH3+ VH under the effect of the signal of the first phase clock signal terminal, so as to reduce the delay time of the scan signal 630 output by the shift register unit corresponding to the pixel in the second dark fringe 603, increase the charging rate of the pixel in the second dark fringe 603, and increase the luminance of the second dark fringe 603 to eliminate the second dark fringe 603. As can be seen from the compensated display panel 640, in the above manner, the first dark stripe 602 and the second dark stripe 603 in the display panel 600 before compensation are all eliminated.

A schematic diagram of the compensation of H-BLOCK is shown in fig. 7. The phenomenon of poor H-Block means that the brightness of different display areas is different. The display panel 700 before compensation in fig. 7 has two regions, respectively: bright area 701, dark area 702. Next, a process of removing the H-BLOCK will be described by taking N-type transistors as examples of the switching elements in the shift register unit corresponding to the pixels in the display panel. The high level of the signal at the first phase clock signal terminal is VH. For the bright region 701, the signal of the pull-up node VPU1 in the shift register unit corresponding to the pixel in the bright region 701 in the charging stage can be reduced to VH1 through the compensation terminal, so as to increase the delay time of the scanning signal 710 output by the shift register unit corresponding to the pixel in the bright region 701, reduce the charging rate of the pixel in the bright region 701, and reduce the brightness of the bright region 701. For the dark area 702, the signal of the pull-up node VPU2 in the shift register unit corresponding to the pixel in the dark area 702 during the charging phase can be raised to VH2 through the compensation terminal, so as to reduce the delay time of the scan signal 720 output by the shift register unit corresponding to the pixel in the dark area 702, increase the charging rate of the pixel in the dark area 702, increase the brightness of the dark area 702, and further eliminate the H-Block defect. As can be seen from the compensated display panel 730, the H-Block defect in the display panel 700 before compensation is completely eliminated in the above manner.

The present exemplary embodiment provides a shift register circuit, which may include: n cascaded shift register cells as described above, wherein: and respectively providing signals for the second signal ends of the shift register units according to the display states of the pixels corresponding to the shift register units at all levels.

In the present exemplary embodiment, as shown in fig. 8, taking the switching element in the pixel as an example of an N-type transistor, the relationship between the drain current IDS of the switching element in the pixel and the off signal VL (i.e., a low level signal) in the scan signal output from the shift register unit is: the leakage current IDS of the switching element is minimized when the off signal VL (i.e., the low level signal) in the scan signal is-8V, and is increased when the off signal VL (i.e., the low level signal) in the scan signal is increased or decreased on the basis of-8V, and thus, the leakage current IDS of the switching element is minimized when the off signal VL in the scan signal is at a reference value (e.g., -8V described above), and is increased when the off signal VL in the scan signal is increased or decreased on the basis of the reference value. In addition, in the holding stage of the pixel, the variation of the holding voltage of the pixel has a positive correlation with the leakage current IDS of the switching element in the pixel, i.e., the larger the leakage current IDS of the switching element in the pixel, the larger the variation of the holding voltage of the pixel. As can be seen from the above, when the off signal VL in the scan signal is at the reference value, the amount of change in the holding voltage of the pixel is the smallest, and when the off signal VL in the scan signal is increased or decreased from the reference value, the amount of change in the holding voltage of the pixel is increased.

In addition, the holding voltage of each pixel can be changed by changing the variable quantity of the holding voltage of each pixel in the holding stage of the pixel, so that the difference of the charging rates of the pixels is compensated, the uniformity of the display brightness of the pixel is ensured, and the bad phenomena of X-thin dark lines, H-BLOCK, horizontal stripes and the like are eliminated.

Therefore, in summary, by adjusting the turn-off signal in the scanning signal corresponding to each pixel, the variation of the holding voltage corresponding to each pixel in the holding stage is changed, and the holding voltage of each pixel is changed according to the variation of the holding voltage of each pixel, so as to compensate the difference of the charging rates of the pixels, thereby ensuring the uniformity of the display brightness of the pixels, and eliminating the bad phenomena such as the X-thin dark line, the H-BLOCK, the horizontal stripes, and the like.

Based on the above principle, since the signal at the second signal terminal of each stage of the shift register unit is the turn-off signal in the output scanning signal, in the exemplary embodiment, the signal at the second signal terminal of each stage of the shift register unit is determined according to the display state of each pixel, and is input to the second signal terminal of each stage of the shift register unit, so as to change the variation of the holding voltage of each pixel in the holding stage through the signal, and further change the holding voltage of each pixel, thereby compensating the difference of the charging rates of the pixels, ensuring the uniformity of the pixel display brightness, and eliminating the adverse phenomena such as X-thin dark lines, H-BLOCK, horizontal stripes, and the like.

For example, fig. 9 shows a shift register circuit, which includes 8 cascaded shift register units, and in the figure, the second signal terminals VGL of the first stage shift register unit to eighth stage gate-driven circuits GOA1 to GOA8 sequentially receive the eighth signal to first signals VL8 to VL 1. When a pixel is abnormal in display, the holding voltage of the pixel can be changed by adjusting the signal of the second signal terminal VGL of the shift register unit GOA corresponding to the pixel, so as to eliminate the display abnormality.

A schematic illustration of the compensation of horizontal striations is shown in fig. 10. Taking the example that the switching element in the pixel is an N-type transistor, the signal of the second signal terminal in the shift register unit corresponding to the pixel in the bright stripe is increased (for example, set to-5V) to increase the leakage current of the switching element in the pixel in the bright stripe, further increase the variation of the holding voltage of the pixel in the bright stripe, and reduce the holding voltage of the pixel in the bright stripe, and meanwhile, the signal of the second signal terminal in the shift register unit corresponding to the pixel in the dark stripe is set to a reference value (for example, set to-8V) to minimize the leakage current of the switching element in the pixel in the dark stripe, so that the variation of the holding voltage of the pixel in the dark stripe is minimized, further, each pixel has different holding voltages, so as to compensate for the difference of the charging rates, and thus eliminate the horizontal stripes.

The pull-down module of the shift register unit may include a first pull-down module and a second pull-down module, and the second signal terminal includes a first sub-signal terminal and a second sub-signal terminal; wherein: the first pull-down module is connected to the pull-down node, the output end and the first sub-signal end, and is configured to respond to a signal of the pull-down node to transmit a signal of the first sub-signal end to the output end; the second pull-down module is connected to a pull-down node, a pull-up node and the second sub-signal end, and is configured to respond to a signal of the pull-down node to transmit a signal of the second sub-signal end to the pull-up node; and the reset module of the shift register unit is connected with a reset end, the pull-up node and the second sub-signal end and is used for responding to a signal of the reset end to transmit a signal of the second sub-signal end to the pull-up node.

A shift register cell in which a pull-down module includes a first pull-down module and a second pull-down module is shown in fig. 11. As can be seen from the figure, the pull-down module 150 includes a first pull-down module 151 and a second pull-down module 152, wherein the first pull-down module 151 is connected to the pull-down node PD, the output terminal G and the first sub-signal terminal VGL1, and is configured to transmit the signal of the first sub-signal terminal VGL1 to the output terminal G in response to the signal of the pull-down node PD. The second pull-down module 152 is connected to a pull-down node PD, a pull-up node PU, and the second sub-signal terminal VGL2, and configured to transmit a signal of the second sub-signal terminal VGL2 to the pull-up node PU in response to a signal of the pull-down node PD. The RESET module 160 of the shift register unit is connected to a RESET terminal RESET, the pull-up node PU and the second sub-signal terminal VGL2, and configured to transmit a signal of the second sub-signal terminal VGL2 to the pull-up node PU in response to a signal of the RESET terminal RESET.

Based on the shift register unit including the first pull-down module and the second pull-down module, and the second signal terminal including the first sub-signal terminal and the second sub-signal terminal, the following two ways of respectively providing signals for the second signal terminal of each stage of the shift register unit according to the display state of the pixel corresponding to each stage of the shift register unit are included.

First, the signals of the first sub-signal terminal may include first to nth signals. On this basis, the mode of respectively providing signals for the second signal ends of the shift register units at each stage according to the display states of the pixels corresponding to the shift register units at each stage is as follows: according to the cascade relation of the shift register units, the first sub-signal ends of the shift register units from the first stage to the Nth stage receive the Nth signal to the first signal in sequence; and according to the cascade relation of the shift register units, the second sub-signal ends of the shift register units from the first stage to the Nth stage all receive the first signal.

In the present exemplary embodiment, specific numerical values of the first to nth signals may be set according to the display state of the corresponding pixels. As can be seen from the above connection manner, the voltage difference between the control terminal and the second terminal of the switch element (e.g., the second switch element T2 in fig. 11) connected to the pull-up node in the nth stage shift register unit in the off state is the difference between the signal of the second sub-signal terminal and the signal of the first sub-signal terminal. Taking the switching element as an N-type transistor as an example, when the first signal to the nth signal are gradually increased, the voltage difference between the control terminal and the second terminal of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth to 1 st stage shift register units in the off state is negative, the voltage difference between the control terminal and the second terminal of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth to 1 st stage shift register units in the off state is gradually decreased, and the leakage current of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth to 1 st stage shift register units in the off state is gradually increased but is smaller than the leakage current of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node when the same signal is input to the first and second sub-signal terminals The piece T2) leakage current in the off state.

Compared with the situation that the same signal is input into the first sub signal terminal and the second sub signal terminal, the problem that the transfer characteristic curve of the switch element connected with the pull-up node in the shift register unit is shifted to the left is solved by inputting different signals into the first sub signal terminal and the second sub signal terminal, the influence of the switch element connected with the pull-up node on the turn-off signal in the scanning signal output by the shift register unit is further reduced, and the accuracy of displaying abnormity is improved by adjusting the turn-off signal in the scanning signal.

Fig. 12 shows a shift register circuit comprising 8 cascaded shift register cells, wherein the pull-down modules of the shift register cells comprise a first pull-down module and a second pull-down module. As can be seen from the figure, the ends of the first sub-signals VGL1 of the shift register units GOA 1-GOA 8 of the first stage to the eighth stage sequentially receive the eighth signal to the first signals VL 8-VL 1; the second sub-signal terminals VGL2 of the shift register units GOA 1-GOA 8 of the first to eighth stages all receive the first signal VL 1.

Second, the signals of the first sub-signal terminal may include first to N +1 th signals. On this basis, the mode of respectively providing signals for the second signal ends of the shift register units at each stage according to the display states of the pixels corresponding to the shift register units at each stage is as follows: according to the cascade relation of the shift register units, the first sub-signal ends of the shift register units from the first stage to the Nth stage receive the (N + 1) th signal to the second signal in sequence; and according to the cascade relation of the shift register units, the second sub-signal ends of the shift register units from the first stage to the Nth stage sequentially receive the Nth signal to the first signal.

In the present exemplary embodiment, specific numerical values of the first to N +1 th signals may be set according to display states of the corresponding pixels. As can be seen from the above connection manner, the voltage difference between the control terminal and the second terminal of the switch element (e.g., the second switch element T2 in fig. 11) connected to the pull-up node in the nth stage shift register unit in the off state is the difference between the signal of the second sub-signal terminal and the signal of the first sub-signal terminal. Taking the switching elements as N-type transistors as an example, when the first signal to the first N +1 signal gradually increases and the difference between adjacent signals is equal, the voltage difference between the control terminal and the second terminal of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth stage shift register unit to the 1 st stage shift register unit in the off state is negative, the voltage difference between the control terminal and the second terminal of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth stage shift register unit to the 1 st stage shift register unit in the off state is the same, and the leakage current of the switching element (e.g., the second switching element T2 in fig. 11) connected to the pull-up node in the nth stage shift register unit to the 1 st stage shift register unit in the off state is the same but smaller than the leakage current of the switching element connected to the pull-up node when the same signal is input to the first sub signal terminal and the second sub signal terminal The leakage current of the switching element (e.g., the second switching element T2 in fig. 11) in the off state.

Compared with the method that the same signals are input to the first sub signal end and the second sub signal end in each stage of shift register unit, the influence of a switch element connected with a pull-up node on a turn-off signal in a scanning signal output by the shift register unit can be eliminated, the control capability of a shift register circuit is improved, the change relation of pixel brightness along with the turn-off signal in the scanning signal is simplified, and the accuracy of improving abnormal display according to the turn-off signal in the scanning signal is improved.

Fig. 13 shows a shift register circuit comprising 8 cascaded shift register cells, wherein the pull-down modules of the shift register cells comprise a first pull-down module and a second pull-down module. As can be seen from the figure, the first sub-signal VGL1 of the shift register units GOA 1-GOA 8 of the first to eighth stages receives the ninth to second signals VL 9-VL 2 in sequence; the second sub-signal terminal VGL2 of the first to eighth stages of the shift register units GOA 1-GOA 8 receives the eighth to first signals VL 8-VL 1 for a plurality of times.

The present exemplary embodiment also provides a display device, which may include the shift register unit described above and the shift register circuit described above. In the present exemplary embodiment, the display device includes a display area and a peripheral area. The shift register circuit may be disposed in a peripheral region of the display device, and the shift register circuit includes at least one shift register unit. On this basis, the display area of the display device may include a plurality of gate lines and a plurality of data lines that are staggered horizontally and vertically, and a plurality of pixel units defined by adjacent gate lines and adjacent data lines: the gate lines are used for transmitting scanning signals provided by the shift register circuit, and the data lines are used for transmitting data signals provided by the source driver. The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A shift register cell, comprising:

the compensation module is connected with the pull-up node and the compensation end and used for transmitting a compensation signal to the pull-up node;

the reset module is connected with a reset end, the second signal end and the pull-up node and used for responding to a signal of the reset end to transmit a signal of the second signal end to the pull-up node;

wherein the pull-down control module comprises:

and a control end of the sixth switching element is connected with the pull-up node, a first end of the sixth switching element is connected with the pull-down node, and a second end of the sixth switching element is connected with the second signal end.

2. The shift register cell of claim 1,

the input module includes:

the compensation module includes:

3. The shift register cell of claim 1,

the input module includes:

the compensation module includes:

4. The shift register cell of claim 1,

the input module includes:

the compensation module includes:

5. The shift register cell of claim 1,

the input module includes:

the compensation module includes:

a tenth switching element having a first end connected to the compensation end;

6. The shift register cell according to any one of claims 1 to 5,

the output module includes:

the pull-down module includes:

the reset module includes:

7. A shift register circuit, comprising:

the shift register cell of any one of claims 1 to 6, wherein:

8. The shift register circuit according to claim 7, wherein the pull-down blocks of the shift register unit include a first pull-down block and a second pull-down block, and the second signal terminal includes a first sub-signal terminal and a second sub-signal terminal; wherein:

9. The shift register circuit according to claim 8, wherein the signals of the first sub-signal terminal include first to nth signals;

10. The shift register circuit according to claim 8, wherein the signals of the first sub-signal terminal include first to N + 1-th signals;

11. A display device comprising the shift register circuit according to any one of claims 7 to 10.