CN108470680B - Method of making a semiconductor structure - Google Patents

Abstract

The invention discloses a fabrication method of a semiconductor structure. The method for fabricating a semiconductor structure provided by the present invention includes: forming a first-type well and a second-type well, and gates respectively located on the first-type well and the second-type well; performing a first ion implantation to form a first-type well an implantation region; a first mask layer is formed on the first type well and on the gate of the second type well and a second ion implantation is performed to form a second implantation region; on the second type well and the first A second mask layer is formed on the gate of the type well and a third ion implantation is performed, so that the first implantation region in the first type well is transformed into a third implantation region and a fourth implantation region is formed. Therefore, at least two layers of LDD masks and corresponding at least two processes can be saved, which can save costs, optimize the manufacturing process, and shorten the production cycle.

Description

Method of making a semiconductor structure

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for fabricating a semiconductor structure.

Background technique

Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS for short) is a circuit structure in which two devices, NMOS transistor and PMOS transistor, are used at the same time in integrated circuit design, and are usually paired. Because the static power consumption of the CMOS circuit is very small and the circuit structure is simple, it can be used in large-scale integrated circuits and ultra-large-scale integrated circuits.

With the development of semiconductor manufacturing technology in the direction of smaller gate channel size and lower applied voltage, the traditional CMOS structure controls the vertical electric field caused by source/drain bias voltage by controlling ion implantation. component, and reduce the number of electrons that can pass through and suppress the hot electron effect. However, current processes are often complex and need to be improved.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for fabricating a semiconductor structure, which can save production cost and shorten production cycle on the basis of improving MOS performance.

In order to solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor structure, comprising:

providing a front end structure formed with a first type well and a second type well, and gates on the first type well and the second type well, respectively;

performing a first ion implantation on the front-end structure to form first implantation regions on both sides of the gate in the first-type well and the second-type well, respectively;

A first mask layer is formed on the first type well and on the gate of the second type well, and a second ion implantation is performed on the second type well, and the gate is formed on both sides of the gate in the second type well In the second implantation region, the ions implanted for the first time are of the same type as the ions implanted in the second time;

removing the first mask layer;

A second mask layer is formed on the second type well and on the gate of the first type well, and a third ion implantation is performed on the first type well, so that the first implantation region in the first type well transforming into a third implantation region, and forming a fourth implantation region on both sides of the gate in the first type well, wherein the ions implanted for the first time and the ions implanted for the third time are of different types;

The second mask layer is removed.

Optionally, for the method for fabricating the semiconductor structure, the first type well is an N well, and the second type well is a P well.

Optionally, for the manufacturing method of the semiconductor structure, the thickness of the second mask layer on the gate of the N-well is smaller than the thickness of the first mask layer on the gate of the P-well.

所述N阱的栅极上的第二掩膜层厚度为

Optionally, for the manufacturing method of the semiconductor structure, the thickness of the first mask layer on the gate of the P well is

The thickness of the second mask layer on the gate of the N well is

Optionally, for the fabrication method of the semiconductor structure, the doping concentration and the implantation depth of the second implantation region are greater than the doping concentration and implantation depth of the first implantation region; the doping concentration and implantation depth of the fourth implantation region are The impurity concentration and the implantation depth are greater than those of the third implantation region.

Optionally, for the fabrication method of the semiconductor structure, the first ion implantation is a general implantation of N-type ions.

Optionally, for the method for fabricating the semiconductor structure, the second ion implantation is N-type ion implantation, and the third ion implantation is P-type ion implantation.

Optionally, for the manufacturing method of the semiconductor structure, the angle of the third ion implantation is an included angle of 30°-60° with the normal direction of the upper surface of the front-end structure.

Optionally, for the fabrication method of the semiconductor structure, after the first ion implantation is performed on the front-end structure to form first implantation regions on both sides of the gate in the first-type well and the second-type well respectively ; forming a first mask layer on the gates of the first type well and the second type well, and before performing the second ion implantation on the second type well, further comprising:

Gate spacers are formed on both sides of the gate.

Optionally, for the manufacturing method of the semiconductor structure, the thickness of the gate spacer on the gate side of the first-type well is smaller than the thickness of the gate spacer on the gate side of the second-type well.

Optionally, for the fabrication method of the semiconductor structure, the thickness of the gate spacer on the gate side of the second type well is 90 nm-110 nm, and the thickness of the gate spacer on the gate side of the first type well is 80nm-90nm.

Optionally, for the fabrication method of the semiconductor structure, the front-end structure further includes a gate oxide layer, the gate oxide layer is located on the first type well and the second type well, and the gate is located on the on the gate oxide.

Optionally, for the manufacturing method of the semiconductor structure, the thickness of the gate oxide layer is

Optionally, for the fabrication method of the semiconductor structure, after the front end structure is provided, and before the first ion implantation is performed on the front end structure, the method further includes:

The gate is subjected to rapid thermal oxidation treatment.

Optionally, for the manufacturing method of the semiconductor structure, after removing the second mask layer, the method further includes:

Carry out the annealing process.

The method for fabricating a semiconductor structure provided by the present invention includes: providing a front-end structure, the front-end structure is formed with a first type well and a second type well, and gates respectively located on the first type well and the second type well; The front-end structure is subjected to the first ion implantation to form first implantation regions on both sides of the gate in the first-type well and the second-type well respectively; on the first-type well and the gate of the second-type well A first mask layer is formed on the second type well, and a second ion implantation is performed on the second type well, and a second implantation region is formed on both sides of the gate in the second type well. The ion types of the secondary implants are the same; the first mask layer is removed; a second mask layer is formed on the second type well and on the gate of the first type well, and the first type well is For the third ion implantation, the first implanted region in the first type well is transformed into a third implantation region, and a fourth implantation region is formed on both sides of the gate in the first type well. The ions and The third implant is of a different ion type; the second mask layer is removed. Therefore, the first implantation region and the third implantation region as LDD can be formed by the first implantation and the third implantation. Compared with the prior art, at least two layers of LDD masks and corresponding at least two layers can be saved. It can be seen that the cost can be greatly saved, the production process can be optimized, and the production cycle can be shortened.

In addition, the adjustment of NMOS performance can be achieved through the first ion implantation and the second ion implantation; through the first ion implantation and the third ion implantation, and further combined with the thickness of the gate spacer, the thickness of the mask layer, and the The selection of the third ion implantation angle can adjust the performance of the PMOS, such as improving the leakage current of the MOS structure, so that the performance of the product can be guaranteed.

Description of drawings

1-6 are schematic diagrams of a fabrication process of a CMOS structure;

7 is a flowchart of a method for fabricating a semiconductor structure in an embodiment of the present invention;

8 is a schematic diagram of a front-end structure provided in an embodiment of the present invention;

9 is a schematic diagram of the first ion implantation in an embodiment of the present invention;

10 is a schematic diagram of forming a gate spacer according to an embodiment of the present invention;

11 is a schematic diagram of performing a second ion implantation in an embodiment of the present invention;

12 is a schematic diagram of performing a second ion implantation in an embodiment of the present invention;

13 is a schematic diagram of a semiconductor structure obtained in an embodiment of the present invention.

Detailed ways

The method for fabricating the semiconductor structure of the present invention will be described in more detail below with reference to the schematic diagrams, wherein the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the advantages of the present invention. Effect. Therefore, the following description should be construed as widely known to those skilled in the art and not as a limitation of the present invention.

The invention is described in more detail by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The inventors have found in long-term research that when the gate width is less than 2 μm, the vertical component of the electric field caused by the bias between the source and drain will be high enough to accelerate the electrons to tunnel through the thin oxide layer. This hot electron The leakage current caused by the effect will affect the performance of the transistor, and it will also cause reliability problems in the integrated circuit chip due to the electron trapping effect of the gate oxide layer.

Conventional LDD (Lightly Doped Drain) junctions are implemented using a low energy, low current ion implantation process. After deposition and etchback of the dielectric, sidewall spacers are formed on both sides of the polysilicon gate. High-current, low-energy ion implantation forms heavily doped source/drain, separated from the gate by sidewall spacers, thereby reducing the vertical component of the electric field caused by the source/drain bias and reducing the number of electrons that can pass through while suppressing the hot electron effect.

Please refer to FIG. 1-FIG. 6, which shows a method for fabricating a CMOS structure, including the following steps:

As shown in FIG. 1, a substrate 1 is provided, and a PMOS region and an NMOS region are formed by ion implantation. Specifically, the PMOS region includes an N well 2, and the NMOS region includes a P well 3, which is isolated by an isolation structure (STI) 4. A gate oxide layer 5 is also formed on the bottom 1 .

As shown in FIG. 2 , a gate 6 is formed, and then a photoresist 7 is formed to cover the N well 2 , exposing the P well 3 , and ion implantation is performed to obtain the LDD structure 8 .

As shown in FIG. 3 , the photoresist 7 is removed and a photoresist 9 is formed, covering the P well 3 , exposing the N well 2 , and performing ion implantation to obtain the LDD structure 10 .

As shown in FIG. 4 , the photoresist 9 is removed and spacers 11 are formed.

As shown in FIG. 5 , a mask layer 12 is formed to cover the gate structures (including the gate 16 and the sidewall spacers) on the N well 2 and the P well 3 , and ion implantation is performed to obtain the N-type heavily doped region 13 .

As shown in FIG. 6 , the mask layer 12 is removed, and the mask layer 14 is formed to cover the gate structure (including the gate 16 and the sidewall spacer) on the P well 3 and the N well 2, and ion implantation is performed to obtain the P-type heavy doping District 15.

When the pattern size is less than 0.18μm, the dose of LDD ion implantation is no longer a light implant, that is, source/drain extended ion implantation. At the same time, LDD is ion implantation in the selective area of the mask, and the number of masks required is 2 or 4 layers. For devices with large polysilicon gate CD (critical dimension) (eg ≥ 0.18 μm), if the input mask layer If the number is large, it will inevitably lead to higher cost and prolong the production cycle of the chip.

Therefore, the present invention provides a method for fabricating a semiconductor structure to improve this problem.

As shown in FIG. 7 , an embodiment of the present invention provides a method for fabricating a semiconductor structure, including:

Step S11, providing a front-end structure, the front-end structure is formed with a first-type well and a second-type well, and gates respectively located on the first-type well and the second-type well;

Step S12, performing a first ion implantation on the front-end structure to form a first implantation region on both sides of the gate in the first-type well and the second-type well, respectively;

Step S13, forming a first mask layer on the first type well and the gate of the second type well, and performing a second ion implantation on the second type well, and the gate in the second type well A second implantation region is formed on both sides, and the ions implanted in the first time are of the same type as the ions implanted in the second time;

Step S14, removing the first mask layer;

Step S15, forming a second mask layer on the second type well and the gate of the first type well, and performing a third ion implantation on the first type well, so that the first type well in the first type well is implanted. An implantation region is transformed into a third implantation region, and a fourth implantation region is formed on both sides of the gate in the first type well, and the ions implanted for the first time and the ions implanted for the third time are of different types;

Step S16, removing the second mask layer.

The above steps will be described in detail below with reference to FIGS. 8-13 .

As shown in FIG. 8, for step S11, a front-end structure is provided, the front-end structure is formed with a first-type well 101 and a second-type well 102, and gates located on the first-type well 101 and the second-type well 102, respectively 105.

Specifically, a substrate 100 may be provided, and the constituent material of the substrate 100 may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), or the like. As an example, in this embodiment, the substrate 100 is made of a single crystal silicon material. A buried layer (not shown in the figure) and the like may also be formed in the substrate 100 .

In addition, the substrate 100 is formed with a first type well 101 and a second type well 102 by ion implantation, and the first type well 101 and the second type well 102 may be isolated by an isolation structure (eg, STI) 103 .

Further, a gate oxide layer 104 is also formed on the substrate 100. For example, the gate oxide layer 104 can be formed through a furnace tube, and the thickness of the gate oxide layer 104 can be

The gate 105 may be made of polysilicon.

In the embodiment of the present invention, the first type well 101 is an N well and the second type well 102 is a P well as an example for description. On the basis of the following, those skilled in the art can also select the first type well 101 to be a P well and the second type well 102 to be an N well by changing the type of ion implantation. The comparison of the present invention is not particularly limited.

The provision of the above-mentioned front-end structure can be completed by using the existing technology. According to actual needs, the size of the implanted ions, such as the type, the concentration, and the thickness of the film layer, can be flexibly adjusted.

Referring to FIG. 9 , in step S12 , first ion implantation is performed on the front-end structure to form first implantation regions 106 on both sides of the gate in the N well 101 and the P well 102 , respectively.

Specifically, the first ion implantation is a general N-type ion implantation, that is, a mask-less full-surface implantation (Blanket LDDIMP). For example, the implanted ions may be phosphorus (P) ions, and the implantation concentration may be 2.2*10 ³ / cm ² -2.5*10 ³ /cm ² , with a depth of approx.

Preferably, in order to protect the gate during the first ion implantation, the gate 105 may be subjected to rapid thermal oxidation treatment after step S11 to form an oxide layer (not shown) to prevent ions The implantation causes damage to the gate 105 .

Please refer to FIG. 9 to FIG. 10 , in step S13 , a first mask layer 108 is formed on the N well 101 and the gate 105 of the P well 102 , and a second ion implantation is performed on the P well 102 . A second implantation region 109 is formed on both sides of the gate 105 in the P-well 102, and the ions implanted in the first time and the ions implanted in the second time are of the same type. This step is also the process of forming the NMOS.

Specifically, as shown in FIG. 10 , gate spacers 107 are first formed on both sides of the gate 105 . In order to help the present invention obtain better MOS performance, the gate spacers 107 on the N-well 101 and the P-well 102 can have different thicknesses (ie, the lateral widths shown in FIG. 10 ), so that the gate spacers 107 located in the N-well The thickness D1 of the gate spacer 107 on the gate 105 side of 101 is smaller than the thickness D2 of the gate spacer 107 on the gate 105 side of the P-well 102 . For example, the thickness D1 of the gate spacer 107 on the gate 105 side of the P well 102 is 90 nm-110 nm, such as 100 nm, and the thickness D2 of the gate spacer 107 on the gate 105 side of the N well 101 is 80 nm-90 nm, Such as 85nm and so on. The effect of this design will be discussed in detail in step S15.

例如可以是

等。在本实施例中，所述第一掩膜层108可以选择为光阻，以既能够实现离子注入的防护，又能够方便的去除。In this step, the first mask layer 108 may completely cover the N-well 101 (including the gate 105 and the gate spacer 107 ), and only cover the gate 105 and the gate spacer 107 above the P-well 102 . In order to obtain a better implantation effect, the thickness H1 of the first mask layer 108 at the P well 102 is

For example it could be

Wait. In this embodiment, the first mask layer 108 can be selected as a photoresist, so as to realize the protection of ion implantation and facilitate removal.

Further, in order to adjust the performance of the NMOS, the second ion implantation in this step may also have a certain angle (as shown in FIG. 11 ).

The second ion implantation is to implant N-type ions, such as phosphorus, arsenic, etc., the implantation concentration can be 2.8*10 ³ /cm ² -3.2*10 ³ /cm ² , and the depth is about

After the second ion implantation in this step, a second implantation region 109 may be formed in the P-well 102 as an N-type heavily doped region, and the doping concentration and implantation depth of the second implantation region 109 are greater than those of the first implantation region Doping concentration and implant depth of implant region 106 .

Step S14 is to remove the first mask layer 108 , which can be accomplished by conventional processes, such as ashing and cleaning.

Referring to FIG. 12, for step S15, a second mask layer 110 is formed on the P-well 102 and the gate 105 of the N-well 101, and a third ion implantation is performed on the N-well 101, so that the N-well 101 is implanted for the third time. The first implanted region 106 in 101 is transformed into a third implanted region 111, and a fourth implanted region 112 is formed on both sides of the gate 105 in the N-well 101. The first implanted ions and the third implanted ions are of the type different. This step is also the process of forming the PMOS.

In this embodiment, the second mask layer 110 can be selected as a photoresist, so as to realize the protection of ion implantation and to be easily removed.

It can be understood that the doping types of the LDD structures in the N well 101 and the P well 102 (ie, the first implantation region 106 and the third implantation region 111 ) are inconsistent, and the first ion implantation performed before has The first implantation region 106 is formed in the N well 101. Therefore, in this step, the first implantation region 106 in the N well 101 is neutralized by the third ion implantation, and then the first implantation region 106 is further transformed into the first implantation region 106. Three injection regions 111 .

In order to better achieve this purpose, as mentioned above, the gate spacer 107 at the N well 101 is thinner, thereby ensuring that the third ion implantation can affect the entire region where the first implantation region 106 is located.

In addition, the angle of the third ion implantation can also be adjusted, for example, the angle of the third ion implantation is an included angle θ of 30°-60°, such as 35°, with the normal direction of the upper surface of the front-end structure.

It can be understood that the above-mentioned conditions of the thickness of the gate spacer, the thickness of the mask layer and the injection angle can be selected or not selected according to actual needs, and multiple conditions can be used in combination.

如

等。由此降低对离子注入的遮挡区域，也能够实现较好的离子注入。Further, the thickness of the part of the second mask layer 110 located on the N-well 101 can be adjusted, so that the thickness of the second mask layer 110 on the gate 105 of the N-well 101 is smaller than that of the P-well The thickness of the first mask layer 108 on the gate 105 of 102 . For example, the thickness H2 of the second mask layer 110 on the gate 105 of the N-well 101 is

like

Wait. Thereby, the shielding area for ion implantation is reduced, and better ion implantation can also be achieved.

The third ion implantation is to implant P-type ions, such as boron, gallium, etc., the implantation concentration can be 1.5*10 ⁴ /cm ² -1.8*10 ⁴ /cm ² , and the depth is about

After the third ion implantation in this step, a third implantation region 111 is formed on the one hand, and a fourth implantation region 112 is also formed on the other hand, wherein the third implantation region 111 is an LDD structure, and the fourth implantation region 112 serves as N type heavily doped region, the doping concentration and implantation depth of the fourth implantation region 112 are greater than the doping concentration and implantation depth of the third implantation region 111 .

Step S16 is to remove the second mask layer 110 , which can be accomplished by conventional processes, such as ashing and cleaning. After removal, the structure shown in FIG. 13 can be obtained. In the case of the CMOS of the embodiment of the present invention, it includes a substrate 100, an N well 101 and a P well 102, and the N well 101 and the P well 102 are separated by an isolation structure 103 isolation, a third implantation region 111 and a fourth implantation region 112 are formed in the N well 101, a first implantation region 106 and a second implantation region 109 are formed in the P well 102, on the N well 101 and the P well 102 A gate oxide layer 104, a gate 105 and a gate spacer 107 are formed thereon.

Further, after removing the second mask layer, the method further includes: performing an annealing process, which may be completed by a conventional process.

It can be understood that the present invention can also be applied to adjust other MOS structures. For example, for the LV/HVMOS process, the thickness of the photoresist or the angle of ion implantation can also be adjusted to ensure that a structure (such as HVMOS) has perfect performance. , in turn, adjust the two LDD processes to ensure that the performance of another structure (such as LVMOS) meets the requirements. This method can also save at least two layers of LDD masks and at least two corresponding processes, thereby saving manufacturing costs and shortening chip production. cycle.

To sum up, the method for fabricating a semiconductor structure provided by the present invention includes: providing a front-end structure, wherein the front-end structure is formed with a first-type well and a second-type well, and is located on the first-type well and the second-type well, respectively the gate; perform the first ion implantation on the front-end structure to form first implantation regions on both sides of the gate in the first-type well and the second-type well, respectively; on the first-type well and the second A first mask layer is formed on the gate of the type well, and a second ion implantation is performed on the second type well, and a second implantation region is formed on both sides of the gate in the second type well, and the first implantation The ions of the second type are of the same type as the ions implanted for the second time; the first mask layer is removed; a second mask layer is formed on the second type well and the gate of the first type well, and the A third ion implantation is performed in the first type well, so that the first implantation region in the first type well is transformed into a third implantation region, and a fourth implantation region is formed on both sides of the gate in the first type well, and the first implantation region is formed in the first type well. The ions of the second implant are of a different type than the third implant; the second mask layer is removed. Therefore, the first implantation region and the third implantation region as LDD can be formed by the first implantation and the third implantation. Compared with the prior art, at least two layers of LDD masks and corresponding at least two layers can be saved. It can be seen that the cost can be greatly saved, the production process can be optimized, and the production cycle can be shortened.

In addition, the adjustment of NMOS performance can be achieved through the first ion implantation and the second ion implantation; through the first ion implantation and the third ion implantation, and further combined with the thickness of the gate spacer, the thickness of the mask layer, and the The selection of the third ion implantation angle can adjust the performance of the PMOS, such as improving the leakage current of the MOS structure, so that the performance of the product can be guaranteed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (13)

1. A method of fabricating a semiconductor structure, comprising: providing a front end structure formed with a first type well and a second type well, and gates on the first type well and the second type well, respectively; performing a first ion implantation on the front-end structure to form first implantation regions on both sides of the gate in the first-type well and the second-type well, respectively; A first mask layer is formed on the first type well and on the gate of the second type well, and a second ion implantation is performed on the second type well, and two sides of the gate are formed in the second type well In the second implantation region, the ions implanted for the first time are of the same type as the ions implanted in the second time; removing the first mask layer; A second mask layer is formed on the second type well and on the gate of the first type well, and a third ion implantation is performed on the first type well, so that the first implantation region in the first type well is It is transformed into a third implantation region, and a fourth implantation region is formed on both sides of the gate in the first type well, the ions implanted for the first time and the ions implanted in the third time are of different types, and the gate of the first type well is The thickness of the second mask layer on the pole is smaller than the thickness of the first mask layer on the gate of the second type well, and the angle of the third ion implantation is 30°- 60° included angle; The second mask layer is removed. 2 . The method for fabricating a semiconductor structure according to claim 1 , wherein the first type well is an N well, and the second type well is a P well. 3 . 3 . The method for fabricating a semiconductor structure according to claim 2 , wherein the thickness of the first mask layer on the gate of the P well is 3 .

The thickness of the second mask layer on the gate of the N well is

4 . The method for fabricating a semiconductor structure according to claim 2 , wherein the doping concentration and the implantation depth of the second implantation region are greater than the doping concentration and implantation depth of the first implantation region; The doping concentration and implantation depth of the four implanted regions are greater than those of the third implanted region. 5 . The method for fabricating a semiconductor structure according to claim 4 , wherein the first ion implantation is a general implantation of N-type ions. 6 . 6 . The method of claim 5 , wherein the second ion implantation is N-type ion implantation, and the third ion implantation is P-type ion implantation. 7 . 7 . The method for fabricating a semiconductor structure according to claim 2 , wherein a first ion implantation is performed on the front-end structure to form two sides of the gate in the first type well and the second type well respectively. 8 . After the first implantation region; forming a first mask layer on the gates of the first type well and the second type well, and before performing the second ion implantation on the second type well, further comprising: Gate spacers are formed on both sides of the gate. 8 . The method of claim 7 , wherein the thickness of the gate spacer on the gate side of the first type well is smaller than the thickness of the gate spacer on the gate side of the second type well. 9 . . 9 . The method for fabricating a semiconductor structure according to claim 8 , wherein the gate spacer on the gate side of the second type well has a thickness of 90 nm-110 nm, and the gate spacer on the gate side of the first type well has a thickness of 90 nm to 110 nm . The thickness of the pole sidewall is 80nm-90nm. 10 . The method for fabricating a semiconductor structure according to claim 1 , wherein the front-end structure further comprises a gate oxide layer, the gate oxide layer is located on the first type well and the second type well, and the A gate is located on the gate oxide layer. 11. The method for fabricating a semiconductor structure according to claim 10, wherein the gate oxide layer has a thickness of

12. The method for fabricating a semiconductor structure according to claim 1, wherein after the front end structure is provided and before the first ion implantation is performed on the front end structure, the method further comprises: A rapid thermal oxidation process is performed on the gate. 13. The method for fabricating a semiconductor structure according to claim 1, wherein after removing the second mask layer, further comprising: Carry out the annealing process.

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