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CN108122850B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN108122850B
CN108122850B CN201611066007.9A CN201611066007A CN108122850B CN 108122850 B CN108122850 B CN 108122850B CN 201611066007 A CN201611066007 A CN 201611066007A CN 108122850 B CN108122850 B CN 108122850B
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layer
forming
transistor
angstroms
protective layer
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CN108122850A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate and a plurality of fins positioned on the substrate, wherein the substrate comprises a first region and a second region, and the first region and the second region form two transistors with different types; forming a grid electrode structure which crosses the fin part and covers part of the side wall and part of the top surface of the fin part; forming a first stress layer in the fin parts at two sides of the first region grid structure; forming a first protective layer; performing ion implantation on the first stress layer to form a source drain doped region of the first transistor; forming a second stress layer in the fin parts at two sides of the second regional gate structure; forming a second protective layer; and performing ion implantation on the second stress layer to form a source drain doped region of the second transistor. The invention overcomes the over-high ion energy when the first stress layer is subjected to ion implantation, avoids the damage of the over-high energy to the semiconductor material and improves the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, the gate size of the planar transistor is getting smaller and smaller as the element density and integration of the semiconductor device are increased, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, increases leakage current, and finally affects the electrical performance of the semiconductor device.
In order to further reduce the size of the MOSFET device, a multi-faceted gate field effect transistor structure is developed to improve the control capability of the gate of the MOSFET device and suppress the short channel effect. Fin field effect transistors (finfets) are one common multi-faceted gate structure transistor. In the FinFET, the grid electrode can control the ultrathin body (fin part) at least from two sides, the control capability of the grid electrode on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the performance of the finfet formed in the prior art needs to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a plurality of fins positioned on the substrate, the substrate comprises a first region used for forming a first transistor and a second region used for forming a second transistor, and the types of the first transistor and the second transistor are different; forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the side wall and part of the top surface of the fin part; forming a first stress layer in the fin parts at two sides of the first region grid structure; forming a first protective layer on the fin portion, the gate structure, the first stress layer and the second region; performing ion implantation on the first stress layer below the first protective layer to form a source drain doped region of the first transistor; forming a second stress layer in the fin parts at two sides of the second region grid electrode structure; forming a second protective layer on the fin portion, the gate structure, the source-drain doped region of the first transistor and the second stress layer; and performing ion implantation on the second stress layer below the second protective layer to form a source drain doped region of the second transistor.
Optionally, the step of forming the second stress layer includes: forming a mask material layer on the first protection layer and the second region; forming a first pattern layer on the mask material layer; etching the first protective layer and the mask material layer by using the first pattern layer to form a first mask; forming a groove in the second region substrate by taking the first mask as a mask; and forming a second stress layer in the groove.
Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the thickness of the masking material layer is in the range of 30 angstroms to 80 angstroms; the first protective layer thickness is in a range of 20 angstroms to 50 angstroms; the ion energy for carrying out ion implantation on the first stress layer is 0.5KeV to 10 KeV; the second protective layer has a thickness in a range of 20 angstroms to 40 angstroms; and the ion energy for carrying out ion implantation on the second stress layer is between 1.5 and 15 KeV.
Optionally, the first transistor is an N-type transistor, and the first transistor is a P-type transistor; the thickness of the masking material layer is in the range of 35 angstroms to 100 angstroms; the first protective layer thickness is in a range of 15 angstroms to 40 angstroms; the ion energy for carrying out ion implantation on the first stress layer is 1KeV to 10 KeV; the second protective layer has a thickness in a range of 35 angstroms to 100 angstroms; and the ion energy for carrying out ion implantation on the second stress layer is between 0.4 and 8 KeV.
Optionally, the step of forming the second stress layer includes: forming a second graphic layer on the first protective layer; etching the first protective layer by using the second pattern layer to form a second mask; etching the second area substrate by taking the second mask as a mask to form a groove; and forming a second stress layer in the groove.
Optionally, the material of the first protection layer is SiN, SiCN, SiBCN, or SiOCN.
Optionally, after forming the source-drain doped region of the second transistor, the forming method further includes: forming a stop layer on the second protective layer; forming a first interlayer dielectric layer on the stop layer; forming a through hole in the first interlayer dielectric layer by taking the second protective layer and the stop layer as contact hole etching stop layers; and forming a conductive plug in the through hole.
Optionally, the stop layer has a thickness in the range of 40 angstroms to 100 angstroms.
Optionally, after forming the source-drain doped region of the second transistor, the forming method further includes: forming a second interlayer dielectric layer on the second protective layer; forming a through hole in the second interlayer dielectric layer by taking the second protective layer as a contact hole etching stop layer; and forming a conductive plug in the through hole.
The present invention also provides a semiconductor structure, comprising: the semiconductor device comprises a base and a plurality of fins, wherein the base comprises a substrate and a plurality of fins positioned on the substrate, the substrate comprises a first region used for forming a first transistor and a second region used for forming a second transistor, and the types of the first transistor and the second transistor are different; the grid electrode structure stretches across the fin part and covers part of the side wall and part of the top surface of the fin part; the first stress layer is positioned in the fin parts at two sides of the first region grid structure, and a source-drain doped region of the first transistor is formed in the first stress layer; the second stress layer is positioned in the fin parts at two sides of the second area grid electrode structure, and a source drain doped region of the second transistor is formed in the second stress layer; the first protective layer is positioned on the first stress layer, the first area grid structure and the side wall of the second area grid structure; and the second protective layer is positioned on the first protective layer, the second regional gate structure and the second stress layer.
Optionally, the first transistor is a P-type transistor, the first protective layer has a thickness in a range of 60 to 90 angstroms, and the second protective layer has a thickness in a range of 20 to 40 angstroms.
Optionally, the first transistor is an N-type transistor, the first protective layer has a thickness in a range of 60 to 90 angstroms, and the second protective layer has a thickness in a range of 30 to 100 angstroms.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, after the first protective layer is formed, ion implantation is carried out on the first stress layer, and a source-drain doped region of the first transistor is formed. Therefore, in the process of ion implantation of the first stress layer, implanted ions only need to penetrate through the first protective layer, and the ion implantation energy is relatively low, so that the crystal lattice damage is reduced; in addition, in the process of subsequent thermal annealing repair, the phenomenon of excessive stress release is reduced, so that the control of ion diffusion is facilitated, and the short channel effect is relieved, so that the performance of the formed semiconductor structure is improved.
In the alternative of the invention, when the second stress layer is formed, a second mask can be formed by etching the first protective layer on the substrate in the second region; and forming a second stress layer by using the second mask as a mask. The protective layer on the second region is used as a mask layer in the process of forming the second stress layer, so that the reduction of process steps is facilitated, and the process cost is reduced.
In the alternative scheme of the invention, after the first protective layer is formed, the mask material layer is formed on the surface of the first protective layer, so that the thickness of the first protective layer can be controlled to a greater extent without considering the subsequent action of the first protective layer, the energy for ion implantation of the first stress layer is lower, the ion distribution is effectively controlled, the short channel effect is reduced, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-4 are schematic cross-sectional views of a semiconductor structure during steps of a semiconductor structure formation process;
fig. 5 to 11 are schematic cross-sectional views corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As is known in the art, the performance of the semiconductor structure formed in the prior art needs to be improved. The reason is now analyzed in conjunction with the method of forming the semiconductor structure. Referring to fig. 1 to 4, cross-sectional structures of respective steps of a semiconductor structure forming method are illustrated.
The semiconductor structure forming method comprises the following steps: as shown in fig. 1, a substrate 10 is provided, and a fin 11 located on the substrate 10 is formed, where the substrate 10 includes a first region a for forming a first transistor and a second region B for forming a second transistor, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; forming an isolation layer 12 on the substrate 10 and between the fin portions 11, and forming an oxide layer 13 on the fin portions 11; forming a gate structure 14 crossing the fin, wherein the gate structure 14 covers part of the side wall and part of the top surface of the fin 11; forming first stress layers 15 in the fin portion 11 on two sides of the gate structure 14 in the first region a, and forming mask material layers 16 on the fin portion 11, the gate structure 14 and the first stress layers 15; forming a pattern layer on the mask material layer 16, and etching the mask material layer 16 by using the pattern layer to form a groove; as shown in fig. 2, forming a second stress layer 17 in the groove; as shown in fig. 3, forming a protective material layer 18 on the mask material layer 16 in the first region a, the second stress layer 17 and the gate structure 14 in the second region B; as shown in fig. 4, performing ion implantation on the first stress layer 15 in the first region a and the second stress layer 17 in the second region B, respectively; and forming a source drain doped region of the first transistor and a source drain doped region of the second transistor.
When the first stress layer 15 in the first region a is subjected to ion implantation, the first stress layer needs to penetrate through the mask material layer 16 and the protective material layer 18, so that the implanted ions need to enter the first stress layer 15 only by adopting higher ion implantation energy, and the excessively high ion implantation energy easily causes too much crystal lattice damage and even forms an amorphous structure; the amorphous structure is easy to cause the performance of the stress layer to be reduced due to excessive stress release in the subsequent annealing process, and can cause the doping ions to excessively diffuse to the channel region to aggravate the short channel effect, thereby causing the performance degradation of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a plurality of fins positioned on the substrate, the substrate comprises a first region used for forming a first transistor and a second region used for forming a second transistor, and the types of the first transistor and the second transistor are different; forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the side wall and part of the top surface of the fin part; forming a first stress layer in the fin parts at two sides of the first region grid structure; forming a first protective layer on the fin portion, the gate structure, the first stress layer and the second region; performing ion implantation on the first stress layer below the first protective layer to form a source drain doped region of the first transistor; forming a second stress layer in the fin parts at two sides of the second regional gate structure; forming a second protective layer on the fin portion, the gate structure and the first stress layer; and performing ion implantation on the second stress layer below the second protective layer to form a source drain doped region of the second transistor.
According to the technical scheme, after the first protective layer is formed, ion implantation is carried out on the first stress layer, and a source-drain doped region of the first transistor is formed. Therefore, in the process of ion implantation of the first stress layer, implanted ions only need to penetrate through the first protective layer, the ion implantation energy is relatively low, and the over-high ion implantation energy is reduced, so that the crystal lattice damage is reduced; in the process of subsequent thermal annealing repair, excessive stress release is avoided, ion diffusion is effectively controlled, and short channel effect is reduced, so that the performance of the formed semiconductor structure is improved. In addition, the first protective layer can also be used as a mask layer for forming a second stress layer subsequently, so that the process steps are reduced, and the production cost is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 11 are schematic cross-sectional views corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Referring to fig. 5, a base is provided, the base includes a substrate 101 and a plurality of fins 102 on the substrate 101, the substrate 101 includes a first region I for forming a first transistor and a second region II for forming a second transistor, and the types of the first transistor and the second transistor are different.
The substrate is formed from an initial substrate as a basis for a process for forming the semiconductor structure. In this embodiment, the material of the initial substrate is monocrystalline silicon. The material of the substrate 101 and the fin 102 is also monocrystalline silicon.
In other embodiments of the present invention, the material of the initial substrate may also be selected from germanium, gallium arsenide, or silicon germanium compounds; the initial substrate may also be other semiconductor materials. In addition, the initial substrate can also be selected from epitaxial layers or silicon-on-epitaxial layers.
It should be noted that the materials of the substrate and the fin portion may be different. The initial base may include a substrate and a semiconductor layer on the substrate. The substrate may be a material suitable for process requirements or easy to integrate; the material of the semiconductor layer may be a material suitable for forming a fin.
The step of etching the initial substrate comprises: forming a patterned fin mask layer (not shown) on the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask to form the substrate 101 and the discrete fin parts 102.
The fin mask layer may be a patterned photoresist layer formed by a coating process and a photolithography process. Alternatively, the fin mask layer may be a hard mask layer or a mask layer formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
In addition, the base further includes an isolation layer 103 on the substrate 101 between adjacent fins 102, for achieving electrical isolation between adjacent fins 102 and between the semiconductor structure and other semiconductor structures on the substrate 101.
In this embodiment, the isolation layer 103 is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.
Specifically, the step of forming the isolation layer 103 includes: forming an isolation material layer on the substrate 101 between adjacent fins 102, the isolation material layer covering the fin mask layer; and removing part of the thickness of the isolation material layer to form an isolation layer 103, so that the top surface of the formed isolation layer 103 is lower than the top surface of the fin 102, and part of the surface of the side wall of the fin 102 is exposed.
In this embodiment, the first region I and the second region II are adjacent to each other. In other embodiments of the present invention, the first region I and the second region II may not be adjacent to each other.
In this embodiment, the first transistor is a P-type transistor, and the second transistor is an N-type transistor. In other embodiments of the present invention, the first transistor may also be an N-type transistor, and the second transistor may also be a P-type transistor.
With continued reference to fig. 5, a gate structure is formed across the fin 102, covering a portion of the sidewalls and a portion of the top surface of the fin 102. The gate structure is used for forming a gate of a transistor and is also used for shielding part of the fin portion 102 in the subsequent transistor source region or drain region forming process so as to prevent the formed transistor source region or drain region from being in direct contact.
The gate structure includes a gate dielectric layer 104 on the fin 102 and a gate electrode 105 on the gate dielectric layer 104.
In this embodiment, the forming method further includes: forming a first hard mask layer 106 on the gate electrode 105, forming a second hard mask layer 107 on the first hard mask layer 106, and forming gate spacers 108 on sidewalls of the gate electrode 105, the first hard mask layer 106, and the second hard mask layer 107.
In other embodiments of the present invention, the gate structure may also be a dummy gate structure, which is used to occupy a spatial position for a subsequently formed gate structure.
The gate dielectric layer 104 is used for isolating the gate electrode 105 from the channel. The gate dielectric layer 104 may include a high-K dielectric layer.
The material of the gate electrode 105 may be polysilicon or metal.
The first hard mask layer 106 and the second hard mask layer 107 are used to define the size and location of the gate structure. The first hard mask layer 106 is made of silicon oxide, and the second hard mask layer 107 is made of nitride.
The gate spacers 108 function to control the distance between the subsequently formed epitaxial layer and the channel. The gate spacer 108 is made of a single layer of silicon nitride. In other embodiments of the present invention, the gate sidewall may also be made of silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride. In addition, the gate side wall may also be a stacked structure.
Continuing to refer to fig. 5, a patterned mask layer 109 is formed on the fin portion and the gate structure in the first region I, the fin portions 102 on both sides of the gate structure in the first region I are etched by using the mask layer 109 as a mask, a groove is formed, and a first stress layer 110 is formed in the groove.
The first stress layer 110 is used for forming a source-drain doped region of the first transistor.
In the present embodiment, the material of the first stress layer 110 is SiGe, and the shape of the first stress layer 110 is "Σ" shape. The first stress layer 110 applies a compressive stress to the channel region of the first transistor through lattice mismatch between Si and SiGe to increase the mobility of carriers in the channel, thereby improving the performance of the transistor.
The process steps for forming the first stress layer 110 include: the first stress layer 110 is formed in the groove by epitaxial growth.
It should be noted that, in this embodiment, after forming the gate structure, before forming the first stress layer 110 in the fin 102 on both sides of the first region igate structure, the forming method further includes: the fin 102 is lightly doped with a drain implant process and a pocket implant process to improve the performance of the transistor.
Referring to fig. 6, a first protection layer 111 is formed on the fin 102, the gate structure, the first stress layer 110 and the second region II.
The first protection layer 111 serves to prevent implantation damage during ion implantation into the first stress layer 110 and to control the depth of ion implantation.
In this embodiment, the first protection layer 111 is made of SiN. In other embodiments of the present invention, the material of the first protection layer 111 may also be SiCN, SiBCN, or SiOCN.
The thickness of the first protective layer 111 should not be too large or too small, and if the thickness is too large, the depth of ion implantation is affected, higher ion implantation energy is needed, lattice damage is easily caused, and the effective control of the ion distribution in the material is not facilitated; if the thickness is too small, the protection function of the first protective layer 111 is affected. In this embodiment, the thickness of the first protective layer 111 is in the range of 20 to 50 angstroms.
Referring to fig. 7, ion implantation is performed on the first stress layer 110 under the first protection layer 111 to form a source-drain doped region of the first transistor.
In this embodiment, the ion implantation performed on the first stress layer 110 only needs to penetrate through the first protection layer 111, so that the implantation energy required for the implantation depth to reach the preset value is relatively small, the ion diffusion is better controlled, and the short channel effect is favorably improved, thereby improving the performance of the formed semiconductor structure.
In this embodiment, the type of the implanted ions is P-type ions, such as B, Ga or In, and the implantation energy for the ion implantation of the first stress layer 110 is 0.5KeV to 10 KeV. Compared with the technical scheme that ion implantation needs to be performed through the mask material layer and the protective material layer, in the embodiment, the ion implantation energy is reduced by 50% to 100%.
Referring to fig. 8, a mask material layer 112 is formed on the first protection layer 111 and the second region II. The mask material layer 112 is used for forming a first mask, and a groove is formed in the fin 102 on two sides of the second region II gate structure by using the first mask as a mask, and the groove is used for forming a stress layer of the second transistor.
In this embodiment, the material of the mask material layer 112 is SiN; in other embodiments of the present invention, the material of the mask material layer is SiCN, SiBCN or SiOCN.
The thickness of the mask material layer 112 should not be too large or too small, and if the thickness of the mask material layer 112 is too large, material waste is easily caused, thereby increasing the production cost; if the thickness of the mask material layer 112 is too small, the masking effect is easily affected, and the performance of the semiconductor structure is easily affected. In this embodiment, the thickness of the masking material layer 112 is in the range of 30 angstroms to 80 angstroms.
In the present embodiment, a mask material layer 112 is formed on the first protective layer 111 to form a first mask. It should be noted that, in other embodiments of the present invention, a mask may also be formed only through the first protection layer, that is, when ion implantation is performed on the first stress layer, the first protection layer located on the first stress layer plays a role in protecting the first stress layer; meanwhile, when the groove is formed, the first protective layer positioned on the second area II also plays a role of a mask, so that the process steps are favorably reduced, and the manufacturing cost is saved.
Referring to fig. 9, a second stress layer 113 is formed in the recess.
The second stress layer 113 is used for forming a source-drain doped region of the second transistor.
In this embodiment, the material of the second stress layer 113 is SiP, and the shape of the second stress layer 113 is "U" shape. The second stress layer 113 applies a tensile stress effect to the channel region of the second region II through lattice mismatch between Si and SiP to improve carrier mobility, thereby improving performance of the transistor.
Referring to fig. 10, a second protection layer 114 is formed on the fin 102, the gate structure, the source-drain doped region of the first transistor, and the second stress layer 113.
The second passivation layer 114 is used to prevent implantation damage and control the depth of ion implantation during the ion implantation process of the second stress layer 113.
In this embodiment, the material of the second protection layer 114 is SiN. In other embodiments of the present invention, the material of the second protection layer is SiCN, SiBCN or SiOCN;
the thickness of the second protection layer 114 should not be too large or too small, and if the thickness is too large, the depth of ion implantation will be affected, and higher ion implantation energy is needed, which is easy to cause lattice damage, and is not beneficial to effectively control the ion distribution in the material; if the thickness is too small, the protective function of the second protective layer 114 is affected. In this embodiment, the thickness of the second protection layer 114 is in the range of 20 to 40 angstroms.
With reference to fig. 10, ion implantation is performed on the second stress layer 113 below the second passivation layer 114 to form a source-drain doped region of the second transistor.
In this embodiment, the implanted ions are N-type ions, such as P, As or Sb, and the implantation energy for performing ion implantation on the second stress layer 113 is 1.5KeV to 15 KeV.
In the ion implantation process, the impact of the high-energy implanted ions on the first stress layer or the second stress layer is likely to cause lattice damage. To recover the lattice damage, an annealing process is performed after the ion implantation to redistribute the dopant ions within the substrate to achieve the desired junction depth and distribution.
In this embodiment, the second stress layer 113 is subjected to ion implantation and then subjected to annealing treatment. Because the process of ion implantation into the first stress layer 110 adopts smaller ion implantation energy, the lattice damage caused by the ion implantation process can be reduced, the release of stress is reduced in the annealing process, the ion distribution in the stress layer is better controlled, and the performance of the semiconductor structure is improved.
Referring to fig. 11, in this embodiment, after forming the source-drain doped region of the second transistor, the forming method further includes: forming a stop layer 115 on the second protective layer 114; forming a first interlayer dielectric layer 116 on the stop layer 115; forming a via hole (not shown) in the first interlayer dielectric layer 116 by using the second protection layer 114 and the stop layer 115 as a contact hole etching stop layer; conductive plugs (not shown) are formed in the through holes.
In this embodiment, the thickness of the stop layer 115 should not be too large or too small, and if the thickness is too large, the manufacturing material will be wasted; if the thickness is too small, the realization of the protective function as the contact hole etching stopper is impaired. In this embodiment, the stop layer 115 has a thickness in the range of 40 to 100 angstroms.
In this embodiment, the material of the stop layer 115 is the same as the material of the second protection layer 114. In other embodiments of the present invention, the material of the stop layer and the material of the second protective layer may also be different.
In addition, in other embodiments of the present invention, the second protection layer may also be used as a contact hole etching stop layer. The forming method therefore comprises: forming a second interlayer dielectric layer (not shown) on the second protective layer; forming a through hole in the second interlayer dielectric layer by taking the second protective layer as a contact hole etching stop layer; and forming a conductive plug in the through hole. The second protective layer plays a role of a protective layer and a contact hole etching stop layer, so that the process steps are reduced, and the manufacturing cost is saved.
In another embodiment of the present invention, the first transistor is an N-type transistor, and the second transistor is a P-type transistor. Correspondingly, the material of the first stress layer is SiP, and the shape of the first stress layer is U-shaped. The first stress layer exerts a tensile stress effect on a channel region of the first region I through lattice mismatch between Si and SiP so as to improve the mobility of current carriers in the channel and further improve the performance of the transistor.
And after ion implantation is carried out on the first stress layer below the first protective layer, a source drain doped region of the N-type transistor is formed. The type of implanted ions is N-type ions such as P, As or Sb, and the implantation energy for the ion implantation of the first stress layer is 1KeV to 10KeV, and the implantation energy varies due to the difference in implanted ions, resulting in a difference in the thickness of the first protective layer from that when forming a P-type transistor, which is in the range of 15 angstroms to 40 angstroms.
The second stress layer is made of SiGe, and the shape of the second stress layer is sigma-shaped. And the second stress layer exerts a compressive stress effect on the channel region of the second region II through lattice mismatch between Si and SiGe so as to improve the mobility of carriers of the P-type transistor and further improve the performance of the P-type transistor.
And performing ion implantation on the second stress layer below the second protective layer to form a source-drain doped region of the P-type transistor. Therefore, the implanted ions are P-type ions, such as B, Ga or In, and the implantation energy for the ion implantation of the second stress layer is 0.4KeV to 8 KeV. The implant energy varies due to the difference in implanted ions, resulting in a difference in the thickness of the layer of masking material, which is in the range of 35 angstroms to 100 angstroms, from that of the layer of masking material when forming the N-type transistor.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 10, a cross-sectional structure of a semiconductor structure according to an embodiment of the invention is shown.
The semiconductor structure includes: the transistor structure comprises a base, wherein the base comprises a substrate 101 and a plurality of fins 102 positioned on the substrate, the substrate 101 comprises a first area I used for forming a first transistor and a second area II used for forming a second transistor, and the types of the first transistor and the second transistor are different; a gate structure crossing the fin 102, wherein the gate structure covers part of the sidewall and part of the top surface of the fin 102, and the gate structure comprises a gate dielectric layer 104 on the fin 102 and a gate electrode 105 on the gate dielectric layer 104; the first stress layer 110 is positioned in the fin part 102 at two sides of the first region I grid structure, and a source-drain doped region of a first transistor is formed in the first stress layer 110; a second stress layer 113 located in the fin portion 102 at two sides of the second region II gate structure, wherein a source-drain doped region of a second transistor is formed in the second stress layer 113; a first protection layer 111 on the first stress layer 110, the first region I gate structure and the sidewall of the second region II gate structure; and a second protective layer 114 located on the first protective layer 111, the second region II gate structure, and the second stress layer 113.
The material of the substrate 101 and the fin portion 102 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate 101 and the fin 102 may also be selected from germanium, gallium arsenide, or a silicon-germanium compound; the substrate 101 and the fin 102 may also be other semiconductor materials.
In addition, the substrate further includes an isolation layer 103 located on the substrate 101 between adjacent fins 102, and a top surface of the isolation layer 103 is lower than a top surface of the fins 102 to expose the top surface and a portion of a sidewall of the fins 102. The isolation layer 103 is used to achieve electrical isolation between adjacent fins 102 and between the semiconductor structure and other semiconductor structures on the substrate 101. In this embodiment, the isolation layer 103 is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the first region I and the second region II are adjacent to each other. In other embodiments of the present invention, the first region I and the second region II may not be adjacent to each other.
In this embodiment, the first transistor is a P-type transistor, and the second transistor is an N-type transistor. In other embodiments of the present invention, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.
In this embodiment, the gate structure crosses over the fin 102 and covers a portion of the sidewall and a portion of the top surface of the fin 102; the gate structure comprises a gate dielectric layer 104 located on the fin portion 102, and a gate electrode 105 located on the gate dielectric layer. A first hard mask layer 106 is formed on the gate electrode 105, a second hard mask layer 107 is formed on the first hard mask layer 106, and gate spacers 108 are formed on the sidewalls of the gate electrode 105, the first hard mask layer 106 and the second hard mask layer 107.
In other embodiments of the present invention, the gate structure may also be a dummy gate structure, which is used to occupy a spatial position for a subsequently formed gate structure.
The gate dielectric layer 104 is used to isolate the gate electrode from the channel. The gate dielectric layer 104 may include a high-K dielectric layer.
The gate electrode 105 is used to make an electrical connection with an external circuit. The material of the gate electrode 105 may be polysilicon or metal.
The first hard mask layer 106 and the second hard mask layer 107 are used to define the size and location of the gate structure. The first hard mask layer 106 is made of silicon oxide, and the second hard mask layer 107 is made of nitride.
In this embodiment, the gate sidewall 108 is used to control the distance between the epitaxial layer and the channel; the gate spacer 108 is made of a single layer of silicon nitride. In other embodiments of the present invention, the gate sidewall may also be made of silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride. In addition, the gate sidewall spacers 108 may also be a stacked structure.
A source-drain doped region of the first transistor is formed in the first stress layer 110. In this embodiment, the first stress layer 110 is made of SiGe, and the shape of the first stress layer is "Σ". The first stress layer 110 applies compressive stress to the channel region of the first transistor through lattice mismatch between Si and SiGe to improve mobility of carriers in the channel, thereby improving performance of the transistor.
In this embodiment, the first protection layer 111 on the first stress layer 110 is used to prevent implantation damage and control the depth of ion implantation during the ion implantation process of the first stress layer 110. The first protective layer 111 is made of SiN. In other embodiments of the present invention, the material of the first protection layer may also be SiCN, SiBCN, or SiOCN. In this embodiment, the thickness of the first protective layer 111 is in the range of 60 to 90 angstroms.
The second stress layer 113 is used for forming a source-drain doped region of the second transistor. The material of the second stress layer 113 is SiP, and the shape of the second stress layer 113 is "U" shape. The second stress layer 113 applies a tensile stress effect to the channel region of the second region II through lattice mismatch between Si and SiP, so as to improve the mobility of carriers in the channel of the N-type transistor, thereby improving the performance of the transistor. The second passivation layer 114 located on the second stress layer 113 is used to prevent implantation damage and control the depth of ion implantation during the ion implantation process of the second stress layer 113. The second protection layer 114 material is SiN. In other embodiments of the present invention, the material of the second passivation layer may also be SiCN, SiBCN, or SiOCN. In this embodiment, the thickness of the second protective layer is in the range of 20 angstroms to 40 angstroms.
In another embodiment of the present invention, the first transistor is an N-type transistor, and the second transistor is a P-type transistor. Correspondingly, the material of the first stress layer is SiP. The first stress layer is U-shaped. The first stress layer exerts a tensile stress effect on a channel region of the first region I through lattice mismatch between Si and SiP so as to improve the mobility of current carriers in the channel and further improve the performance of the transistor. The first protective layer has a thickness in a range of 60 angstroms to 90 angstroms. The second stress layer is made of SiGe, and the shape of the second stress layer is sigma-shaped. And the second stress layer exerts a compressive stress effect on the channel region of the second region II through lattice mismatch between Si and SiGe so as to improve the mobility of carriers of the P-type transistor and further improve the electrical property of the P-type transistor. The second protective layer has a thickness in a range of 30 angstroms to 100 angstroms.
In summary, in the technical solution of the present invention, after the first protection layer is formed, ion implantation is performed on the first stress layer to form a source-drain doped region of the first transistor. Therefore, in the process of ion implantation of the first stress layer, implanted ions only need to penetrate through the first protective layer, and the ion implantation energy is relatively low, so that the crystal lattice damage is reduced; in addition, in the process of subsequent thermal annealing repair, the phenomenon of excessive stress release is reduced, so that the control of ion diffusion is facilitated, and the short channel effect is relieved, so that the performance of the formed semiconductor structure is improved. In addition, in the alternative of the invention, when the second stress layer is formed, a second mask can be formed by etching the first protective layer on the substrate in the second area; and forming a second stress layer by using the second mask as a mask. The protective layer on the second region is used as a mask layer in the process of forming the second stress layer, so that the reduction of process steps is facilitated, and the process cost is reduced. In addition, in the alternative of the invention, after the first protective layer is formed, the mask material layer is formed on the surface of the first protective layer, so that the thickness of the first protective layer can be controlled to a greater extent without considering the subsequent action of the first protective layer, the energy for ion implantation of the first stress layer is lower, the ion distribution is effectively controlled, the short channel effect is reduced, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a plurality of fins positioned on the substrate, the substrate comprises a first region used for forming a first transistor and a second region used for forming a second transistor, and the types of the first transistor and the second transistor are different;
forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the side wall and part of the top surface of the fin part;
forming a first stress layer in the fin parts at two sides of the first region grid structure;
forming a first protective layer on the fin portion, the gate structure, the first stress layer and the second region;
performing ion implantation on the first stress layer below the first protective layer to form a source drain doped region of the first transistor;
forming a second stress layer in the fin parts at two sides of the second region grid electrode structure;
forming a second protective layer on the fin portion, the gate structure, the source-drain doped region of the first transistor and the second stress layer;
and performing ion implantation on the second stress layer below the second protective layer to form a source drain doped region of the second transistor.
2. The method of forming of claim 1, wherein forming the second stress layer comprises:
forming a mask material layer on the first protection layer and the second region;
forming a first pattern layer on the mask material layer;
etching the first protective layer and the mask material layer by using the first pattern layer to form a first mask;
forming a groove in the second region substrate by taking the first mask as a mask;
and forming a second stress layer in the groove.
3. The method of forming of claim 2, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.
4. The method of forming of claim 3, wherein the layer of masking material has a thickness in a range of 30 angstroms to 80 angstroms.
5. The method of forming of claim 3, wherein the first protective layer thickness is in a range of 20 angstroms to 50 angstroms.
6. The method of claim 3, wherein the first stressor layer is ion implanted with an ion energy in a range from 0.5KeV to 10 KeV.
7. The method of forming of claim 3, wherein a thickness of the second protective layer is in a range of 20 angstroms to 40 angstroms; and the ion energy for carrying out ion implantation on the second stress layer is in the range of 1.5KeV to 15 KeV.
8. The method of forming of claim 2, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.
9. The method of forming of claim 8, wherein the layer of masking material has a thickness in a range of 35 angstroms to 100 angstroms.
10. The method of forming of claim 8, wherein the first protective layer thickness is in a range of 15 angstroms to 40 angstroms.
11. The method of claim 8, wherein the first stressor layer is ion implanted with an ion energy in a range from 1KeV to 10 KeV.
12. The method of forming of claim 8, wherein a thickness of the second protective layer is in a range of 35 angstroms to 100 angstroms; and the ion energy for carrying out ion implantation on the second stress layer is in the range of 0.4KeV to 8 KeV.
13. The method of forming of claim 1, wherein forming the second stress layer comprises: forming a second graphic layer on the first protective layer;
etching the first protective layer by using the second pattern layer to form a second mask;
etching the second area substrate by taking the second mask as a mask to form a groove;
and forming a second stress layer in the groove.
14. The method of claim 1, wherein the first protective layer is SiN, SiCN, SiBCN, or SiOCN.
15. The method of forming of claim 1, wherein after forming source and drain doped regions of the second transistor, the method further comprises:
forming a stop layer on the second protective layer;
forming a first interlayer dielectric layer on the stop layer;
forming a through hole in the first interlayer dielectric layer by taking the second protective layer and the stop layer as contact hole etching stop layers;
and forming a conductive plug in the through hole.
16. The method of forming as in claim 15 wherein the stop layer has a thickness in the range of 40 angstroms to 100 angstroms.
17. The method of forming of claim 1, wherein after forming source and drain doped regions of the second transistor, the method further comprises:
forming a second interlayer dielectric layer on the second protective layer;
forming a through hole in the second interlayer dielectric layer by taking the second protective layer as a contact hole etching stop layer;
and forming a conductive plug in the through hole.
18. A semiconductor structure, comprising:
the semiconductor device comprises a base and a plurality of fins, wherein the base comprises a substrate and a plurality of fins positioned on the substrate, the substrate comprises a first region used for forming a first transistor and a second region used for forming a second transistor, and the types of the first transistor and the second transistor are different;
the grid electrode structure stretches across the fin part and covers part of the side wall and part of the top surface of the fin part;
the first stress layer is positioned in the fin parts at two sides of the first region grid structure, and a source-drain doped region of the first transistor is formed in the first stress layer;
the second stress layer is positioned in the fin parts at two sides of the second area grid electrode structure, and a source drain doped region of the second transistor is formed in the second stress layer;
the first protective layer is positioned on the first stress layer, the first area grid structure and the side wall of the second area grid structure;
and the second protective layer is positioned on the first protective layer, the second regional gate structure and the second stress layer.
19. The semiconductor structure of claim 18, wherein the first transistor is a P-type transistor, the first protective layer has a thickness in a range of 60 angstroms to 90 angstroms, and the second protective layer has a thickness in a range of 20 angstroms to 40 angstroms.
20. The semiconductor structure of claim 18, wherein the first transistor is an N-type transistor, the first protective layer has a thickness in a range of 60 to 90 angstroms, and the second protective layer has a thickness in a range of 30 to 100 angstroms.
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