CN108305877B - Back gate non-junction NAND flash memory and manufacturing method thereof - Google Patents
Back gate non-junction NAND flash memory and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a back gate junctionless NAND flash memory and a manufacturing method thereof, wherein the memory comprises: the device comprises a substrate, an insulating layer, a two-dimensional semiconductor material channel layer, a carbon nanotube grid array, a grid capture structure, a protective layer, a source contact electrode and a drain contact electrode. The gate trapping structure comprises a tunnel layer, a charge trapping layer and a blocking layer, wherein the tunnel layer is located on the channel layer, the blocking layer surrounds the outer side faces of carbon nanotubes in the carbon nanotube gate array, and the charge trapping layer comprises a first portion surrounding the outer side faces of the blocking layer and a second portion located on the tunnel layer and in contact with the first portion. The back-gate junctionless NAND flash memory adopts a two-dimensional semiconductor material horizontal channel, adopts a metallic carbon nanotube gate array, and surrounds a carbon nanotube gate by a barrier layer and a charge trapping layer, so that the structure of the device can be simplified, the density of a storage unit can be improved, and stronger gate charge trapping performance can be obtained.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a back-gate junction-free NAND flash memory and a manufacturing method thereof.
Background
For NAND (NAND) memories of different architectures, they can be divided into three-dimensional floating gate memories and three-dimensional charge trapping memories according to the material division of the memory layers. The former is mainly promoted by american light corporation, and the technical preparation is completed in 2015, because the polysilicon floating gate is used as a storage layer, the area of the storage unit is larger, and the process difficulty is higher when more layers of storage units are stacked, so that the area is reduced by mainly arranging a peripheral circuit below the storage array. The latter three-dimensional charge trap memory can be divided into a vertical gate type and a vertical channel type. The three-dimensional charge trapping flash memory structure based on the vertical gate structure proposed by taiwangwhong has a process difficulty in vertical channel type, and has not been declared to be mass-produced. The vertical channel type three-dimensional charge trapping memory is a flash memory product which realizes large-scale mass production at the earliest, in 8 months in 2013, the three-star electron promotes a first generation 24-layer three-dimensional vertical channel type charge trapping three-dimensional memory, in 7 months in 2014, a second generation 32-layer 128Gb product is promoted, and in 2015, a 48-layer 256Gb product is promoted.
The three-dimensional charge trapping memory cell of the samsung electron vertical channel type is also based on the junction-free field effect transistor structure. The chip has 24 layers of stacked Word Lines (WL). Except the lowest unit selection transistor in the normal inversion mode, the rest of the transistors in each word unitBoth transistors are based on Charge trapping Flash junction-free Thin-film transistors (JL Charge Trap Flash Thin-film transistors, JL-CTF TFTs). When the device is closed, a polysilicon thin film channel (tubular) is required to be in a fully depleted state; therefore, the polysilicon film Thickness (TCH) is as thin as possible. In addition, there is a strong demand for further increasing the density of memory cells, and the polysilicon thin film channel TCH is also being continuously reduced. The product exhibits superior performance compared to devices operating in Inversion Mode (IM), providing faster write/erase (P/E) speeds, larger memory window>12V), and better endurance (> 10)4Second); it also has excellent 10-year data retention capacity under the test condition of 150 ℃. The switching current ratio of the device is more than 108And simultaneously has very steep subthreshold swing. However, the channel material of the device is a polysilicon film, which is required to have good crystallinity and larger crystal grains, and the thickness (T) of the polysilicon filmCH) The thickness is as thin as possible, the process is difficult to be considered, and the product yield is influenced.
Silicon (Si) transistors are predicted to have gate lengths that cannot be scaled below 5nm because of the severe short channel effects that occur at that time. As an alternative to silicon, certain layered semiconductors are more attractive due to their properties of uniform monoatomic layer thickness, lower dielectric constant, larger band gap, and heavier effective carrier mass, allowing smaller gates to control their current. Sujay et al show a MoS with a gate length of only 1nm2A transistor using single-walled carbon nanotube as gate electrode, wherein a single carbon nanotube with a diameter of 1nm is embedded in the MoS2ZrO in a thin layer (0.65nm thick)2In the film. These ultrashort devices exhibit excellent switching characteristics, such as: subthreshold swing amplitude of about 65mV/dec, and about 106The on-off current ratio of (c). Simulation results show that the effective channel length is about 3.9 nm in the off state and about 1nm in the on state. (Science DOI:10.1126/Science. aah4698)
Therefore, how to provide a new nand flash memory and a method for manufacturing the same, so as to utilize the advantages of the two-dimensional semiconductor material and the carbon nanotube to further improve the performance of the memory and reduce the process difficulty, is an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a back-gate junction-free nand flash memory and a manufacturing method thereof, which are used to solve the problems of large size, complex structure and high process difficulty of the nand flash memory in the prior art.
To achieve the above and other related objects, the present invention provides a back-gate junction-free nand flash memory, comprising:
a substrate;
an insulating layer over the substrate;
the channel layer is positioned on the insulating layer and made of two-dimensional semiconductor materials;
the carbon nano tube grid array is suspended above the channel layer and comprises a plurality of discrete carbon nano tubes, and the carbon nano tubes are used as gate electrodes of transistors in the memory;
a gate trapping structure comprising a tunnel layer, a charge trapping layer and a blocking layer; wherein the tunnel layer is located over the channel layer, the blocking layer surrounds the outer sides of the carbon nanotubes, and the charge trapping layer includes a first portion surrounding the outer sides of the blocking layer and a second portion located over the tunnel layer and in contact with the first portion;
a protective layer covering the gate trapping structure;
and the source contact electrode and the drain contact electrode are respectively positioned at two ends of the carbon nano tube grid array and are respectively connected with the channel layer.
Optionally, the device further comprises a plurality of gate contact electrodes for leading out the carbon nanotubes respectively.
Optionally, the carbon nanotubes are metallic carbon nanotubes.
Optionally, the carbon nanotube has a tube diameter of 0.75-3 nm and a length of 100 nm-50 μm.
Optionally, the memory comprises a plurality of serial strings, each serial string comprises a memory cell string and a non-junction switch transistor respectively connected to two ends of the memory cell string; the memory cell string comprises a plurality of memory cell transistors connected in series; the carbon nanotube grid array corresponds to the serial, and each carbon nanotube in the carbon nanotube grid array is respectively used as a gate electrode of each transistor in the serial.
Optionally, the non-junction switch transistors connected to two ends of the memory cell string are a string selection transistor and a ground selection transistor, respectively.
Optionally, in the carbon nanotube grid array, the carbon nanotubes are arranged in parallel in a horizontal plane.
Optionally, the two-dimensional semiconductor material is selected from MoS2、WS2、ReS2And SnO.
Optionally, the material of the charge trapping layer includes at least one of nitride and hafnium oxide, and the material of the blocking layer and the material of the tunnel layer are both high-K dielectrics with a dielectric constant greater than 3.9.
The invention also provides a manufacturing method of the back gate junctionless NAND gate flash memory, which comprises the following steps:
providing a substrate, and sequentially forming an insulating layer, a two-dimensional semiconductor material channel layer and a tunnel layer on the substrate from bottom to top;
forming a sacrificial layer on the tunneling layer;
forming a carbon nano tube grid array on the sacrificial layer; the carbon nanotube grid array comprises a plurality of carbon nanotubes which are separately arranged and are used as gate electrodes of transistors in the memory;
wet etching is carried out on the sacrificial layer, so that the carbon nano tube grid array is suspended, and parts of the sacrificial layer positioned at the two axial ends of the carbon nano tube are reserved as supporting layers;
forming a barrier layer surrounding the outer side surface of the carbon nano tube;
forming a charge trapping layer; the charge trapping layer includes a first portion surrounding an outer side of the blocking layer and a second portion over and in contact with the tunnel layer;
forming a protective layer covering the charge trapping layer;
and forming a source contact electrode and a drain contact electrode which are respectively positioned at two ends of the carbon nanotube grid array and connected with the channel layer, and forming grid contact electrodes respectively leading out the carbon nanotubes.
Optionally, a chemical vapor deposition method is used to form the carbon nanotube gate array on the sacrificial layer, wherein the material of the sacrificial layer includes a carbon nanotube growth catalyst material.
Optionally, the carbon nanotube growth catalyst material comprises one or more of Ni, Ag, Fe, Co.
Optionally, the method of forming the source and drain contact electrodes includes the steps of: and forming a through hole penetrating through the protective layer, the charge trapping layer and the tunnel layer, and filling a conductive material in the through hole.
Optionally, the method of forming the gate contact electrode includes the steps of: and forming a through hole penetrating through the protective layer, the charge trapping layer and the blocking layer, and filling a conductive material in the through hole.
As described above, the back gate junction-free nand flash memory and the manufacturing method thereof of the invention have the following beneficial effects: the back gate junctionless NAND gate flash memory adopts a metallic carbon nanotube gate array, and uses the carbon nanotube as a gate electrode of a storage unit transistor, so that the size of the gate is obviously reduced, and the density of a storage unit is favorably improved; the back-grid junctionless NAND flash memory also adopts a grid charge trapping mode, and replaces the traditional silicon doping channel with a two-dimensional semiconductor material channel, so that the control of the carbon nanotube grid to the channel current is easier; and because of adopting the horizontal channel form, compared with the existing vertical channel type memory, the memory structure of the invention is simpler. The manufacturing method of the back-grid junctionless NAND gate flash memory adopts a back-grid process, namely, the two-dimensional semiconductor material channel layer is manufactured firstly, and then the carbon nano tube grid array is manufactured, so that the barrier layer and the charge trapping layer surrounding the carbon nano tube grid can be obtained, and the charge trapping capacity of the grid can be further improved.
Drawings
Fig. 1 is a schematic structural diagram of a back-gate junction-free nand flash memory according to the present invention.
Fig. 2 is a schematic diagram showing the method for manufacturing a back-gate junction-free nand flash memory according to the present invention, in which an insulating layer, a two-dimensional semiconductor material channel layer, and a tunnel layer are sequentially formed on a substrate from bottom to top.
Fig. 3 is a schematic diagram illustrating a sacrificial layer formed on the tunnel layer by the method for manufacturing a back-gate junction-free nand flash memory according to the present invention.
Fig. 4 is a schematic diagram illustrating a carbon nanotube gate array formed on the sacrificial layer by the method for manufacturing a back-gate junction-free nand flash memory according to the present invention.
Fig. 5 is a schematic diagram illustrating wet etching of the sacrificial layer by the method for manufacturing a back-gate junction-free nand flash memory according to the present invention.
Fig. 6 is a schematic diagram illustrating a barrier layer formed around the outer side of the carbon nanotube according to the method for manufacturing a back-gate junction-free nand flash memory of the present invention.
FIG. 7 is a schematic diagram of a charge trapping layer formed by the method for fabricating a back-gate junction-free NAND flash memory according to the present invention.
Fig. 8 is a schematic diagram showing a protective layer formed to cover the gate charge trapping layer according to the method for manufacturing a back-gate junction-less nand flash memory of the present invention.
Fig. 9 is a schematic diagram showing the formation of source contact electrodes and drain contact electrodes in the method for manufacturing a back-gate junction-less nand flash memory according to the present invention.
Description of the element reference numerals
1 substrate
2 insulating layer
3 channel layer
4 carbon nanotubes
5 tunnel layer
6 charge trapping layer
7 barrier layer
8 protective layer
9 source contact electrode
10 drain contact electrode
11 electric charge
12 sacrificial layer
13 support layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a back gate non-junction nand gate flash memory, please refer to fig. 1, which shows a schematic structural diagram of the memory, comprising:
a substrate 1;
an insulating layer 2 located over the substrate 1;
the channel layer 3 is positioned on the insulating layer 2 and is made of two-dimensional semiconductor materials;
the carbon nanotube grid array is suspended above the channel layer 3 and comprises a plurality of carbon nanotubes 4 which are separately arranged, and the carbon nanotubes 4 are used as gate electrodes of transistors in the memory;
a gate trapping structure comprising a tunnel layer 5, a charge trapping layer 6 and a barrier layer 7; wherein the tunnel layer 5 is located above the channel layer 3, the barrier layer 7 surrounds the outer side surfaces of the carbon nanotubes 4, and the charge trapping layer 6 comprises a first portion surrounding the outer side surfaces of the barrier layer 7 and a second portion located above the tunnel layer 5 and in contact with the first portion;
a protective layer 8 covering the gate trapping structure;
and the source contact electrode 9 and the drain contact electrode 10 are respectively positioned at two ends of the carbon nanotube grid array and are respectively connected with the channel layer 3.
Specifically, the back-gate junctionless nand flash memory further comprises a plurality of gate contact electrodes respectively leading out the carbon nanotubes 4. As an example, during application, a voltage V is applied to the source contact electrode 9ssA positive voltage V is applied to the drain contact electrode 10ddA voltage V is applied to the gate contact electrodeg1、Vg2、……、Vgn、Vg(n+1). Wherein n is the number and represents the nth carbon nano tube.
By way of example, the substrate 1 includes, but is not limited to, a suitable semiconductor substrate such as silicon, germanium, silicon germanium, and the like, and the insulating layer 2 includes, but is not limited to, a suitable insulating material such as silicon oxide and the like. The channel layer 3 is made of a two-dimensional semiconductor material, and the thickness of the channel layer is 1-10 atomic layers. The two-dimensional semiconductor material is selected from MoS2、WS2、ReS2And SnO, in this example, MoS is preferably used2. The memory structure is simpler because the channel layer 3 is in a horizontal channel form.
As an example, the memory comprises a plurality of serial strings, each serial string comprises a memory cell string and a non-junction switch transistor respectively connected to two ends of the memory cell string; the memory cell string comprises a plurality of memory cell transistors connected in series; the carbon nanotube grid array corresponds to the serial, and each carbon nanotube in the carbon nanotube grid array is respectively used as a gate electrode of each transistor in the serial. In this embodiment, the switch transistor and the memory cell transistor both use carbon nanotube gates, and gate dielectric layers thereof both use the gate trapping structure.
As an example, the non-junction switching transistors connected to both ends of the memory cell string are a string selection transistor and a ground selection transistor, respectively. The number of the string selection transistors may be one or more, the number of the ground selection transistors may be one or more, and the number of the memory cell transistors in the memory cell string may be set as desired, for example, 24, 32, 48, or even more.
In this embodiment, each string corresponds to one channel, that is, each memory cell transistor and the switch transistor in one string share one channel layer 3. For different strings, their channel layers are isolated from each other, which may be achieved by patterning the channel layers as they are formed and depositing insulating material between adjacent channel layers.
In this embodiment, in the carbon nanotube grid array, the carbon nanotubes 4 are arranged in parallel on a horizontal plane above the channel layer 3, so that the transistors are arranged in sequence from left to right in a series. Of course, in other embodiments, the arrangement of the carbon nanotubes in the carbon nanotube grid array may be adjusted according to the need, and the scope of the present invention should not be limited herein.
Specifically, the carbon nanotube 4 is a metallic carbon nanotube. The carbon nano tube 4 has a tube diameter of 0.75-3 nm and a length of 100 nm-50 μm. The carbon nano tube 4 has a smaller tube diameter, so that the width of the grid electrode is favorably reduced, and the density of the storage unit is improved.
Specifically, in the gate trapping structure, the blocking layer and the charge trapping layer both surround the carbon nanotube gate, so that a stronger gate charge trapping capability can be obtained. As an example, the material of the charge trapping layer 6 includes at least one of nitride and hafnium oxide, and the material of the blocking layer and the tunneling layer are both high K dielectrics with a dielectric constant greater than 3.9, such as zirconium oxide, silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, and the like.
The back gate junctionless NAND gate flash memory adopts a metallic carbon nanotube gate array, and uses the carbon nanotube as a gate electrode of a storage unit transistor, so that the size of the gate is obviously reduced, and the density of a storage unit is favorably improved; the back-grid junctionless NAND flash memory also adopts a grid charge trapping mode, and replaces the traditional silicon doping channel with a two-dimensional semiconductor material channel, so that the control of the carbon nanotube grid to the channel current is easier; the blocking layer and the charge trapping layer surround the carbon nanotube gate, so that the charge trapping capability of the gate is stronger. And because of adopting the horizontal channel form, compared with the existing vertical channel type memory, the memory structure of the invention is simpler.
Example two
The invention also provides a manufacturing method of the back gate junctionless NAND gate flash memory, which comprises the following steps:
referring to fig. 2, a substrate 1 is provided, and an insulating layer 2, a two-dimensional semiconductor material channel layer 3 and a tunnel layer 5 are sequentially formed on the substrate 1 from bottom to top.
Specifically, the substrate 1 includes, but is not limited to, a suitable semiconductor substrate such as silicon, germanium, silicon germanium, and the like, and the insulating layer 2 includes, but is not limited to, a suitable insulating material such as silicon oxide and the like. The insulating layer may be formed, for example, by growing an oxide layer on a silicon substrate.
The channel layer 3 is made of a two-dimensional semiconductor material, and the thickness of the channel layer is 1-10 atomic layers. As an example, the two-dimensional semiconductor material is selected from MoS2、WS2、ReS2And SnO, in this example, MoS is preferably used2. The method of forming the channel layer 3 may be a deposition method such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), or other suitable processes.
The material of the tunnel layer 5 is a high-K dielectric with a dielectric constant greater than 3.9, such as zirconium oxide, silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, etc. The method for forming the channel layer 3 and the tunnel layer 5 may be Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), or other suitable processes.
Then, referring to fig. 3 and fig. 4, a sacrificial layer 12 is formed on the tunneling layer 5, and a carbon nanotube gate array is formed on the sacrificial layer 12; the carbon nanotube grid array comprises a plurality of carbon nanotubes 4 which are separately arranged and are used as gate electrodes of transistors in the memory.
Here, the sacrificial layer 12 means that it can be removed by wet etching.
As an example, the carbon nanotube grid array is formed on the sacrificial layer 12 by using a chemical vapor deposition method, wherein the material of the sacrificial layer 12 includes a carbon nanotube growth catalyst material. For example, the carbon nanotube growth catalyst material includes, but is not limited to, one or more of Ni, Ag, Fe, Co.
In this embodiment, a catalyst material is grown by using carbon nanotubes in a protective atmosphere, and a carbon source is introduced into the reaction chamber to form the carbon nanotube gate array by a chemical vapor deposition method. The protective atmosphere comprises N2、H2And Ar, the carbon source comprises but is not limited to carbon-containing gas such as methane, acetylene and the like.
Referring to fig. 5, wet etching is performed on the sacrificial layer 12 to suspend the carbon nanotube gate array, and portions of the sacrificial layer at two axial ends of the carbon nanotube 4 are reserved as a supporting layer 13. The support layer 13 is shown in fig. 5 with a dashed box in order to show the suspended state of the carbon nanotubes.
Referring to fig. 6, a barrier layer 7 surrounding the outer side of the carbon nanotube 4 is formed.
Specifically, the barrier layer 7 is a high-K dielectric with a dielectric constant greater than 3.9, such as zirconium oxide, silicon nitride, hafnium oxide, silicon oxide, aluminum oxide, or the like. The method for forming the barrier layer 7 may be a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), a Metal Organic Chemical Vapor Deposition (MOCVD), an Atomic Layer Deposition (ALD), or other suitable process. In the process of forming the barrier layer 7, a part of high-K dielectric may be deposited on the surface of the tunnel layer 5, but since the tunnel layer 5 also adopts the high-K dielectric, no adverse effect is generated.
Referring to FIG. 7, a charge trapping layer 6 is formed; the charge trapping layer 6 comprises a first portion surrounding the outer side of the blocking layer 7 and a second portion located above and in contact with the tunnel layer 5.
Specifically, the material of the charge trapping layer 6 includes at least one of nitride and hafnium oxide, and the method for forming the charge trapping layer 6 may be a deposition method such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), or other suitable processes.
Then, referring to FIG. 8, a protective layer 8 is formed overlying the charge trapping layer 6.
Specifically, the protective layer 8 is made of silicon oxide or other insulating materials.
Finally, referring to fig. 9, a source contact electrode 9 and a drain contact electrode 10 are formed at two ends of the carbon nanotube gate array and connected to the channel layer 3, and gate contact electrodes are formed to lead out the carbon nanotubes 4, respectively.
As an example, the method of forming the source and drain contact electrodes 9 and 10 includes the steps of: through holes penetrating the protective layer 8, the charge trapping layer 6 and the tunnel layer 5 are formed at corresponding positions, and the through holes are filled with a conductive material. The method of forming the gate contact electrode includes the steps of: through holes penetrating through the protection layer 8, the charge trapping layer 6 and the blocking layer 7 are formed at corresponding positions, and conductive materials are filled in the through holes.
The manufacturing method of the back-grid junctionless NAND gate flash memory adopts a back-grid process, namely, the two-dimensional semiconductor material channel layer is manufactured firstly, and then the carbon nano tube grid array is manufactured, so that the barrier layer and the charge trapping layer surrounding the carbon nano tube grid can be obtained, and the charge trapping capacity of the grid is stronger.
In summary, the back-gate junction-free nand gate flash memory of the invention adopts a metallic carbon nanotube gate array, and uses the carbon nanotube as the gate electrode of the memory cell transistor, thereby significantly reducing the gate size and being beneficial to improving the density of the memory cell; the back-grid junctionless NAND flash memory also adopts a grid charge trapping mode, and replaces the traditional silicon doping channel with a two-dimensional semiconductor material channel, so that the control of the carbon nanotube grid to the channel current is easier; and because of adopting the horizontal channel form, compared with the existing vertical channel type memory, the memory structure of the invention is simpler. The manufacturing method of the back-grid junctionless NAND gate flash memory adopts a back-grid process, namely, the two-dimensional semiconductor material channel layer is manufactured firstly, and then the carbon nano tube grid array is manufactured, so that the barrier layer and the charge trapping layer surrounding the carbon nano tube grid can be obtained, and the charge trapping capacity of the grid can be further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A back-gate junction-free nand flash memory, comprising:
a substrate;
an insulating layer over the substrate;
the channel layer is positioned on the insulating layer and made of two-dimensional semiconductor materials;
the carbon nano tube grid array is suspended above the channel layer and comprises a plurality of discrete carbon nano tubes, and the carbon nano tubes are used as gate electrodes of transistors in the memory;
a gate trapping structure comprising a tunnel layer, a charge trapping layer and a blocking layer; wherein the tunnel layer is located over the channel layer, the blocking layer surrounds the outer sides of the carbon nanotubes, and the charge trapping layer includes a first portion surrounding the outer sides of the blocking layer and a second portion located over the tunnel layer and in contact with the first portion;
a protective layer covering the gate trapping structure;
and the source contact electrode and the drain contact electrode are respectively positioned at two ends of the carbon nano tube grid array and are respectively connected with the channel layer.
2. The back-gate junction-free nand flash memory of claim 1, wherein: and a plurality of grid contact electrodes for respectively leading out the carbon nano tubes.
3. The back-gate junction-free nand flash memory of claim 1, wherein: the carbon nanotubes are metallic carbon nanotubes.
4. The back-gate junction-free nand flash memory of claim 1, wherein: the carbon nano tube has a tube diameter of 0.75-3 nm and a length of 100 nm-50 μm.
5. The back-gate junction-free nand flash memory of claim 1, wherein: the memory comprises a plurality of serial strings, wherein each serial string comprises a memory cell string and a knotless switch transistor respectively connected to two ends of the memory cell string; the memory cell string comprises a plurality of memory cell transistors connected in series; the carbon nanotube grid array corresponds to the serial, and each carbon nanotube in the carbon nanotube grid array is respectively used as a gate electrode of each transistor in the serial.
6. The back-gate junction-free nand flash memory of claim 5, wherein: the non-junction switch transistors connected to both ends of the memory cell string are a string selection transistor and a ground selection transistor, respectively.
7. The back-gate junction-free nand flash memory of claim 1, wherein: in the carbon nanotube grid array, the carbon nanotubes are arranged in parallel in a horizontal plane.
8. The back-gate junction-free nand flash memory of claim 1, wherein: the two-dimensional semiconductor material is selected from MoS2、WS2、ReS2And SnO.
9. The back-gate junction-free nand flash memory of claim 1, wherein: the material of the charge trapping layer comprises at least one of nitride and hafnium oxide, and the material of the blocking layer and the material of the tunnel layer are both high-K dielectrics with dielectric constants larger than 3.9.
10. A manufacturing method of a back gate junctionless NAND flash memory is characterized by comprising the following steps:
providing a substrate, and sequentially forming an insulating layer, a two-dimensional semiconductor material channel layer and a tunnel layer on the substrate from bottom to top;
forming a sacrificial layer on the tunneling layer;
forming a carbon nano tube grid array on the sacrificial layer; the carbon nanotube grid array comprises a plurality of carbon nanotubes which are separately arranged and are used as gate electrodes of transistors in the memory;
wet etching is carried out on the sacrificial layer, so that the carbon nano tube grid array is suspended, and parts of the sacrificial layer positioned at the two axial ends of the carbon nano tube are reserved as supporting layers;
forming a barrier layer surrounding the outer side surface of the carbon nano tube;
forming a charge trapping layer; the charge trapping layer includes a first portion surrounding an outer side of the blocking layer and a second portion over and in contact with the tunnel layer;
forming a protective layer covering the charge trapping layer;
and forming a source contact electrode and a drain contact electrode which are respectively positioned at two ends of the carbon nanotube grid array and connected with the channel layer, and forming grid contact electrodes respectively leading out the carbon nanotubes.
11. The method of claim 10, wherein the method comprises: and forming the carbon nanotube grid array on the sacrificial layer by adopting a chemical vapor deposition method, wherein the material of the sacrificial layer comprises a carbon nanotube growth catalyst material.
12. The method of claim 11, wherein the method comprises: the carbon nano tube growth catalyst material comprises one or more of Ni, Ag, Fe and Co.
13. The method of claim 10, wherein the method comprises: the method of forming the source and drain contact electrodes includes the steps of: and forming a through hole penetrating through the protective layer, the charge trapping layer and the tunnel layer, and filling a conductive material in the through hole.
14. The method of claim 10, wherein the method comprises: the method of forming the gate contact electrode includes the steps of: and forming a through hole penetrating through the protective layer, the charge trapping layer and the blocking layer, and filling a conductive material in the through hole.
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| CN114388529A (en) * | 2020-01-14 | 2022-04-22 | 长江存储科技有限责任公司 | Channel structure including tunneling layer with adjusted nitrogen weight percentage and method of forming the same |
| KR20210154602A (en) * | 2020-06-12 | 2021-12-21 | 삼성전자주식회사 | Semiconductor device and a method for manufacturing the same |
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| CN101124638A (en) * | 2004-12-06 | 2008-02-13 | 哈佛大学 | Nanoscale wire-based data storage |
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