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CN108231892B - 具有弧形底面的合并的外延部件的半导体器件及其制造方法 - Google Patents

具有弧形底面的合并的外延部件的半导体器件及其制造方法 Download PDF

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CN108231892B
CN108231892B CN201711166177.9A CN201711166177A CN108231892B CN 108231892 B CN108231892 B CN 108231892B CN 201711166177 A CN201711166177 A CN 201711166177A CN 108231892 B CN108231892 B CN 108231892B
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semiconductor component
semiconductor
substrate
semiconductor device
fins
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CN108231892A (zh
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李宜静
游政卫
周立维
郭紫微
游明华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例公开了一种半导体器件及其形成方法。该半导体器件包括衬底,位于衬底上方的两个半导体鳍和位于两个半导体鳍上方的半导体部件。半导体部件包括两个下部和一个上部。两个下部分别直接位于两个半导体鳍上方。上部位于两个下部上方。上部的底面具有弧形的截面形状。

Description

具有弧形底面的合并的外延部件的半导体器件及其制造方法
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及半导体器件及其形成方法。
背景技术
半导体集成电路(IC)产业经历了指数型增长。IC材料和设计上的技术进步产生了一代又一代IC,其中,每一代都具有比前一代更小且更复杂的电路。在IC发展过程中,功能密度(即,每单位芯片面积上互连器件的数量)通常增大了而几何尺寸(即,使用制造工艺可以制造的最小组件(或线))减小了。这种按比例缩小工艺通常因提高生产效率和降低相关成本而提供益处。这种按比例缩小工艺还增大了加工和制造IC的复杂度。
例如,随着半导体器件按比例逐渐缩小,已经使用外延(epi)半导体材料来实现应变的源极/漏极部件(例如,应力源区)以提高载流子的迁移率且提高器件的性能。形成具有应力源区的金属氧化物半导体场效应晶体管(MOSFET)通常外延生长硅(Si)以形成用于n型器件的突起的S/D部件,且外延生长硅锗(SiGe)以形成用于p型器件的突起的S/D部件。已经实施针对这些S/D部件的形状、配置和材料的各种技术以进一步提高晶体管器件性能。尽管形成S/D的现有方法通常能够满足它们的预期目的,但它们并非在所有方面都完全令人满意。例如,随着晶体管按比例缩小,S/D接触电阻已经成为电路性能中日益突出的因素。非常期望具有降低的S/D接触电阻,因为其导致降低的功率消耗和更快的电路速度。
发明内容
根据本发明的一个方面,提供了一种半导体器件,包括:衬底;两个半导体鳍,位于所述衬底上方;以及半导体部件,位于所述两个半导体鳍上方,其中:所述半导体部件包括两个下部和一个上部;所述两个下部分别直接位于所述两个半导体鳍上方;所述上部位于所述两个下部上方;和所述上部的底面具有弧形的截面形状。
根据本发明的另一个方面,提供了一种方法,包括:提供了包括衬底和从所述衬底延伸的两个鳍的器件;蚀刻所述两个鳍,从而形成两个沟槽;在所述两个沟槽中外延生长第一半导体部件;在第一生长条件下在所述第一半导体部件上方外延生长第二半导体部件,其中,所述第二半导体部件横向合并以形成合并部分;以及在所述合并部分的尺寸达到目标尺寸之后,在第二生长条件下外延生长所述第二半导体部件,其中,在所述第二生长条件下所述第二半导体部件的晶向[100]与[111]之间的生长速率比大于在所述第一生长条件下的所述生长速率比。
根据本发明的又一个方面,提供了一种形成半导体器件的方法,包括:提供具有衬底和从所述衬底处延伸的至少两个鳍的器件;蚀刻所述至少两个鳍,从而形成至少两个沟槽;在所述至少两个沟槽中外延生长第一半导体部件;在第一生长条件下,在所述第一半导体部件上方外延生长第二半导体部件,其中,所述第二半导体部件横向合并,从而形成合并部分;在所述合并部分的厚度达到目标尺寸之后,在不同于所述第一生长条件的第二生长条件下外延生长所述第二半导体部件,从而在所述合并部分的底面中形成弧形形状;以及实施蚀刻工艺以减小所述第二半导体部件的宽度。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A、图1B、图1C、图1D和图1E示出根据本发明的各个方面构造的半导体器件的各个实施例。
图2示出根据本发明的各个方面形成半导体器件的方法的框图。
图3示出根据图2的方法的实施例在中间制造步骤中的半导体器件的立体图。
图4A、图4B、图4C、图5A、图5B、图5C、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图12A、图12B、图13A和13B示出根据一些实施例的根据图2的方法形成目标半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
本发明在各个实施例中总体涉及半导体器件及其形成方法。特别地,本发明涉及在包括具有鳍式沟道的FET的场效应晶体管(FET)(称为FinFET)中形成凸起的S/D部件。在一些实施例中,本发明提供作为合并多个外延部件的结果的凸起的S/D部件,其中凸起的S/D部件具有弧形底面。此外,凸起的S/D部件可以具有平坦或接近平坦的顶面。当蚀刻凸起的S/D部件以形成诸如S/D接触件的导电部件时,具有的弧形底面在凸起的S/D部件中提供大的体积。该大体积有助于减小凸起的S/D部件和导电部件之间的界面电阻。
图1A示出根据本发明的各个方面构造的半导体器件100。器件100可以是在处理IC或其部分期间制造的中间器件,IC或其部分可以包括:静态随机存取存储器(SRAM)和/或逻辑电路;诸如电阻器、电容器和电感器的无源组件;以及诸如p型FET(PFET)、n型FET(NFET)、FinFET、金属氧化物半导体场效应晶体管(MOSFET)和互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储器单元和它们的组合的有源组件。此外,本发明的各个实施例中提供的包括晶体管、鳍、栅极堆叠件,器件区的各个部件和其他部件是为了简化和容易理解,但不必将实施例限制于任何类型的器件、任何数目的器件、任何数目的区域或任何配置的结构或区域。即使在各个实施例中示出为FinFET器件,但在可选实施例中,器件100还可以是平面FET器件和其他多栅极器件。
图1A是器件100在其S/D区域中的截面图。参考图1A,在本实施例中,器件100包括衬底102,位于衬底102上方的隔离结构104和位于衬底102上方的两个或多个鳍106(图1A中示出两个)。鳍106垂直于“x-z”平面纵向延伸。尽管未示出,鳍106的一些部分可以突出在隔离结构104之上。此外,在该实施例中,器件100包括外延生长的半导体部件(或外延部件)122。外延部件122包括上部122U和两个或多个下部122L(图1A中示出两个)。下部122L设置在相应的鳍106上方并且至少部分地被鳍侧壁介电层110围绕。在本实施例中,下部122L在“z”方向(鳍高度方向)上低于鳍侧壁介电层110。各下部122L通过上部122U彼此物理连接。上部122U提供平坦或接近平坦的顶面124。在实施例中,顶面124大致平行于衬底102的顶面102'。在本实施例中,上部122U的底面125在“x-z”平面中具有弧形的截面形状。下文中将进一步描述器件100的各个部件。
在本实施例中衬底102是硅衬底。可选地,衬底102可以包括诸如锗的其他元素半导体;包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体;或它们的组合。在另一可选实施例中,衬底102是诸如具有掩埋介电层的绝缘体上半导体(SOI)。在实施例中,衬底102包括用于形成有源器件的诸如p阱和n阱的有源区。
鳍106可以是用于形成PFET的p型鳍或用于形成NFET的n型鳍。鳍106可以包括与衬底102大致相同的半导体材料。尽管在图1A中未示出,每个鳍106包括沟道区和夹置沟道区的两个S/D区。图1A示出器件100的穿过鳍106的S/D区中的一个切割得到的截面图。通过隔离结构104分离鳍106。隔离结构104可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。在一些实施例中,隔离结构104可以是浅沟槽隔离(STI)部件。介电层110设置在隔离结构104上方且与鳍106的S/D区相邻。介电层110至少部分地围绕下部122L。在实施例中,介电层110包括诸如氮化硅、氮氧化硅或碳氮化硅的氮化物。在介电层110和下部122L上方设置上部122U。
在实施例中,下部122L和上部122U均包括掺杂有诸如磷(P)或砷(As)的n型掺杂剂的硅,从而用于形成NFET器件。此外,上部122U包括比下部122L更高的n型掺杂剂浓度。在一个实例中,上部122U包括掺杂有磷的硅,掺杂剂浓度在从1e21cm-3至5e21cm-3的范围内,而下部122L包括掺杂有磷的硅,掺杂剂浓度在从1e20cm-3至1e21cm-3的范围内。在另一实施例中,下部122L和上部122U均包括掺杂有诸如硼(B)或铟(In)的p型掺杂剂的硅锗,从而用于形成PFET器件。在另一实施例中,上部122U包括比下部122L更高浓度的p型掺杂剂。
在图1A所示的实施例中,鳍106具有沿鳍宽度方向(“x”方向)的鳍间距“p”。鳍间距“p”还是下部122L的间距。在实施例中,调节间距“p”,从而用于工艺节点并且用于形成外延部件122的特定形状。如果“p”太小,则上部122U可能在外延生长工艺中较早地合并,从而使得其倾向于生长成菱形形状,而不是具有平坦的顶面和弧形底面的形状。如果“p”太大,则上部122U可能根本不合并。在实例中,间距“p”调整为在从30纳米(nm)至50nm的范围内。此外,上部122U具有从弧形底面125的峰顶至顶面124的垂直厚度(沿“z”方向)“h”。在实例中,厚度“h”在从25nm至55nm的范围内。在各个实施例中,介电层110具有沿着“z”方向的高度“d”,并且高度“d”可以在从5nm至25nm的范围内。如下面将讨论的,高度“d”有助于外延部件122的各种形状和尺寸。下部122L均具有在下部122L的约半高处测得的沿着“x”方向的宽度“c”。在一些实施例中,宽度“c”可以在从6nm至15nm的范围内。此外,下部122L均具有沿“z”方向的高度“e”。在一些实施例中,高度“e”可以在从3nm至15nm的范围内。
仍参考图1A,在上部122U、侧壁介电层110和隔离结构104之间存在间隔。可以用层间介电(ILD)层完全或部分填充该间隔(图1A中未示出,但参见图13A的部件130)。在实施例中,ILD层包括与侧壁介电层110不同的材料。例如,ILD层可以包括原硅酸四乙酯(TEOS)氧化物、掺杂或未掺杂的硅酸盐玻璃或熔融石英玻璃(FSG),而侧壁介电层110包括氮化物。
如图1A所示,底面125的弧形形状可以远离衬底102向上延伸。在可选实施例中,弧形可以朝向衬底102向下延伸,如稍后将讨论的图1D所示。在本实施例中,弧形具有沿着“x”方向的跨度“b”,并且具有沿着“z”方向的高度(或上升)“a1”。在间距“p”在从30nm至50nm的实例中,跨度“b”为约20nm至40nm,而高度“a1”为约0nm至10nm。在本实施例中,底面125具有浅弧形形状,即弧的高度/跨度比a1/b小于0.5。在另一实施例中,a1/b的比率小于0.25。具有小的高度与跨度比的优势和效果将通过参考图1B变得清楚。
参考图1B,在实施例中,器件100还包括形成在外延部件122上方的导电部件126。特别地,在该实施例中,导电部件126部分地嵌入在外延部件122的上部122U中。在本实施例中,导电部件126包括阻挡层126a和位于阻挡层上方的导体(例如,金属)126b。例如,导体126b可以包括铝(Al)、钨(W)、铜(Cu)、钴(Co)、它们的组合或其他合适的材料;并且阻挡层126a可以包括诸如TaN或TiN的金属氮化物。导电部件126可以包括额外的层。在另一实施例中,导电部件126包括掺杂的多晶硅。导电部件126可以是S/D接触件或S/D局部互连线。导电部件126的形成包括在外延部件122中蚀刻沟槽并且将导电部件126的层(或多层)沉积到沟槽中。可以蚀刻沟槽以具有进入外延部件122的深度“q”,其小于上部122U的厚度“h”(沿着“z”方向)。在一些实施例中,深度“q”在从15nm到25nm的范围内。尽管未示出,但是在一些实施例中,在导电部件126和外延部件122之间可能存在硅化物部件(或硅化物)。
在各个实施例中,与传统结构相比,导电部件126和外延部件122之间的大的界面面积提供了减小的接触电阻。传统的外延部件典型地具有菱形的截面轮廓并且彼此隔离(未合并),或者合并成具有尖锐的拱顶的形状,如图1B中的虚线150所示。隔离的外延部件不提供与合并的外延部件一样大的界面面积。例如,当形成用于沉积导电部件126的沟槽时,合并的外延部件中的尖锐的拱顶不提供足够的体积以用于蚀刻。例如,当外延部件的垂直厚度“v”小于沟槽深度“q”时,将蚀穿外延部件。如果蚀穿外延部件,则导电部件126的一些区域将不接触外延部件,导致增加的接触电阻。
这种过蚀刻可能对于当今的先进的工艺节点(其中晶体管形貌的纵横比正在上升)变得更严重。纵横比是指晶体管形貌峰(topography peak)(例如,栅极堆叠件)的高度与相邻峰之间的间隔之间的比率。在一些实例中,随着器件集成的继续,该纵横比已经变为10或更大。在用于S/D接触件或局部S/D互连线的蚀刻期间,可以针对特定的过蚀刻来调整化学蚀刻剂或蚀刻时间,以便到达通常位于晶体管形貌底部的S/D部件。在外延部件中具有的尖锐的拱顶可能不提供足够大的体积来承受这种过蚀刻。相反,具有小的高度与跨度比(例如,0.25或更小)的弧形底部125有利地增加了合并的外延部件122的体积以承受这种过蚀刻。
参考图1C,其中示出器件100的另一实施例,其中底表面125是平坦的或接近平坦的。该实施例的其他方面与图1B的相同或相似。
参考图1D,其中还示出器件100的另一实施例,其中底面125具有向下延伸的弧形形状。弧形具有沿“x”方向的跨度“b”和沿“z”方向的高度(或深度)a2。在一些实施例中,高度与跨度比a2/h小于0.5,诸如小于0.25。在实施例中,跨度“b”在20nm至40nm的范围内,高度“a2”在从0nm至10nm的范围内。该实施例的其他方面与图1B的相同或相似。在图1B、图1C和图1D的每个中,导电部件126示出为完全或部分地嵌入在上部122U中。然而,这并非限制。在一些其他实施例中,导电部件126可以设置在外延部件122的顶面124上。
参考图1E,在另一实施例中,器件100包括区域102a和相邻区域102b。区域102a包括上面讨论的各个部件106和122。区域102b包括鳍146和位于鳍146上方的外延部件152。外延部件152包括下部152L和位于下部152L上方的上部152U。介电层110至少部分地围绕下部152L。在本实施例中,下部152L在“z”方向上低于鳍侧壁介电层110。在介电层110上方设置上部152U。此外,在该实施例中,器件100包括与外延部件122和152两者连接的导电部件128。导电部件128包括阻挡层128a和位于阻挡层128a上方的导体(例如,金属)128b。阻挡层128a和导体128b可以分别具有与阻挡层126a和导体126b相同或类似的组成。在所示的该实施例中,外延部件152具有菱形截面轮廓,并且导电部件128的部分设置在外延部件152的侧面上方。特别地,在该实施例中,在外延部件122U和152U之间且在外延部件122U和/或外延部件152U的最宽部分(沿着“x”方向)下面设置导电部件128的部分。在另一实施例中,区域102b可以包括外延部件,其形状类似于外延部件122,即具有平坦或接近平坦的顶面和弧形底面。在实施例中,区域102a中的部件形成n型晶体管(例如,NMOS),并且区域102b中的部件形成p型晶体管(例如,PMOS)。在可选实施例中,区域102a中的部件形成p型晶体管(例如,PMOS),且区域102b中的部件形成n型晶体管(例如,NMOS)。
图2示出根据本发明的各个方面形成半导体器件(例如,半导体器件100)的方法200的框图。方法200是实例,并且除了权利要求中的明确列举之外,不旨在限制本发明。可在方法200之前、期间和之后提供额外的操作,并且对于方法的额外的实施例,可替换、消除或重新定位描述的一些操作。下面结合图3至图13B描述方法200,图3至图13B是根据本发明的各个方面的半导体器件100的立体图和截面图。
在操作202中,方法200(图2)在中间制造阶段接收器件100。图3示出器件100的立体图。图4A、图4B和图4C示出分别沿着图3中的线“1-1””、线“2-2”和线“3-3”的器件100的截面图。“1-1”线在鳍106的S/D区域中的“x-z”平面中切割器件100。“2-2”线沿着鳍106的长度在“y-z”平面中切割器件100。“3-3”线在鳍106外部的“y-z”平面中切割器件100。整体地参考图3、图4A、图4B和图4C,器件100包括衬底102,位于衬底102上方的隔离结构104和从衬底102延伸且穿过隔离结构104的两个鳍106。两个鳍106均具有两个源极/漏极(S/D)区106a和介于S/D区106a之间的沟道区106b。器件100还包括包裹(engage)沟道区106b中的鳍106的栅极堆叠件108。特别地,栅极堆叠件108在鳍106的多个侧面上包裹鳍106,从而形成多栅极器件(在这种情况下为FinFET)。
可以使用包括光刻和蚀刻工艺的合适的工艺来制造鳍106。光刻工艺可以包括在衬底102上方形成抗蚀剂(光刻胶),将抗蚀剂曝光于图案,实施曝光后烘烤工艺,以及使抗蚀剂显影以形成包括抗蚀剂的掩模元件。然后使用掩模元件在衬底102内蚀刻凹槽,从而在衬底102上留下鳍106。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的工艺。例如,干蚀刻工艺可以实施含氧气体、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBr3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。例如,湿蚀刻工艺可包括在以下蚀刻剂中的蚀刻:稀释的氢氟酸(DHF);氢氧化钾(KOH)溶液;氨水;含氢氟酸(HF)、硝酸(HNO3)和/或醋酸(CH3COOH)的溶液;或其他合适的湿蚀刻剂。还可以使用双重图案化光刻(DPL)工艺形成鳍106。形成鳍106的方法的许多其他实施例可以是合适的。
通过在衬底102中蚀刻沟槽(例如,作为鳍106的形成工艺的部分)来形成隔离结构104。然后可以用隔离材料填充沟槽,接着是化学机械平坦化(CMP)工艺。诸如场氧化物、硅的局部氧化(LOCOS)和/或其他合适的结构的其他隔离结构是可能的。隔离结构104可包括多层结构,例如,具有一个或多个热氧化物衬垫层。
栅极堆叠件108包括栅极介电层和栅电极层。栅极介电层可以包括氧化硅或诸如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇和钛酸锶的高k介电材料。可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其他合适的方法来形成栅极介电层。栅电极层包括多晶硅,并且可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)的合适的沉积工艺来形成。在一些实施例中,栅电极层包括n型或p型功函层和金属填充层。例如,n型功函层可以包括诸如钛、铝、碳化钽、碳氮化钽、氮硅化钽或它们的组合的具有足够低的有效功函的金属。例如,p型功函层可以包括诸如氮化钛、氮化钽、钌、钼、钨、铂或它们的组合的具有足够大的有效功函的金属。例如,金属填充层可以包括铝、钨、钴、铜和/或其他合适的材料。可以通过CVD、PVD、镀法和/或其他合适的工艺形成栅电极层。在一些实施例中,栅极堆叠件108是牺牲栅极结构,即,为最终栅极堆叠件预留位置(placeholder)。在一些实施例中,栅极堆叠件108包括在其栅极介电层与鳍106之间的界面层。界面层可以包括诸如氧化硅或氮氧化硅的介电材料并且可以通过化学氧化、热氧化、ALD、CVD和/或其他合适的电介质形成。栅极堆叠件108可以包括诸如硬掩模层的其他层。
在操作204处,方法200(图2)在相应S/D区106a中的鳍106的侧壁上形成介电层110。图5A、图5B和图5C示出在制造步骤之后分别沿着图3的线“1-1”、线“2-2”和线“3-3”的器件100的截面图。参考图5A、图5B和图5C,介电层110可以包括单层或多层结构,并且可以包括诸如氮化硅(SiN)或氮氧化硅的介电材料。可以通过CVD、PECVD、ALD、热沉积或其他合适的方法形成介电层110。在本实施例中,还在栅极堆叠件108的侧壁上设置介电层110。在实施例中,操作204包括沉积工艺,接着是蚀刻工艺。例如,可以在器件100上方沉积介电材料作为覆盖隔离结构104、鳍106和栅极堆叠件108的毯状层。然后,可以实施各向异性蚀刻工艺以从隔离结构104的顶面、鳍106的顶面和栅极堆叠件108的顶面处去除介电材料的部分,从而在鳍106和栅极堆叠件108的侧壁上留下介电材料的剩余部分来作为介电层110。在实施例中,鳍106的侧壁上的介电层110具有约5nm至25nm的高度。
在操作206中,方法200(图2)选择性地蚀刻鳍106的S/D区106a以在其中形成沟槽(或凹槽)114。图6A和图6B示出在制造步骤之后分别沿着图2的线“1-1”、线“2-2”的器件100的截面图。参考图6A和6B,在本实施例中,鳍106被蚀刻为低于隔离结构104的顶面。操作206可包括一种或多种光刻工艺和蚀刻工艺。例如,光刻工艺可以形成覆盖器件100的不欲被蚀刻的区域的掩模元件。掩模元件提供开口,通过该开口蚀刻鳍106。可以通过干法蚀刻工艺、湿法蚀刻工艺或其他蚀刻技术来蚀刻鳍106。在本实施例中,选择性地调整蚀刻工艺以去除鳍106的材料,而栅极堆叠件108、介电层110和隔离结构104保持基本不变。操作206形成四个沟槽114,其中,在栅极堆叠件108的每侧上具有两个沟槽。每个沟槽114可以具有锥形截面轮廓(在“x-z”平面中),其中,开口在其底部处比在其顶部处更宽。在蚀刻工艺之后,可以实施清洁工艺,其用清洁化学品清洁沟槽114,以使其中的各个表面准备用于后续的外延生长工艺。清洁化学品可以是氢氟酸(HF)溶液、稀释的HF溶液或其他合适的清洁溶液。
在操作208处,方法200(图2)在四个沟槽114中生长四个外延部件122L,每个沟槽中有一个(图7A和7B)。外延部件122L部分地填充相应的沟槽114。外延生长工艺可以是具有硅基前体的LPCVD工艺、选择性外延生长(SEG)工艺或循环沉积和蚀刻(CDE)工艺。例如,可以将二氯甲硅烷(SiH2Cl2)作为前体、利用LPCVD来生长硅晶体。作为另一实例,可以使用氯化氢(HCl)作为蚀刻气体并且锗烷(GeH4)和氢气(H2)的气体混合物(在H2中包含约1%至约10%的GeH4)作为沉积气体利用CDE工艺形成硅锗晶体。调整介电层110的高度以促进外延部件122L生长至期望的高度,而没有太多的横向生长。在各个实施例中,外延部件122L生长为具有从3nm至15nm的高度。外延部件122L包括适于形成凸起的S/D部件的半导体材料。在实施例中,外延部件122L包括掺杂有一种或多种p型掺杂剂(诸如硼或铟)的硅锗(SiGe)。在实施例中,外延部件122L包括掺杂有一种或多种n型掺杂剂(诸如磷或砷)的硅。可以与外延生长工艺原位或非原位地实施掺杂。
在操作210处,方法200(图2)在下部外延部件122L(图8A和8B)上方生长上部外延部件122U。在本实施例中,利用与外延部件122L中相同的半导体材料生长外延部件122U,但是具有不同的掺杂剂浓度。例如,外延部件122L和122U均可以包括用n型掺杂剂掺杂的硅,但是外延部件122U具有更高浓度的n型掺杂剂。对于另一实例,外延部件122L和122U均可以包括用p型掺杂剂掺杂的硅锗,但是外延部件122U具有更高浓度的p型掺杂剂。类似于外延部件122L的形成,可以使用LPCVD、SEG或CDE技术形成外延部件122U。图8A和图8B是在该制造阶段处分别沿图3的线“1-1”和“2-2”的器件100的截面图。
如图8A和8B所示,外延部件122U填充相应沟槽114中的剩余间隔,并且一旦它们从相应沟槽114生长出,则进一步横向扩展。如图8A所示,因为外延部件122的生长速率沿着不同的晶向(例如,硅晶体的[100]、[111]和[110]方向)不同,所以随着外延部件122U生长得更高和更宽,它们开始合并。参考图8A,为了方便讨论,外延部件122U合并成连接的外延部件,还称为外延部件122U。外延部件122U的合并部分在外延部件122U的接近中间处具有垂直厚度“t”,并且在与合并部分的相对两侧上具有s1的侧面膨胀。沿着“x”方向从沟槽114的侧壁(图6A)测量侧面膨胀s1
在该制造阶段处,外延部件122U不具有平坦的顶面和浅弧形底面。相反,外延部件122U具有带下降部分116的弯曲顶面115,以及具有大的高度与跨度比的尖或凹的底面117。例如,形状117的高度与跨度比大于0.5。本发明的发明人已经发现,在同一外延生长条件下生长的外延部件122U不可能导致其具有平坦的顶面和浅的弧形底面。
在操作212处,方法200(图2)改变外延部件122U的生长条件,并且继续生长外延部件122U以具有大致平坦的顶面124和浅的弧形底面125,如图9A所示,图9A是沿着图3的线“1-1”的器件100的截面图。图9B示出在该制造阶段处沿着图3的线“2-2”的器件100的截面图。外延部件122U具有在鳍106的顶面下方的高度S11和在鳍106的顶面之上的高度S22。在各个实施例中,高度S11可以大于、小于或等于高度S22。在实施例中,高度S11在45nm至65nm的范围内。在实施例中,当外延部件122U的合并部分达到目标尺寸时,例如当该合并部分沿着“x”方向的横向尺寸达到特定值(例如,间距“p”的至少1.5倍)时,或者当其垂直厚度“t”达到尺寸的目标范围(诸如5nm至10nm)时,方法200从操作210切换到操作212。
在实施例中,操作212使用与操作210不同的沉积前体或不同的蚀刻气体。在另一实施例中,操作212使用与操作210不同(在类型或数量上)的蚀刻气体,但是具有相同的沉积前体。在又一实施例中,在与操作210不同的温度下实施操作212。操作212中的生长条件导致晶向[100]和[111]之间的生长速率比在操作210中的更大。例如,可以调整操作210以有利于晶向[111]的生长,以便形成外延部件122的合并部分,而可以调整操作212以有利于晶向[100]的生长以填充下降部分116和凹形117(图8A)。本发明的发明人已经发现了实现上述目的的各种条件。例如,他们发现,当温度在650和720摄氏度之间时,硅晶体沿[100]方向的生长速率大于或等于硅晶体沿[111]方向的生长速率。下面讨论一些其他生长条件。
在实施例中,操作210使用二氯甲硅烷(SiH2Cl2)(还称为DCS)作为前体形成硅晶体以生长外延部件122U。为了进一步说明该实施例,操作212向前体中添加硅烷以在硅晶体[100]方向上具有更高的生长(或沉积)速率。在实施例中,硅烷是SiH4。在实施例中,操作212中的SiH4与DCS的比率在约0.005至约0.05的范围内。在另一实施例中,操作210和212两者使用HCl作为蚀刻气体,并且操作212降低HCl气体的流速以减少其对晶体[100]方向的蚀刻效果。
在另一实施例中,操作210使用GeH4和H2的气体混合物作为沉积气体并且使用HCl作为蚀刻气体来形成硅锗晶体,以生长外延部件122U。为了进一步说明该实施例,操作212降低HCl的流速,从而使得硅锗在[100]方向上比在其他方向上生长得更快。在实施例中,操作212中的HCl流速在约100至约400标准立方厘米每分钟(sccm)的范围内。
在各个实施例中,可以在从200托至350托的范围内的压力处实施操作210和212。
凭借操作208、210和212,器件100提供为具有凸起的S/D部件122,凸起的S/D部件122具有浅弧形底面125和平坦或接近平坦的顶面124。如图1A至图1D所示,浅弧形底面125可以是任何一种形状。
在实施例中,侧壁介电层110的高度还可以用于控制上部122U的垂直体积(参见操作204中所讨论的)。例如,当侧壁介电层110较低时,上部122U更早地合并,导致沿着“z”方向的更大的厚度。另一方面,当侧壁介电层110较高时,上部122U稍后合并,导致沿“z”方向的较小厚度。
仍参考图9A,在一些实施例中,在操作212期间,外延部件122U横向扩展。例如,外延部件122U的侧面尺寸“s2”变得大于“s1”。这是因为在这些实施例的操作212中的生长条件没有完全抑制外延部件122沿晶体[110]方向的生长。在一些情况下,这种侧面膨胀是不期望的,因为它可能使相邻的S/D区域短接,造成器件故障。例如,当外延部件122是SRAM单元的部分时,器件密度可能是高的,并且可能需要严格控制相邻SRAM单元之间的间隔。在本实施例中,方法200(图2)实施操作214以修整外延部件122的侧面尺寸。
在实施例中,操作214对器件100实施蚀刻工艺。调整蚀刻工艺以减小外延部件122的宽度(沿着“x”方向),而对外延部件122的厚度(沿着“z”方向)没有太大的影响。在实施例中,蚀刻工艺使用GeH4气体和HCl气体的混合物作为蚀刻剂。在又一实施例中,将蚀刻剂中的GeH4和HCl之间的比例调整为0.5至1.2。例如,可以通过将引入至工艺室中的GeH4气体和HCl气体的流速控制在0.5至1.2的范围内来调整GeH4和HCl之间的比率。可以在实施部件122外延生长的同一工艺室中原位实施蚀刻工艺。在可选实施例中,可以异位(ex-situ)实施蚀刻工艺。在实施例中,可以在650摄氏度至750摄氏度的范围内的温度下和在5托至100托的压力下实施蚀刻工艺。在各个实施例中,调整操作214的化学蚀刻剂、温度和压力以减小外延部件122的宽度,而不会显著减小外延部件122的厚度。结果,外延部件的侧面尺寸减小到如图10A所示的“s3”(s3<s2)。在实施例中,侧面尺寸s3甚至变得小于侧面尺寸s1(s3<s1)。此外,在该制造阶段,由于蚀刻工艺,外延部件122U在鳍106的顶面之上的高度可以从S22缩小至S33,即S33<S22。在实施例中,S33在3nm至12nm的范围内。
在操作216处,方法200(图2)对器件100实施进一步的工艺。这包括各个工艺。在一个实例中,在外延部件122U上形成硅化物或锗硅化物。例如,可以通过在外延部件122U上方沉积金属层、对金属层进行退火,使得金属层与外延部件122U中的硅反应以形成金属硅化物,然后去除未反应的金属层来形成诸如硅化镍的硅化物。
在另一实例中,如图11B所示,操作216用最终的栅极堆叠件108a代替栅极堆叠件108。为了进一步说明该实例,图3至图10B中的栅极堆叠件108是具有伪栅极介电层(例如,氧化硅)和伪栅电极层(例如,多晶硅)的用于预留位置的部件(placeholder),而栅极堆叠件108a是包括高k栅极介电层、适当的n型或p型功函层和金属填充层的高k金属栅极。高k栅极介电层、功函层和金属填充层可以使用参考图3讨论的合适的材料。为了进一步说明该实例,操作216可以在衬底102上方沉积层间介电(ILD)层130以覆盖其上的形貌(参见图11A和11B)。ILD层130可以包括诸如原硅酸四乙酯(TEOS)氧化物、掺杂或未掺杂的硅酸盐玻璃、熔融石英玻璃(FSG)和/或其他合适的介电材料的材料。可以通过PECVD工艺、可流动CVD(FCVD)或其他合适的沉积技术来沉积ILD层130。在一些实施例中,ILD层130可填充弧形底面125、隔离结构104和两个相对的鳍侧壁介电层110之间的间隔。在可选实施例中,ILD层130可能不能流入该间隔内,导致位于弧形底面125下方的空腔(或开放空间)。在一些实施例中,可以在沉积ILD层130之前,在外延部件122和隔离结构104上方沉积具有诸如氮化硅的介电材料的接触蚀刻停止层(未示出)。在沉积ILD层130之后,操作216使用一次或多次蚀刻工艺去除栅极堆叠件108,并且使用一次或多次沉积工艺形成最终的栅极堆叠件108a以代替栅极堆叠件108,从而产生如图11A和图11B所示的器件100。
在另一实例中,如图13A和图13B所示,操作216形成部分地嵌入在外延部件122U中的导电部件126。这涉及各个工艺。例如,如图12A和图12B所示,操作216可以实施一次或多次光刻工艺和蚀刻工艺以形成穿过ILD层130的沟槽(或接触孔)127。沟槽127暴露外延部件122U(或其上的硅化物或锗硅化物,如果已经对外延部件122U实施硅化工艺)。在本实施例中,沟槽127延伸至外延部件122U内达到深度“q”。在高密度IC中,器件形貌的纵横比(例如,栅极堆叠件108a的高度和相邻栅极堆叠件之间的距离之间的比率)可以是高的(诸如大于10:1)。为了确保导电部件126和外延部件122之间在IC的大面积上的良好接触,当形成沟槽127时,期望特定的过蚀刻。例如,在IC的某个位置处,沟槽深度“q”可以在从15nm至25nm的范围内。在外延部件的底面是尖锐的拱顶(如图12A的虚线150所示)的传统器件中,沟槽127将穿过外延部件。这将减小导电部件126和传统的外延部件之间的界面面积。在本实施例中,外延部件122形成为具有浅弧形底面125,这有利地增加外延部件122的厚度“h”。在各个实施例中,厚度“h”设计为大于沟槽深度“q”。例如,厚度“h”设计为25nm或更大。在实施例中,操作216可在外延部件122U的暴露部分上方进一步形成硅化物或锗硅化物。例如,可以通过以下方法来形成硅化物:在外延部件122U的暴露部分上方沉积金属层(例如,镍),退火金属层,从而使得金属层与外延部件122U中的硅反应以形成金属硅化物,并且然后去除未反应的金属层。
然后,操作216在沟槽127(在不同的实施例中具有或没有硅化物)的底部和侧壁上沉积阻挡层126a,以防止导体126b的金属材料扩散到相邻的部件中。在一个实例中,阻挡层包括诸如TaN或TiN的介电材料。随后,操作216沉积导体(例如,金属)126b以填充沟槽127中的剩余空间。在该实施例中,导电部件126包括阻挡层126a和导体126b。阻挡层和金属层的沉积可以使用共形或非共形沉积工艺。导电部件126和下面的外延部件122U之间的大的界面由外延部件122U的大体积产生,这有利地降低了S/D接触电阻。可以类似地实施如图1E所示的形成的结构。
尽管不意在限制,但本发明的一个或多个实施例提供了半导体器件及其形成的许多益处。例如,凸起的S/D部件可以生长为具有浅的弧形底面和大致平坦的顶面。这有利地增加了凸起的S/D部件的体积以承受后续制造步骤中的某个过蚀刻。实质性效果是导电部件(例如,S/D接触件或S/D互连线)与凸起的S/D部件之间的界面面积增加并且接触电阻减小。本发明的各个实施例可以容易地集成到现有的制造工艺中。
在一个示例性方面,本发明涉及一种半导体器件。该半导体器件包括衬底,位于衬底上方的两个半导体鳍和位于两个半导体鳍上方的半导体部件。半导体部件包括两个下部和一个上部。两个下部分别直接位于两个半导体鳍上方。上部位于两个下部上方。上部的底面具有弧形的截面形状。
在一些实施例中,该半导体器件还包括:介电层,位于所述衬底上方,其中,所述介电层至少部分地围绕所述半导体部件的所述两个下部。
在一些实施例中,所述半导体部件包括具有n型掺杂剂的硅。
在一些实施例中,该半导体器件还包括:隔离结构,位于所述衬底上方,其中,所述两个半导体鳍的部分突出于所述隔离结构之上。
在一些实施例中,所述弧形的截面形状包括远离所述衬底向上延伸的弧。
在一些实施例中,所述弧具有小于0.5的高度与跨度比。
在一些实施例中,所述弧具有小于0.25的高度与跨度比。
在一些实施例中,所述弧形的截面形状包括朝着所述衬底向下延伸的弧。
在一些实施例中,所述弧具有小于0.5的高度与跨度比。
在一些实施例中,该半导体器件还包括:导体,部分地嵌入在所述半导体部件的所述上部中。
在一些实施例中,所述两个半导体鳍具有介于两个源极/漏极区之间的沟道区,并且所述半导体部件位于所述两个源极/漏极区中的一个上方,还包括:栅极堆叠件,包裹所述两个半导体鳍的所述沟道区。在另一示例性方面中,本发明针对一种半导体器件。该半导体器件包括衬底,位于衬底上方的两个半导体鳍和位于两个半导体鳍上方的半导体部件。半导体部件包括两个下部和一个上部。两个下部分别位于两个半导体鳍上方。上部位于两个下部上方并且物理地连接两个下部。上部的底面在垂直于鳍长度方向的平面中具有弧形形状。半导体器件还包括位于衬底上方的介电层,其中介电层至少部分地围绕半导体部件的两个下部。
在一些实施例中,所述弧形形状包括远离所述衬底向上延伸的弧。
在一些实施例中,所述弧具有小于0.25的高度与跨度比。
在一些实施例中,所述弧形形状包括朝着所述衬底向下延伸的弧。
在一些实施例中,所述弧具有小于0.25的高度与跨度比。
在另一示例性方面中,本发明针对一种形成半导体器件的方法。该方法包括提供包括衬底和从衬底延伸的两个鳍的器件;蚀刻该两个鳍,从而形成两个沟槽;在两个沟槽中外延生长第一半导体部件;以及在第一生长条件下在该第一半导体部件上外延生长第二半导体部件,其中,第二半导体部件横向合并以形成合并部分。该方法还包括,在合并部分的尺寸达到目标尺寸之后,在第二生长条件下外延生长第二半导体部件,其中,在第二生长条件下第二半导体部件的晶向[100]和[111]之间的生长速率比大于在第一生长条件下的该比率。
在一些实施例中,所述第二生长条件包括在650℃至720℃的温度范围内生长所述第二半导体部件。
在一些实施例中,该方法还包括:在所述第二生长条件下外延生长所述第二半导体部件之后,实施蚀刻工艺以减小所述第二半导体部件的宽度。
在一些实施例中,所述第二半导体部件包括硅,所述第一生长条件使用具有二氯甲硅烷(SiH2Cl2)的前体,并且所述第二生长条件向所述前体添加硅烷。
在一些实施例中,所述蚀刻工艺使用包括锗烷(GeH4)和氯化氢(HCl)的蚀刻剂。
在一些实施例中,该方法还包括:在所述第二半导体部件上方形成层间介电层(ILD);蚀刻穿过所述层间介电层的接触孔以暴露所述第二半导体部件的部分;以及在所述第二半导体部件中的所述接触孔内的暴露部分上方形成导电部件。
在另一示例性方面中,本发明针对一种形成半导体器件的方法。该方法包括提供具有衬底和从衬底延伸的至少两个鳍的器件。该方法还包括蚀刻至少两个鳍,从而形成至少两个沟槽;以及在至少两个沟槽中外延生长第一半导体部件。该方法还包括在第一生长条件下在第一半导体部件上方外延生长第二半导体部件,其中第二半导体部件横向合并,从而形成合并部分。在合并部分的厚度达到目标尺寸之后,该方法还包括在不同于第一生长条件的第二生长条件下外延生长第二半导体部件,从而在合并部分的底面中形成弧形形状。该方法还包括实施蚀刻工艺以减小第二半导体部件的宽度。
在一些实施例中,所述第二半导体部件包括硅,所述第一生长条件使用具有二氯甲硅烷(SiH2Cl2)的前体,所述第二生长条件使用所述前体和硅烷(SiH4),以及所述蚀刻工艺使用包括锗烷(GeH4)和氯化氢(HCl)的蚀刻剂。
在一些实施例中,所述蚀刻剂中的GeH4与HCl的比率在0.5至1.2的范围内。
在一些实施例中,该方法还包括:形成部分地嵌入在所述第二半导体部件中的导电部件。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件,包括:
衬底;
两个半导体鳍,位于所述衬底上方;以及
半导体部件,位于所述两个半导体鳍上方,
其中:
所述半导体部件包括两个下部和一个上部;
所述两个下部分别直接位于所述两个半导体鳍上方;
所述上部位于所述两个下部上方;和
所述上部的底面具有弧形的截面形状。
2.根据权利要求1所述的半导体器件,还包括:
介电层,位于所述衬底上方,其中,所述介电层至少部分地围绕所述半导体部件的所述两个下部。
3.根据权利要求1所述的半导体器件,其中,所述半导体部件包括具有n型掺杂剂的硅。
4.根据权利要求1所述的半导体器件,还包括:
隔离结构,位于所述衬底上方,其中,所述两个半导体鳍的部分突出于所述隔离结构之上。
5.根据权利要求1所述的半导体器件,其中,所述弧形的截面形状包括远离所述衬底向上延伸的弧。
6.根据权利要求5所述的半导体器件,其中,所述弧具有小于0.5的高度与跨度比。
7.根据权利要求5所述的半导体器件,其中,所述弧具有小于0.25的高度与跨度比。
8.根据权利要求1所述的半导体器件,其中,所述弧形的截面形状包括朝向所述衬底向下延伸的弧。
9.根据权利要求8所述的半导体器件,其中,所述弧具有小于0.5的高度与跨度比。
10.根据权利要求1所述的半导体器件,还包括:
导体,部分地嵌入在所述半导体部件的所述上部中。
11.一种形成半导体器件的方法,包括:
提供了包括衬底和从所述衬底延伸的两个鳍的器件;
蚀刻所述两个鳍,从而形成两个沟槽;
在所述两个沟槽中外延生长第一半导体部件;
在第一生长条件下在所述第一半导体部件上方外延生长第二半导体部件,其中,所述第二半导体部件横向合并以形成合并部分;以及
在所述合并部分的尺寸达到目标尺寸之后,在第二生长条件下外延生长所述第二半导体部件,其中,在所述第二生长条件下所述第二半导体部件的晶体方向[100]和[111]之间的生长速率比大于在所述第一生长条件下的所述生长速率比。
12.根据权利要求11所述的方法,其中,所述第二生长条件包括在从650℃至720℃的温度范围内生长所述第二半导体部件。
13.根据权利要求11所述的方法,还包括:
在所述第二生长条件下在外延生长所述第二半导体部件之后,实施蚀刻工艺以减小所述第二半导体部件的宽度。
14.根据权利要求13所述的方法,其中,所述第二半导体部件包括硅,所述第一生长条件使用具有二氯甲硅烷(SiH2Cl2)的前体,并且所述第二生长条件向所述前体添加硅烷。
15.根据权利要求14所述的方法,其中,所述蚀刻工艺使用包括锗烷(GeH4)和氯化氢(HCl)的蚀刻剂。
16.根据权利要求11所述的方法,还包括:
在所述第二半导体部件上方形成层间介电层(ILD);
蚀刻穿过所述层间介电层的接触孔以暴露所述第二半导体部件的部分;以及
在所述第二半导体部件的在所述接触孔中的暴露部分上方形成导电部件。
17.一种形成半导体器件的方法,包括:
提供具有衬底和从所述衬底处延伸的至少两个鳍的器件;
蚀刻所述至少两个鳍,从而形成至少两个沟槽;
在所述至少两个沟槽中外延生长第一半导体部件;
在第一生长条件下在所述第一半导体部件上方外延生长第二半导体部件,其中,所述第二半导体部件横向合并,从而形成合并部分;
在所述合并部分的厚度达到目标尺寸之后,在不同于所述第一生长条件的第二生长条件下外延生长所述第二半导体部件,从而在所述合并部分的底面中形成弧形形状;以及
实施蚀刻工艺以减小所述第二半导体部件的宽度。
18.根据权利要求17所述的方法,其中,所述第二半导体部件包括硅,所述第一生长条件使用具有二氯甲硅烷(SiH2Cl2)的前体,所述第二生长条件使用所述前体和硅烷(SiH4),以及所述蚀刻工艺使用包括锗烷(GeH4)和氯化氢(HCl)的蚀刻剂。
19.根据权利要求18所述的方法,其中,所述蚀刻剂中的锗烷与氯化氢的比率在从0.5至1.2的范围内。
20.根据权利要求17所述的方法,还包括:
形成部分地嵌入在所述第二半导体部件中的导电部件。
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