CN107742644B - High-performance normally-off GaN field effect transistor and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to the technical field of semiconductor device preparation, in particular to a high-performance normally-off GaN field effect transistor and a preparation method thereof. The device comprises a substrate, an epitaxial layer grown on the substrate, a gate dielectric layer, a gate electrode, a drain electrode and a source electrode. The epitaxial layer comprises a stress buffer layer and a GaN channel layer which are epitaxially grown at one time, a mask is reserved only in a grid region through mask patterning and etching processes, and after mask residues and surface contamination of an access region are removed through in-situ etching, an AlGaN/GaN heterojunction structure is grown in a selected region to form a groove channel. The gate metal covers the recessed channel, source and drain regions are formed at both ends of the device and the source and drain regions are formed overlying the metal. The device structure and the preparation process are simple and reliable, the in-situ etching access region can reduce defect impurities introduced into the device access region in the mask preparation process, a high-quality access region interface is obtained, the quality of the secondary epitaxial AlGaN/GaN heterostructure is ensured, and therefore the conduction performance of the normally-off GaN field effect transistor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a high-performance normally-off GaN field effect transistor and a preparation method thereof. In particular to an improved method for preparing an access area secondary growth interface of a groove gate normally-off GaN field effect transistor by selective area epitaxy.
Background
As a representative of the third generation semiconductor material, gaN has the characteristics of large forbidden bandwidth, large critical breakdown electric field strength, large power density, high carrier saturation velocity, and the like. The GaN power switch device can greatly improve the upper limit working frequency while maintaining the low noise performance and high rated power of the metal semiconductor field effect transistor, and has the advantages of higher working voltage, higher power density, high temperature resistance and the like, so that the GaN-based device gradually replaces the original Si-based device and the GaAs-based device in some power devices and high-frequency circuits.
The preparation method of the groove in the conventional groove gate normally-off GaN power device is to epitaxially grow an AlGaN/GaN heterostructure once, and then reduce the concentration of the two-dimensional electron gas in the region under the gate under the condition of keeping the concentration of the two-dimensional electron gas in the access region unchanged, and generally comprises the following steps: plasma etching a groove structure, F plasma injection, adding a P-type cap layer and the like. However, these methods inevitably use plasma processing techniques. The plasma etching groove or injection treatment causes lattice damage to the region under the grid electrode, so that leakage current of the device can be increased, and the grid control capability is reduced; the P-type cap layer scheme can cause lattice damage to the access area, and the stability of the two-dimensional electron gas channel and the reliability of the device are affected. Compared with the method, the Selective Area Growth (SAG) method can avoid the damage of plasma treatment to the active layer of the device, improve the interface quality of the grid electrode area and improve the stability and reliability of the device. However, in the field effect transistor with the selective area epitaxial GaN trench gate structure, the AlGaN/GaN heterojunction structure of the device access area is formed through secondary epitaxy, and the quality of the secondary epitaxial AlGaN/GaN heterojunction structure directly determines the performance of the device. Before the AlGaN/GaN epitaxial layer is grown secondarily, the epitaxial wafer covered with the SiO 2 mask layer needs to be subjected to deep cleaning, which exposes the substrate with the GaN channel layer to air, and air oxidation and C, si impurity contamination exist on the surface of the substrate. Meanwhile, when the AlGaN/GaN epitaxial layer is secondarily grown by using a metal organic compound chemical vapor deposition method, high-temperature treatment is needed for the Si substrate to realize cleaning of the Si substrate, but only H 2 is used as carrier gas in the heating process, and the heating condition can damage the surface of the GaN material because GaN is easy to decompose in the H 2 environment, and the reaction equation is as follows:
GaN reacts with H 2 at high temperatures to produce Ga drops and ammonia. Ga droplets can cause irregularities in the secondary epitaxial growth interface and thus degrade the quality of the secondary epitaxial AlGaN/GaN heterojunction structure. More seriously, the preparation of the selective area epitaxial mask pattern requires the growth of a SiO 2 mask layer on the surface of the substrate with the GaN channel layer by utilizing a plasma enhanced chemical vapor deposition method, and then the SiO 2 mask covered by the access area is removed by a dry/wet etching method, wherein the process has the risk of Si residues. The quality of the secondary epitaxial heterostructure is deteriorated due to the introduction of excessive impurities, the two-dimensional electron gas concentration of the conductive channel of the access region is reduced, and the improvement of the conduction performance of the device is not facilitated. It is therefore necessary to find a method for optimizing the interface quality of the normally-off GaN field effect transistor access region to overcome the defect of introducing defective impurities into the device access region caused by the selective region growth method, thereby obtaining a high-performance normally-off GaN field effect transistor.
Disclosure of Invention
The invention provides a high-performance normally-off GaN field effect transistor and a preparation method thereof, which aims to overcome at least one defect in the prior art, reduce Si, C/O and other impurities introduced at an interface of an access area in the mask preparation process and remove mask residues and surface contamination of the access area before growing a secondary epitaxial layer by in-situ etching of a GaN channel layer of the access area, improve the quality of the secondary growth interface of the access area of a device, and keep the two-dimensional electron gas concentration of the channel of the access area basically unchanged, thereby preparing the high-performance normally-off GaN field effect transistor.
The technical scheme of the invention is as follows: the high-performance normally-off GaN field effect transistor comprises a substrate, a stress buffer layer and a GaN channel layer from bottom to top, wherein a secondary epitaxial layer grows after the GaN channel layer of an access area is etched in situ, a grid mask is removed to form a groove grid structure, a grid dielectric layer is deposited on the surface of the groove grid structure, the grid dielectric layer is removed at two ends of the device, a source electrode and a drain electrode are formed, and a grid is covered on the grid dielectric layer of the groove grid region.
Further, the substrate is any one of a sapphire substrate, a silicon carbide substrate, a silicon substrate and a gallium nitride self-supporting substrate.
The stress buffer layer is any one or combination of AlGaN, gaN, alN; the thickness of the stress buffer layer is 100 nm-10 mu m.
The GaN channel layer is an unintentionally doped GaN channel layer or a doped high-resistance GaN channel layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN channel layer under the groove area is 100 nm-20 mu m, and is reduced by 10-50 nm compared with the thickness of the GaN channel layer under the lower access area.
The secondary epitaxial layer is an AlGaN/GaN heterojunction, the thickness of the AlGaN layer is 10-50 nm, the concentration of aluminum components can be changed, and the thickness of the GaN layer is 10-500 nm.
The groove gate structure is formed by removing surface contamination and growing a secondary epitaxial layer by in-situ etching of the GaN channel layer of the access region, and is in a U-shaped or trapezoid structure. The method for in-situ etching the access region has the advantages that mask residues and impurity introduction exist in the GaN channel layer of the access region when the gate mask layer is formed, the GaN channel layer of the access region can be subjected to in-situ etching to remove the surface defect state of the access region, and meanwhile, the introduction of environmental impurities is reduced, so that a high-quality secondary epitaxial interface is obtained.
The gate dielectric layer is an Al 2O3 or Si 3N4 compound, and the thickness is 10-100 nm.
The source electrode and the drain electrode materials comprise but are not limited to Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy, and other various metals or alloys capable of realizing ohmic contact can be used as source electrode and drain electrode materials; the gate material includes, but is not limited to, ni/Au alloys, pt/Al alloys, pd/Au alloys, or TiN/Ti/Al/Ti/TiN alloys, and various other metals or alloys capable of achieving high threshold voltages may be used as the gate material.
A preparation method of a high-performance normally-off GaN field effect transistor comprises the following steps: the method comprises the following steps:
s1, growing a stress buffer layer on a substrate;
s2, growing a GaN channel layer on the stress buffer layer;
S3, depositing a layer of SiO 2 on the GaN channel layer to serve as a mask layer;
S4, reserving a mask layer on the grid electrode region by photoetching and combining a dry etching method or a wet etching method;
S5, in-situ etching the GaN channel layer of the access area, wherein the etching depth is 10-50 nm;
S6, growing a secondary epitaxial layer in a selected area to form a groove type gate structure;
s7, removing the mask layer on the grid electrode area;
S8, depositing to form a gate dielectric layer;
S9, performing dry etching to complete mesa isolation of the device, and etching source electrode and drain electrode ohmic contact areas;
s10, evaporating source electrode metal and drain electrode metal on the source electrode area and the drain electrode area, and forming ohmic contact through ohmic alloy annealing;
S11, evaporating gate metal in a gate region on the gate dielectric layer at the groove.
The stress buffer layer in the step S1 and the GaN channel layer in the step S2 and the secondary epitaxial layer in the step S6 are grown by a high-quality film forming method such as a metal organic chemical vapor deposition method, a molecular beam epitaxy method and the like; the mask layer growing method in the step S3 is a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method or a magnetron sputtering method; the in-situ etching method in the step S5 is dry etching, and the etching gas environment is any one or combination of N 2、NH3; the growth method of the gate dielectric layer in the step S8 is a low-pressure chemical vapor deposition method.
Compared with the prior art, the beneficial effects are that: the invention improves the quality of the secondary growth interface of the access area of the device, and keeps the two-dimensional electron gas concentration of the channel of the access area basically unchanged, thereby improving the conduction performance of the device. According to the method, a step is added to a conventional selective region growing method, before a secondary epitaxial layer AlGaN/GaN heterojunction structure is grown, in-situ etching is carried out on a GaN channel layer which is not covered by a SiO 2 mask layer, siO 2 mask residues on an access region and interfaces containing more C, si donor impurities are removed, and meanwhile, environmental impurities introduced in a preparation stage before the secondary epitaxial layer is grown are reduced, so that the quality of the secondary epitaxial heterojunction structure is improved, the two-dimensional electron gas concentration of the channel of the access region is kept unchanged basically, and the conduction performance of a device is improved. The device has simple structure and high process repeatability and reliability, and improves the quality of the interface of the device access area while maintaining the high quality of the interface under the grid electrode area of the device, thereby providing a technology for preparing the high-performance normally-off GaN field effect transistor device.
Drawings
FIGS. 1-11 are process schematic diagrams of the device fabrication method of example 1 of the present invention.
Fig. 12-14 are schematic views of a process for preparing a mask layer on a gate region according to embodiment 2 of the present invention.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.
Example 1
Fig. 11 is a schematic diagram of a device structure in this embodiment, where the structure sequentially includes, from bottom to top, a substrate 1, a stress buffer layer 2, a GaN channel layer 3, growing a secondary epitaxial layer 4 after in-situ etching the GaN channel layer 3 in the access region, removing a gate mask to form a trench gate structure, depositing a gate dielectric layer 5 on the surface, removing the gate dielectric layers at two ends of the device to form a source electrode 6 and a drain electrode 7, and covering a gate electrode 8 on the gate dielectric layer in the trench gate region.
The preparation method of the high-performance normally-off GaN field effect transistor is shown in fig. 1-10, and comprises the following steps:
S1, growing a stress buffer layer 2 on a Si substrate 1 by using a metal organic chemical vapor deposition method, as shown in FIG. 1;
S2, growing a GaN channel layer 3 on the stress buffer layer 2 by using a metal organic chemical vapor deposition method, as shown in FIG. 2;
S3, depositing a layer of SiO 2 by using a plasma enhanced chemical vapor method to serve as a mask layer 9, as shown in FIG. 3;
s4, a photoetching combined reaction coupled plasma etching method is utilized, and a mask layer 9 on the grid electrode area is reserved, as shown in FIG. 4;
s5, performing in-situ etching on the access region in an N 2 gas environment by using a dry etching method, as shown in FIG. 5;
S6, growing a secondary epitaxial AlGaN/GaN layer 4 on a selected area of the substrate with the mask layer 9 by using a metal organic chemical vapor deposition method to form a groove structure, as shown in FIG. 6;
S7, removing the mask layer 9 on the gate region by adopting a wet etching method, as shown in FIG. 7;
s8, growing a gate dielectric layer 5 by using a low-pressure chemical vapor deposition method, as shown in FIG. 8;
S9, performing reactive coupling plasma etching to complete mesa isolation of the device, and etching source electrode and drain electrode ohmic contact areas at the same time, as shown in FIG. 9;
S10, ti/Al/Ni/Au alloy is evaporated on the source electrode and drain electrode regions to serve as ohmic contact metal of the source electrode 6 and the drain electrode 7, and ohmic contact is formed through ohmic alloy annealing, as shown in FIG. 10;
S11, ni/Au alloy is evaporated on the gate dielectric layer of the groove gate region to be used as the metal of the gate 9, as shown in FIG. 11.
Thus, the whole device preparation process is completed. Fig. 11 is a schematic diagram of the device structure of embodiment 1.
Example 2
Fig. 12-14 are schematic views of the process of preparing the SiO 2 mask layer on the gate region according to example 2 of the present invention, which differ from the preparation method of the SiO 2 mask layer on the gate region in example 1 only in that: in example 1, a reactive coupled plasma etch was used to form a mask pattern over the gate region, while in example 2, a lift-off process was used to form a mask pattern over the gate region. The specific process comprises the following steps:
S1, forming a photoresist protection layer 10 with a patterned structure on the upper part of a secondary epitaxial layer 3, as shown in FIG. 12;
S2, depositing a layer of SiO 2 on the substrate with the photoresist protective layer 10 by using a plasma enhanced chemical vapor method as a mask layer 9, as shown in FIG. 13;
And S3, removing the photoresist protective layer 10 by using photoresist stripping liquid, removing the mask layer 9 on the protective layer, and reserving the mask layer on the gate region so that the mask layer is patterned, as shown in FIG. 14.
The SiO 2 mask on the grid region is prepared by adopting a stripping process, so that the problem that a growth interface is easy to damage when a mask layer is manufactured by adopting the traditional photoetching and corrosion process can be well solved. However, before the secondary epitaxial layer 4 is grown, the GaN channel layer 3 is exposed in air, and the surface of the GaN channel layer is stained with air oxidation and C, si impurities, so that the defect problem of the device access area interface can not be completely solved by adopting a stripping process, and the preparation method provided by the patent can be used for obtaining a higher-quality access area secondary epitaxial growth interface.
Further, it is noted that the drawings of the above embodiments are for illustrative purposes only and are not necessarily drawn to scale.
It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.
Claims (8)
1. The high-performance normally-off GaN field effect transistor is characterized by comprising a substrate (1), a stress buffer layer (2) and a GaN channel layer (3) from bottom to top, wherein a secondary epitaxial layer (4) is grown after the GaN channel layer of an access area is etched in situ, a grid mask is removed to form a groove grid structure, a layer of grid dielectric layer (5) is deposited on the surface of the groove grid structure, the grid dielectric layer (5) is removed at two ends of the device, a source electrode (6) and a drain electrode (7) are formed, and a grid electrode (8) is covered on the grid dielectric layer (5) of the groove grid region; the groove gate structure is formed by removing surface contamination and growing a secondary epitaxial layer (4) through in-situ etching of a GaN channel layer (3) of the access area, and is in a U-shaped or trapezoid structure; the GaN channel layer (3) of the access area has mask residues and impurities introduced when the grid mask layer is formed, the GaN channel layer (3) of the access area is etched in situ, so that the defect state on the surface of the access area can be removed, and simultaneously, the introduction of environmental impurities is reduced, and a high-quality secondary epitaxial interface is obtained.
2. A high performance normally-off GaN field effect transistor according to claim 1 wherein: the substrate (1) is any one of a sapphire substrate, a silicon carbide substrate, a silicon substrate and a gallium nitride self-supporting substrate.
3. A high performance normally-off GaN field effect transistor according to claim 1 wherein: the stress buffer layer (2) is any one or combination of AlGaN, gaN, alN; the thickness of the stress buffer layer is 100 nm-10 mu m.
4. A high performance normally-off GaN field effect transistor according to claim 1 wherein: the GaN channel layer (3) is an unintentionally doped GaN channel layer or a doped high-resistance GaN channel layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN channel layer under the groove area is 100 nm-20 mu m, and is reduced by 10-50 nm compared with the thickness of the GaN channel layer under the lower access area.
5. A high performance normally-off GaN field effect transistor according to claim 1 wherein: the secondary epitaxial layer (4) is an AlGaN/GaN heterojunction, the thickness of the AlGaN layer is 10-50 nm, the concentration of aluminum components can be changed, and the thickness of the GaN layer is 10-500 nm.
6. A high performance normally-off GaN field effect transistor according to claim 1 wherein: the gate dielectric layer (5) is an Al2O3 or Si3N4 compound, and the thickness is 10-100 nm; the source electrode (6) and the drain electrode (7) are made of Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the grid electrode (8) is made of Ni/Au alloy, pt/Al alloy, pd/Au alloy or TiN/Ti/Al/Ti/TiN alloy.
7. The method for manufacturing a high-performance normally-off GaN field effect transistor according to claim 1, wherein: the method comprises the following steps:
s1, growing a stress buffer layer (2) on a substrate (1);
S2, growing a GaN channel layer (3) on the stress buffer layer (2);
S3, depositing a layer of SiO2 on the GaN channel layer (3) to serve as a mask layer (9);
S4, reserving a mask layer (9) above the grid region by photoetching and combining a dry etching method or a wet etching method;
s5, in-situ etching the GaN channel layer (3) of the access area, wherein the etching depth is 10-50 nm;
S6, growing a secondary epitaxial layer (4) in a selected area to form a groove type gate structure;
S7, removing the mask layer (9) above the grid region;
S8, depositing to form a gate dielectric layer (5);
S9, performing dry etching to complete mesa isolation of the device, and etching source electrode and drain electrode ohmic contact areas;
S10, metal of a source electrode (6) and a drain electrode (7) is evaporated on the source electrode and drain electrode regions, and ohmic contact is formed through ohmic alloy annealing;
S11, evaporating metal of a grid electrode (8) in a grid electrode area on the grid dielectric layer at the groove.
8. The method for manufacturing a high-performance normally-off GaN field effect transistor according to claim 7, wherein: the stress buffer layer (2) in the step S1, the GaN channel layer (3) in the step S2 and the secondary epitaxial layer (4) in the step S6 are grown by a high-quality film forming method such as a metal organic chemical vapor deposition method, a molecular beam epitaxy method and the like; the growth method of the mask layer (9) in the step S3 is a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method or a magnetron sputtering method; the in-situ etching method in the step S5 is dry etching, and the etching gas environment is any one or combination of N2 and NH 3; the growth method of the gate dielectric layer in the step S8 is a low-pressure chemical vapor deposition method.
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| CN114220738B (en) * | 2021-12-22 | 2024-04-30 | 江苏第三代半导体研究院有限公司 | GaN-based semiconductor device and preparation method thereof |
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