CN107741523A - A kind of time-domain signal measurement apparatus based on PLL phaselocked loops - Google Patents
A kind of time-domain signal measurement apparatus based on PLL phaselocked loops Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention relates to a kind of time-domain signal measurement apparatus based on PLL phaselocked loops, including normalization module, VCXO modules, frequency measuring instrument, single-chip microcomputer, compensating module and PLL loop units；Time-domain signal measurement apparatus based on PLL phaselocked loop of the present invention in, reduce the method for PLL frequency displacements using signal feedback control loop, and improved ultimate VCXO output frequency signals device is provided, it will to dock with the measuring system of user terminal with more stable, more accurate output signal.
Description
Technical field
The present invention relates to signal measurement field, and in particular to a kind of time-domain signal measurement apparatus based on PLL phaselocked loops.
Background technology
Phaselocked loop (phase locked loop), is exactly the loop of locking phase as its name suggests.Learned and automatically control original
The people of reason both knows about, and this is a kind of typical feedback control circuit, using being shaken inside the reference signal control loop of outside input
The frequency and phase of signal are swung, realizes that output signal frequency, from motion tracking, is generally used for Closed loop track to frequency input signal
Circuit.It is to make a kind of relatively stable method of frequency in radio transmitting, mainly there is VCXO（Voltage controlled oscillator）With PLL IC
（Phase-locked loop intergrated circuit）, voltage controlled oscillator provides a signal, a part of to be used as output, and another part passes through frequency dividing and PLL
Local oscillation signal caused by IC makees phase bit comparison, in order to which keep frequency is constant, it is desirable to which phase difference does not change, if phase
The change of potential difference, then the voltage of PLL IC voltage output end change, go control VCXO, until phase difference recover, reach
Lock the purpose of phase.The frequency of controlled oscillator and phase can be made to keep the close loop electronic circuit of determination relation with input signal.
In the PLL circuit environment of reality, we can also ignore the parameter of other key, that is, in whole PLL circuit
The amplitude of signal influences and the accuracy of final extreme pressure controlled oscillator VCXO output frequencies.Domestic related reported literature at present
In detailed research is not deployed with regard to this technology, cause the phenomenon of most of PLL phase-locked loop operations stability differences.
The frequency stability evaluation of temporal frequency signal is an importance of time-frequency research work.For a signal
For source, its output signal is generally expressed with following formula：
（1）
Wherein, a (t) represents that signal source output signal rises and falls with the random magnitude of time,Represent signal source output signal
Phase（It that is to say frequency）With the random fluctuation of time,The frequency of expression signal source output signal is small unidirectional with the time
Change, referred to as frequency drift, now relatively good VCXO is typically severalMagnitude.
Chronological aging inside signal source is come from, the output frequency of introducing unidirectionally changes.
Come from contribution of each component noise of composition signal source to overall frequency stability, it is generally accepted that composition letter
It is ergodic that complete machine output frequency, which rises and falls, caused by each component noise in number source, therefore it can be used in random statistical theory
Variance characterize.
The standard variance that early stage people are risen and fallen with relative frequency deviation characterizes the frequency stability of signal source.If it is signal to make f0
The average frequency in source, then in sample timeInterior, the relative frequency deviation of output frequency is：
（2）
Research shows, for the output signal of various types of signal source, the relative frequency deviation relief volume of its output frequencyIt is big
Small, speed 5 kinds of noises listed in by power-law noise model are influenceed, and power-law noise model is：
（3）
In formula=-2, -1,0,1,2；,For constant, depending on size is with specific signal source；For system
Higher cutoff frequency.
Actual use shows that the frequency of tested frequency source has scope limitation when entering measuring instrument, and this is one of defect；Its
The frequency of secondary external reference clock in itself is unstable also to bring error to systematic survey.
Above mentioned problem, have to be solved.
The content of the invention
The technical problem to be solved in the present invention is：It is proposed a kind of being locked based on PLL with more stable, more accurate output signal
The time-domain signal measurement apparatus of phase ring.
The present invention is to solve the technical scheme that above-mentioned technical problem proposes to be：A kind of time-domain signal based on PLL phaselocked loops
Measurement apparatus, including normalization module, VCXO modules, frequency measuring instrument, single-chip microcomputer, compensating module and PLL loop units；
The VCXO modules are suitable to the high steady external reference source clock signal of output, the external reference source clock signal respectively by
Deliver to the normalization module and frequency measuring instrument；
The normalization module is suitable in the presence of the external reference source clock, and place is normalized to tested frequency signal
Reason, obtains standard 1MHz calibratings frequency signal and is output to the frequency measuring instrument；
The frequency measuring instrument be suitable in the presence of external reference source clock, to normalization module output signal frequency according to
Sampling time T=10 second progress temporal frequency measurement, and give measurement result to outer computer；
The compensating module is suitable to compensate control to the output error frequency of the VCXO modules；
The single-chip microcomputer is suitable to carry out state modulator to normalization module, frequency measuring instrument and the compensating module；
The PLL unit is suitable to the accuracy by accurately VCXO modules output frequency described in signal frequency closed-loop control.
Further, the PLL loop units include PLL loop modules, prime amplification module, signal feedback module and end
Level amplification module, the frequency signal that the PLL loop modules obtain are obtained by prime amplification not synchronizing phase demodulation before processing
Obtain radiofrequency signal and be fed through the processing of signal feedback module；
Single-chip microcomputer obtains the relevant parameter information of radiofrequency signal, the relevant parameter information by the access to signal feedback module
Including signal maximum amplitude, minimum amplitude, peak-to-peak value, the prime amplification of final stage amplification module is will be fed under the control of single-chip microcomputer
Signal carries out parameter reparation, and completes the synchronous phase discrimination function of traditional PLL phaselocked loops；
Voltage-controlled voltage signal is obtained after synchronized phase demodulation effect to remake for VCXO modules, completes PLL phase-locked loops.
Further, the normalization module includes the first isolated amplifier, the first DDS module and the 2nd DDS crossover rates
Unit, the reference frequency signal f0 of the external reference source clock are sent to the first DDS module after the first isolated amplifier
External clock input, as the work external reference clock of the first DDS module, the external communication end of first DDS module
Mouth is connected to single-chip microcomputer, to receive control word command and the two-way data transfer from single-chip microcomputer；
The 2nd DDS frequency units include the second isolated amplifier, the second DDS module, walk hour counter, latch, the 3rd
DDS module and filtration module；Second isolated amplifier is connected respectively to second DDS module and the 3rd DDS module, institute
State the second DDS module, first walk hour counter and the first latch sequentially forms signal connection, the 3rd DDS module connection
To the filtration module；The external communication port of second DDS module and the 3rd DDS module is respectively connecting to single-chip microcomputer, uses
To receive control word command and the two-way data transfer from single-chip microcomputer.
Further, the frequency measuring instrument include the 3rd isolated amplifier, second walk hour counter, the second latch,
4th isolated amplifier, the 3rd walk hour counter and the 3rd latch；3rd isolated amplifier, second walk hour counter and
Second latch sequentially forms signal connection；4th isolated amplifier, the 3rd walk hour counter and the 3rd latch successively
Form signal connection；3rd isolated amplifier and the 4th isolated amplifier are also respectively connected to the single-chip microcomputer, and described
Two walk hour counter and the 3rd controlled end for walking hour counter is connected respectively to the control terminal of the single-chip microcomputer, the single-chip microcomputer
Read end and be also respectively connected to second latch and the 3rd latch.
Further, the compensating module include first voltage base modules, second voltage base modules, D/A modules and
Temperature control modules；
The voltage output that the first voltage base modules are adapted to provide for stablizing all the way delivers to VCXO modules；
The Voltage Reference that the second voltage base modules are adapted to provide for stablizing all the way delivers to the external voltage reference of D/A modules
End；
The temperature control modules are described on the outer wall of the VCXO modules and including Temperature Controlling Chip and the second thermistor
Temperature control modules are adapted to detect for the operating temperature of the VCXO modules and send result to the single-chip microcomputer；
The D/A modules are suitable to the variable DC voltage value of output size under the control of the single-chip microcomputer, and deliver to VCXO moulds
Block.
The beneficial effects of the invention are as follows：
Time-domain signal measurement apparatus based on PLL phaselocked loop of the present invention in, reduce PLL frequencies using signal feedback control loop
The method of shifting, and improved ultimate VCXO output frequency signals device is provided, it will be come with more stable, more accurate output signal
Docked with the measuring system of user terminal.
Brief description of the drawings
The time-domain signal measurement apparatus based on PLL phaselocked loops of the present invention is described further below in conjunction with the accompanying drawings.
Fig. 1 is the structured flowchart of the time-domain signal measurement apparatus based on PLL phaselocked loops in the present invention；
Fig. 2 is the structured flowchart and fundamental diagram of PLL loop units；
Fig. 3 is the structured flowchart for normalizing module；
Fig. 4 is the structured flowchart of the 2nd DDS frequency units；
Fig. 5 is the structure and working principle block diagram of compensating module；
Fig. 6 is the circuit diagram of temperature control modules；
Fig. 7 is the schematic diagram of compensating module；
Fig. 8 is the frequency measurement schematic diagram of signal；
Fig. 9 is the structural principle block diagram of frequency measuring instrument；
Figure 10 is the circuit arrangement figure of signal feedback module.
Embodiment
Embodiment
According to Fig. 1, the time-domain signal measurement apparatus based on PLL phaselocked loops in the present invention, including normalization module,
VCXO modules, frequency measuring instrument, single-chip microcomputer, compensating module and PLL loop units.
VCXO modules are suitable to the high steady external reference source clock signal of output, and external reference source clock signal is sent to respectively
Normalize module and frequency measuring instrument；
Normalize module to be suitable in the presence of external reference source clock, tested frequency signal is normalized, obtained
Standard 1MHz calibratings frequency signal is simultaneously output to frequency measuring instrument.
As shown in figure 3, it can be used as preferably：Normalize module include the first isolated amplifier, the first DDS module and
2nd DDS crossover rate units.
Reference frequency signal f0 is sent to the external clock input of the first DDS module after the first isolated amplifier, makees
Worked external reference clock for the first DDS module, while the external communication port of the first DDS module is connected to single-chip microcomputer, to
Receive control word command and two-way data transfer from single-chip microcomputer.The DDS chip internals actually selected have 2 48 bit frequencies
Control register（F0、F1）, it is 10MHz for present apparatus reference frequency signal f0, when without using PLL double frequency functions inside DDS
When, during the frequency control register F0 full packings 1 of 48, DDS has the output of 10MHz frequency signals, therefore to obtain standard
Sampling time periods signal T（Such as 1 second, 10 seconds）, it is necessary to corresponding frequency dividing numerical value is set to frequency control register F0 in DDS,
The method specifically calculated is：
（4）
Wherein, D is the required specific frequency dividing numerical value calculated, and f0 is reference signal frequency, and f0 is 10MHz in the present apparatus, and f is institute
The sample time signal frequency divided is needed, is 1Hz for f（1 second）And 0.1Hz（10 seconds）Situation, frequency dividing numerical value D should be
248 × 10-7 or 248 × 10-8.Specific sampling time T is user according to the needs during actual samples and by PC ends
Software design patterns, and when dividing numerical value to be single-chip microcomputer obtaining the sampling that user is set by RS232 serial line interfaces and PC end communications
Between after T, formula（4）It is calculated.Single-chip microcomputer will divide numerical value D according to the corresponding serial communication sequential of the first DDS module
After writing the first DDS module respective cache device, final the first DDS module end sample time signal T outputs are obtained.
When measured signal frequency is up to a hundred million or even hundreds of megahertzs, it is contemplated that walk hour counter to being tested frequency range
Limitation, as shown in figure 4, the 2nd DDS frequency units include the second isolated amplifier, the second DDS module, walk hour counter, lock
Storage, the 3rd DDS module and filtration module；Second isolated amplifier is connected respectively to the second DDS module and the 3rd DDS module,
Second DDS module, first walk hour counter and the first latch sequentially forms signal connection, and the 3rd DDS module is connected to filtering
Module；The external communication port of second DDS module and the 3rd DDS module is respectively connecting to single-chip microcomputer, to receive to come from monolithic
The control word command of machine and two-way data transfer.
The second DDS module is designed in this patent, and 1/100 scaling down processing is carried out to tested frequency signal.Measured signal is through
The external clock input of the second DDS module is sent directly into after two isolated amplifiers, reference when being worked as the second DDS module
Clock.The external communication port of second DDS module is connected to single-chip microcomputer, and single-chip microcomputer is according to formula（4）Obtained 248 × 10-2 frequency dividings
Numerical value writes the second DDS module buffer area, the 1/100 crossover rate signal obtained through the second DDS module by serial communication sequential
Afterwards, deliver to first and walk hour counter progress coarse frequency measurement, single-chip microcomputer reads the first latch and hour counter sampling is walked to first
Numerical value after, record frequency values now, be multiplied by the coarse frequency value F that measured signal can be obtained after 100.
Another way is sent to the external clock input of the 3rd DDS module by the measured signal of the second isolated amplifier,
Reference clock when being worked as the 3rd DDS module.The external communication port of the 3rd DDS module is connected to single-chip microcomputer simultaneously, single
Piece machine is according to formula（4）The frequency dividing numerical value with the 3rd DDS module communication is calculated：, wherein F is to be walked by first
The coarse frequency value for the measured signal that hour counter counts, single-chip microcomputer computing obtains, f take 1MHz, and will by serial communication sequential
The specific frequency dividing numerical value of gained writes the 3rd DDS module buffer area, and 1MHz frequency signal is obtained after the 3rd DDS module, will
The frequency signal of gained obtains final 1MHz frequency signals output after delivering to low-pass filtering module again.
Compensating module is suitable to compensate control to the output error frequency of VCXO modules.
As shown in figure 5, it can be used as preferably：Compensating module includes first voltage base modules, second voltage benchmark
Module, D/A modules and temperature control modules.The voltage output that first voltage base modules are adapted to provide for stablizing all the way delivers to VCXO
Module.The Voltage Reference that second voltage base modules are adapted to provide for stablizing all the way delivers to the external voltage reference end of D/A modules.Temperature
Control module is spent on the outer wall of VCXO modules and is suitable to inspection including Temperature Controlling Chip and the second thermistor, temperature control modules
Survey the operating temperature of VCXO modules and send result to single-chip microcomputer.D/A modules are suitable to the output size under the control of single-chip microcomputer
Variable DC voltage value, and deliver to VCXO modules.
As shown in fig. 6, two of which R and R1 are the resistance with identical temperature coefficient, its resistance should select and Rk
Quite.Here R1 value reflects actual VCXO operating ambient temperatures T.Rk is a thermistor, and it is affixed on VCXO surface,
To perceive the actual operating ambient temperature T of VCXO.Therefore when VCXO operating ambient temperature T is unchanged, in upper figure at electric bridge
In balance, the temperature-compensated voltage value for being delivered to voltage-controlled conversion module is 0.Once VCXO operating ambient temperature T changes,
Then thermistor Rk resistance will diminish（Temperature raises）Or become big（Temperature reduces）, then there is voltage difference in electric bridge both ends, warp
It is changed into temperature-compensated voltage after operational amplifier A differential amplification and is delivered to voltage source, while exports and give traditional heating silk thread ring
Road.The gain amplifier of whole circuit is adjusted by the negative feedback resistor Rw of operational amplifier, and Rw is a digital potentiometer, passes through regulation
Rw resistance changes function to reach foregoing circuit compensating factor.
In compensating module device, We conducted Component screening：
Voltage reference 1, voltage reference 2 have identical temperature coefficient, i.e. temperature often changes 10C, caused relevant voltage benchmark
It is consistent with reference to value changes, be, for example,：-1E-3（V/0C）.
According to VCXO temperature profile curve, VCXO specific works temperature spot is set by single-chip microcomputer, makes VCXO herein
Operating point or so has the temperature characterisitic opposite with above-mentioned 1 voltage reference（Above-mentioned is negative temperature coefficient, then correspondingly selects VCXO
For positive temperature coefficient）, such as selection occurrence for：+ 1E-10/0C, i.e. temperature often change 10C, will cause VCXO output signals
Frequency change+1E-10.
With reference to above-mentioned 1, corresponding VCXO voltage-controlled slope value is selected, 1E-7/V is such as selected, because voltage reference acts on
VCXO makes it export different frequency, then after 1, we can obtain voltage reference change caused by relevant temperature change and be turned into
It is for caused output signal frequency rate of change after VCXO：
-1E-3（V/0C）×1E-7（V）=-1E-10/0C
The less VCXO of aging drift rate is selected, such as：In -1E-6/ years, obtained by conversion in 365 days 1 year:- 2.7E-9/ days.
As shown in fig. 7, wherein curved portion（VCXO is exported）What is expressed is the frequency sampling curve of traditional VCXO outputs.By
Figure curved portion can be seen that in whole sampling process, the fluctuation point that VCXO outputs can be larger：The frequency fluctuation upper limit, frequency
Fluctuate lower limit.This requires frequency absolute value harsh occasion, such as guided missile precise guidance, GPS precision navigations etc. for some
It is extremely disadvantageous.It is as follows that this patent specifically compensates embodiment：
1st, on traditional VCXO Process ba- sis, VCXO, voltage reference 1, voltage reference 2 is made to be operated in the work of scheme requirement first
Make on temperature spot, such as T=200C, then VCXO is by with positive temperature coefficient+1E-10/0C, voltage reference 1 and voltage reference
2 will be with negative temperature coefficient -1E-3/0C, corresponding caused VCXO output signal frequency rates of change：-1E-10/0C.
In VCXO course of normal operation, due to the limitation of temperature control effect, internal operational module VCXO, voltage reference 1, voltage reference 2
Will because of temperature fluctuation it is impacted, but according to the implementation of above-mentioned 1 scheme, VCXO positive frequencys changing value caused by temperature will
With temperature caused by voltage reference act on VCXO negative frequencies changing value neutralize be 0.Here caused by the change for solving temperature
The problem of VCXO output frequencies change.
2nd, single-chip microcomputer internal record VCXO voltage-controlled slope data, and set up the relation of " voltage-frequency ", that is, think
Desired value f1, the f2 scope in figure is realized, processor records corresponding magnitude of voltage V1, V2.Here VCXO output frequencies are realized
Rate is controlled in a small range, that is, is realized in the desired value square frame shown in figure.
3rd, with reference to the VCXO aging drift data of selection：The voltage-controlled slope value in -2.7E-9/ days and VCXO：1E-7/V,
Single-chip microcomputer carries out corresponding main modulation according to day to correction voltage V, i.e., voltage V is rectified a deviation per angel on above-mentioned 2 technical foundation,
Plus a fixed correction value, such as：27mV, then VCXO output frequencies are caused to increase 1E-7/V × 27mV=+ -2.7E- accordingly
9, branch VCXO can be so compensated because frequency change influences caused by aging drift.Here scheme will make above-mentioned 2 to obtain more
Good implementation result.
Frequency measuring instrument be suitable in the presence of external reference source clock, to normalization module output signal frequency according to
Sampling time T=10 second progress temporal frequency measurement, and give measurement result to outer computer.
As shown in Figure 8 and Figure 9, can be used as preferably：When frequency measuring instrument is walked including the 3rd isolated amplifier, second
Counter, the second latch, the 4th isolated amplifier, the 3rd walk hour counter and the 3rd latch.3rd isolated amplifier,
Two walk hour counter and the second latch sequentially forms signal connection；4th isolated amplifier, the 3rd walk hour counter and the 3rd
Latch sequentially forms signal connection；3rd isolated amplifier and the 4th isolated amplifier are also respectively connected to single-chip microcomputer, and second
Walk hour counter and the 3rd controlled end for walking hour counter is connected respectively to the control terminal of single-chip microcomputer, the reading end of single-chip microcomputer is also divided
The second latch and the 3rd latch are not connected to.
The 1MHz frequency signals that tested frequency signal obtains after the processing of DDS frequency units are believed with 10MHz reference clocks
Number frequency measuring instrument is delivered to respectively.As shown in Figure 4 and Figure 5, single-chip microcomputer foundation reference clock signal is after the processing of the first DDS module
Obtained sample time signal T rising edge enables two-way frequency signal and measured, specifically：On a sampled signal T
Rise along rear, when the rising edge of measured signal and external reference clock signal arrives, single-chip microcomputer counts when enabled second walks respectively
Device and the 3rd walks hour counter progress frequency counting.After a sampled signal T trailing edge, when measured signal and external reference
When the rising edge of clock signal arrives, single-chip microcomputer enables second respectively to be walked hour counter and the 3rd and walks hour counter and terminate frequency meter
Number, while obtain in a complete sample signal T time in upper figure, measured signal and the overall pulse of external reference clock signal
Number N1 and N2.And enabled second latch and the 3rd latch walk hour counter and the 3rd to second respectively and walk the meter of hour counter
Numerical value is latched.If the frequency of measured signal is Fx, the frequency of base is fo during reference（It is 10MHz in practice）, in gate
Between in T, the counting of base is respectively N1, N2 when counter is to measured signal and reference, then has：
（5）
By formula（5）Understand, the frequency fx of measured signal is relevant with the count value N1, N2 with reference to timebase frequency fo and two counters.
In a complete sampling period T, what the second latch and the 3rd latch preserved second walks hour counter and the 3rd when walking
Reading value N1, N2 of counter pass to single-chip microcomputer, in formula（5）In it is considered that reference clock source frequency fo is constant,
That is 10MHz, so we can be readily available the frequency values fx of measured signal.
PLL unit is suitable to the accuracy by accurately signal frequency closed-loop control VCXO module output frequencies.Wherein, may be used
Using as preferably：As shown in Fig. 2 PLL loop units include PLL loop modules, prime amplification module, signal feedback module
With final stage amplification module, PLL loop modules obtain frequency signal do not synchronize phase demodulation before processing by prime amplification obtain
Obtain radiofrequency signal and be fed through the processing of signal feedback module.
The frequency signal of VCXO modules output is sent into calibration module, and signal frequency is modified under the control of single-chip microcomputer
Export again afterwards to user terminal.
On signal feedback module, as shown in Figure 10, prime amplified signal transports to amplifier A1 and A3 respectively, and prime is put
Big signal delivers to A2 after A3.A4 and A5 is voltage follower, on its output end V11 and V12 voltage magnitudes and electric capacity C1 and C2
Voltage it is identical（The effect for adding one-level to follow is to provide electric current with this follower to support）.V11 and V12 delivers to A6's respectively
End of oppisite phase and in-phase end, complete N（V12-V11）Computing.
Wherein A1 and A4 completes the detection of prime amplified signal peak-peak：
When prime amplified signal voltage is more than electric capacity C1 voltages, pressure drop is produced on resistance Rf, electric current is from left to right.According to amplifier
Void break rule D11 do not turn on.At this moment charging current is carried out by D12 to C1.When the voltage of prime amplified signal is less than electricity
When holding C1 voltages, pressure drop is produced on resistance R2, electric current is from right to left.Do not turned on according to the disconnected rule D12 of the void of amplifier, it is at this moment electric
Stream only enters A1 by D11.Because voltage follower A4 output voltages are identical with the voltage on electric capacity C1, diode D11 is cut
Only, electric capacity can not lead D11 electric discharges, and voltage is protected, i.e. electric capacity C1 and A4 outputs V11 have recorded prime amplified signal most
Big peak value.Electric capacity C1 have discharge resistance a R1, RC discharge time constant τ according to the cycle of the prime amplified signal of reality come
Setting, such as the frequency of prime amplified signal is 79Hz, then τ takes 1S.V11 is delivered to A/D samplings 1 and corresponded to simultaneously
Magnitude of voltage be transferred to single-chip microcomputer.
It is anti-phase that A3 completes prime amplified signal：
Prime amplified signal progress of the amplifier A3 first to its input is anti-phase, then is superimposed a negative amplitude DC level Vref, finally
The conversion of the high and low level of prime amplified signal is completed, obtains signal output to amplifier A2.
A2 and A5 completes the detection of prime amplified signal minimum peak：
Prime amplified signal delivers to amplifier A2 in-phase end after A3 is handled.The wherein for example above-mentioned A1 and A3 of A2 and A5 principles,
Only this moment has already passed through amplifier A3 processing due to prime amplified signal, and what A2 and A5 were completed is prime amplified signal minimum
The detection of value.Simultaneously V12 be delivered to A/D sampling 2 obtain corresponding to magnitude of voltage be transferred to single-chip microcomputer.
A6 completes the detection of peak-to-peak value：
Prime amplified signal high level V11 and low level V12 after aforementioned processing is respectively fed to difference amplifier A6, passes through tune
Save Ry and Rx ratio, output（V12-V11）*(Ry/Rx).Magnitude of voltage corresponding to being delivered to the acquisition of A/D samplings 3 simultaneously is transferred to
Single-chip microcomputer.
1,2,3 magnitudes of voltage obtained are sampled by above-mentioned A/D and may determine that the frequency of prime amplified signal module output is believed
Number amplitude Characteristics, these signals, into final stage amplified signal module, complete synchronous phase demodulation by singlechip feedbsck.Herein
There is a critically important technology：Substantially in accordance with main schematic diagram, we are only by above-mentioned acquisition（V12-V11）* (Ry/Rx) information
Carry out processing and be changed into amendment to be delivered to VCXO, Wo Menji with voltage-controlled voltage VX and conventional synchronization phase demodulation voltage-controlled voltage VY summations
（V12-V11）=VPP、(Ry/Rx)=K.Here K be a gain amplifier it typically rely on amplifier A6 in signal feedback module
Feedback oscillator Ry and Rx ratio, KVPPThe voltage-controlled voltage swing of amendment for adding to VCXO is directly determined, so the necessary roots of VX
It is configured according to specific VCXO voltage-controlled slope and conventional synchronization phase demodulation with voltage-controlled voltage VY magnitudes, we typically take VX=VY/20
To VX=VY/10 magnitudes
The patent working benefit that above scheme obtains：
The voltage-controlled voltage that we are applied to VCXO according to above-mentioned principle is：
VY+VX=VY+（V12-V11）* (Ry/Rx)=VY+KVPP（6）
Here VY is that the synchronous phase demodulation that traditional PLL phaselocked loops obtain is voltage-controlled；K is signal feedback circuit feedback oscillator（During design
Through being fixed）；VPPIt is the peak-to-peak value of prime amplified signal.
In same time domain frequency signal output system, as the frequency of output signal becomes big, the peak-to-peak value of signal will diminish,
As shown above.So when signal frequency caused by traditional PLL phase-locked loop circuits becomes small, the prime signal peak-to-peak value of acquisition
Big, to be obtained by the embodiment of this patent voltage-controlled voltage VY+KV will be becomePPIt will become big（It is V in practicePPBecome big）, act on
After VCXO the signal frequency that VCXO is exported will be made to become big（Because that select in practice is the VCXO of just voltage-controlled slope）, thus rise
The effect of compensation is arrived.
The present invention's is not limited to above-described embodiment, and the technical scheme of above-mentioned each embodiment of the invention can be handed over each other
Fork combination forms new technical scheme, in addition all technical schemes formed using equivalent substitution, all falls within the guarantor of application claims
In the range of shield.
Claims (5)
- A kind of 1. time-domain signal measurement apparatus based on PLL phaselocked loops, it is characterised in that：Including normalization module, VCXO modules, Frequency measuring instrument, single-chip microcomputer, compensating module and PLL loop units；The VCXO modules are suitable to the high steady external reference source clock signal of output, the external reference source clock signal respectively by Deliver to the normalization module and frequency measuring instrument；The normalization module is suitable in the presence of the external reference source clock, and place is normalized to tested frequency signal Reason, obtains standard 1MHz calibratings frequency signal and is output to the frequency measuring instrument；The frequency measuring instrument be suitable in the presence of external reference source clock, to normalization module output signal frequency according to Sampling time T=10 second progress temporal frequency measurement, and give measurement result to outer computer；The compensating module is suitable to compensate control to the output error frequency of the VCXO modules；The single-chip microcomputer is suitable to carry out state modulator to normalization module, frequency measuring instrument and the compensating module；The PLL unit is suitable to the accuracy by accurately VCXO modules output frequency described in signal frequency closed-loop control.
- 2. the time-domain signal measurement apparatus based on PLL phaselocked loops according to claim 1, it is characterised in that：The PLL loops Unit includes PLL loop modules, prime amplification module, signal feedback module and final stage amplification module, and the PLL loop modules obtain Frequency signal do not synchronize phase demodulation before processing by prime amplification obtain radiofrequency signal be fed through signal feedback module Processing；Single-chip microcomputer obtains the relevant parameter information of radiofrequency signal, the relevant parameter information by the access to signal feedback module Including signal maximum amplitude, minimum amplitude, peak-to-peak value, the prime amplification of final stage amplification module is will be fed under the control of single-chip microcomputer Signal carries out parameter reparation, and completes the synchronous phase discrimination function of traditional PLL phaselocked loops；Voltage-controlled voltage signal is obtained after synchronized phase demodulation effect to remake for VCXO modules, completes PLL phase-locked loops.
- 3. the time-domain signal measurement apparatus based on PLL phaselocked loops according to claim 2, it is characterised in that：The normalization module includes the first isolated amplifier, the first DDS module and the 2nd DDS crossover rate units, the outside The reference frequency signal f0 of reference source clock is sent to the external clock input of the first DDS module after the first isolated amplifier End, as the work external reference clock of the first DDS module, the external communication port of first DDS module is connected to monolithic Machine, to receive control word command and the two-way data transfer from single-chip microcomputer；The 2nd DDS frequency units include the second isolated amplifier, the second DDS module, walk hour counter, latch, the 3rd DDS module and filtration module；Second isolated amplifier is connected respectively to second DDS module and the 3rd DDS module, institute State the second DDS module, first walk hour counter and the first latch sequentially forms signal connection, the 3rd DDS module connection To the filtration module；The external communication port of second DDS module and the 3rd DDS module is respectively connecting to single-chip microcomputer, uses To receive control word command and the two-way data transfer from single-chip microcomputer.
- 4. the time-domain signal measurement apparatus based on PLL phaselocked loops according to claim 3, it is characterised in that：The frequency is surveyed Amount instrument includes the 3rd isolated amplifier, second walks hour counter, the second latch, the 4th isolated amplifier, the 3rd and count when walking Device and the 3rd latch；3rd isolated amplifier, second walk hour counter and the second latch sequentially forms signal connection； 4th isolated amplifier, the 3rd walk hour counter and the 3rd latch sequentially forms signal connection；3rd isolation is put Big device and the 4th isolated amplifier are also respectively connected to the single-chip microcomputer, and described second, which walks hour counter and the 3rd, walks hour counter Controlled end be connected respectively to the control terminal of the single-chip microcomputer, the reading end of the single-chip microcomputer is also respectively connected to second lock Storage and the 3rd latch.
- 5. the time-domain signal measurement apparatus based on PLL phaselocked loops according to claim 4, it is characterised in that：The compensation mould Block includes first voltage base modules, second voltage base modules, D/A modules and temperature control modules；The voltage output that the first voltage base modules are adapted to provide for stablizing all the way delivers to VCXO modules；The Voltage Reference that the second voltage base modules are adapted to provide for stablizing all the way delivers to the external voltage reference of D/A modules End；The temperature control modules are described on the outer wall of the VCXO modules and including Temperature Controlling Chip and the second thermistor Temperature control modules are adapted to detect for the operating temperature of the VCXO modules and send result to the single-chip microcomputer；The D/A modules are suitable to the variable DC voltage value of output size under the control of the single-chip microcomputer, and deliver to VCXO moulds Block.
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| CN113049878A (en) * | 2021-03-04 | 2021-06-29 | 中国科学院微小卫星创新研究院 | Satellite frequency measurement system and method |
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