CN207382288U - A kind of phase-locked loop circuit - Google Patents
A kind of phase-locked loop circuit Download PDFInfo
- Publication number
- CN207382288U CN207382288U CN201721195288.8U CN201721195288U CN207382288U CN 207382288 U CN207382288 U CN 207382288U CN 201721195288 U CN201721195288 U CN 201721195288U CN 207382288 U CN207382288 U CN 207382288U
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- voltage
- frequency
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model is related to a kind of phase-locked loop circuit, including PLL loop modules, prime amplification module, signal feedback module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator module；The utility model reduces the method for PLL frequency displacements and provides improved ultimate voltage-controlled local oscillator output frequency signal device by using signal feedback control loop, will with it is more stable, more accurately output signal to user terminal.
Description
Technical field
The utility model is related to frequency signal device fields, and in particular to a kind of phase-locked loop circuit.
Background technology
Phaselocked loop (phase locked loop), is exactly the loop of locking phase as its name suggests.It learned and automatically controls original
The people of reason both knows about, this is a kind of typical feedback control circuit, using shaking inside externally input reference signal control loop
The frequency and phase of signal are swung, realizes that output signal frequency, from motion tracking, is generally used for Closed loop track to frequency input signal
Circuit.It is a kind of method for making frequency relatively stable in radio transmitting, mainly there is voltage-controlled local oscillator（Voltage controlled oscillator）And PLL
IC （Phase-locked loop intergrated circuit）, voltage controlled oscillator provides a signal, a part as output, another part by frequency dividing with
Local oscillation signal caused by PLL IC makees phase bit comparison, in order to which keep frequency is constant, it is desirable to and phase difference does not change, if
Dephased variation, then the voltage of the voltage output end of PLL IC change, go to control voltage-controlled local oscillator, until phase difference is extensive
It is multiple, achieve the purpose that lock phase.The frequency of controlled oscillator and phase can be made to keep determining the closed loop electricity of relation with input signal
Sub-circuit.
In actual PLL circuit environment, we can also ignore the parameter of other key, that is, in entire PLL circuit
The amplitude of signal influences and the accuracy of the voltage-controlled local oscillator output frequency of final pole voltage controlled oscillator.Domestic relevant document at present
The phenomenon that in report there is no detailed research is unfolded with regard to this technology, causes most of PLL phase-locked loop operations stability poor.
Utility model content
The technical problems to be solved in the utility model is：It is proposed a kind of improved phase-locked loop circuit.
The technical solution that the utility model proposes to solve above-mentioned technical problem is：A kind of phase-locked loop circuit, including PLL rings
Road module, prime amplification module, signal feedback module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator mould
Block；
The obtained frequency signal of the PLL loop modules is sent to the prime amplification module, the prime amplification module
Signal output part be connected respectively to the signal input part of the signal feedback module and the signal input part of final stage amplification module,
The parameter output of the signal feedback module is connected to the parameter input end of the central processing unit, the central processing unit
Control terminal is connected to the controlled end of the final stage amplification module；
The voltage-controlled voltage signal of the final stage amplification module is exported to the voltage-controlled local oscillator module, the letter of the voltage-controlled local oscillator
Number output terminal is connected respectively to the signal input part of the PLL loop modules and the signal input part of calibration module, the center
The control terminal of processor is also connected to the controlled end of the calibration module.
Further, the calibration module includes isolated amplifier, the first DDS module, the second DDS module, counts when walking
Device, wave filter and latch；
The signal output part of the isolated amplifier is connected respectively to first DDS module and the second DDS module, described
The signal output part of second DDS module be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch；
The signal output part of first DDS module is connected to filter module.
Further, second DDS module is suitable for carrying out 1/100 to the voltage-controlled local oscillation signal inputted through isolated amplifier
Scaling down processing.
Further, the 1/100 crossover rate signal obtained through 1/100 scaling down processing send thick to hour counter progress is walked
Frequency measurement after central processing unit reads numerical value of the latch to walking hour counter sampling, is recorded frequency values at this time, is multiplied
The coarse frequency value F of voltage-controlled local oscillator can be obtained after 100.
Further, the external communication port of first DDS module is connected to central processing unit, central processing unit according toThe frequency dividing numerical value with DDS1 communications is calculated, wherein f is the radio frequency letter of user terminal to be delivered to
Number frequency values, f0For voltage-controlled local oscillator output signal frequency, and the specific frequency dividing numerical value as serial communication sequential by obtained by writes
First DDS module buffer area, frequency signal is obtained after the first DDS module, and the frequency signal of gained is sent to wave filter again
Obtain final frequency signal output.
The beneficial effects of the utility model are：
The utility model reduces the method for PLL frequency displacements and provides improved ultimate by using signal feedback control loop
Voltage-controlled local oscillator output frequency signal device, will with it is more stable, more accurately output signal to user terminal.
Description of the drawings
The phase-locked loop circuit of the utility model is described further below in conjunction with the accompanying drawings.
Fig. 1 is the structure diagram of phase-locked loop circuit in the utility model；
Fig. 2 is the circuit diagram of signal feedback module；
Fig. 3 is time-domain radio-frequency signal frequency and magnitude relation figure；
Fig. 4 is the structure diagram of calibration module.
Specific embodiment
Embodiment
According to Fig. 1, the phase-locked loop circuit of the utility model, including PLL loop modules, prime amplification module, signal
Feedback module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator module（VCXO）.
The obtained frequency signal of PLL loop modules is sent to prime amplification module, the signal output part of prime amplification module
It is connected respectively to the signal input part of signal feedback module and the signal input part of final stage amplification module, the ginseng of signal feedback module
Number output terminals are connected to the parameter input end of central processing unit, the control terminal of central processing unit be connected to final stage amplification module by
Control end.
The voltage-controlled voltage signal of final stage amplification module is exported to voltage-controlled local oscillator module, and the signal output part of voltage-controlled local oscillator is distinguished
The signal input part of PLL loop modules and the signal input part of calibration module are connected to, the control terminal of central processing unit also connects
To the controlled end of calibration module.
Prime amplification, signal feedback, final stage amplifying element are introduced in said program.The frequency that traditional PLL loops obtain
Rate signal do not synchronize phase demodulation before processing by prime amplification obtain radiofrequency signal be fed through signal feedback module processing；In
Central processor mainly includes signal most significantly by the relevant parameter information of the access acquisition radiofrequency signal to signal feedback module
Value, minimum amplitude, peak-to-peak value.The prime amplified signal that will be fed into final stage amplification module under the control of central processing unit is joined
Number is repaired, and completes the synchronous phase discrimination function of traditional PLL phaselocked loops.Voltage-controlled voltage signal is obtained after synchronized phase demodulation effect to remake
For voltage-controlled local oscillator, tradition PLL phase-locked loops are completed.The frequency signal of voltage-controlled local oscillator output is sent into calibration module, in centre
It manages and is exported again to user terminal after being modified under the control of device to signal frequency.
On signal feedback module
As shown in Fig. 2, prime amplified signal transports to amplifier A1 and A3 respectively, and prime amplified signal sent after A3 to
A2.A4 and A5 is voltage follower, and output terminal V11 and V12 voltage magnitude are identical with the voltage on capacitance C1 and C2（Add level-one
The effect followed is to provide electric current with this follower to support）.V11 and V12 is sent respectively to the end of oppisite phase of A6 and in-phase end, complete
Into N（V12-V11）Computing.
Wherein A1 and A4 completes the detection of prime amplified signal peak-peak：When prime amplified signal voltage is more than capacitance C1
During voltage, pressure drop is generated on resistance Rf, electric current is from left to right.It is not turned on according to the void of the amplifier rule D11 that breaks.At this moment charge electricity
Stream carries out C1 by D12.When the voltage of prime amplified signal is less than capacitance C1 voltages, pressure drop, electric current are generated on resistance R2
From right to left.It is not turned on according to the void of the amplifier rule D12 that breaks, at this moment electric current only enters A1 by D11.Due to voltage follow
Device A4 output voltages are identical with the voltage on capacitance C1, and diode D11 cut-offs, capacitance cannot lead D11 electric discharges, and voltage is protected
Shield, i.e. capacitance C1 and A4 outputs V11 have recorded the peak-peak of prime amplified signal.There are one discharge resistance R1, RC by capacitance C1
Discharge time constant τ set according to the cycle of actual prime amplified signal, such as the frequency of prime amplified signal is
79Hz, then τ take 1S.V11 is delivered to the corresponding voltage value of 1 acquisition of A/D samplings and is transferred to central processing unit simultaneously.
A3 completes prime amplified signal reverse phase：Amplifier A3 first carries out reverse phase to the prime amplified signal of its input, then is superimposed
One negative amplitude DC level Vref, is finally completed the conversion of the high and low level of prime amplified signal, obtains signal output to amplifier
A2。
A2 and A5 completes the detection of prime amplified signal minimum peak：Prime amplified signal after A3 is handled, and send to
The in-phase end of amplifier A2.The wherein for example above-mentioned A1 and A3 of A2 and A5 principles, only this moment passed through due to prime amplified signal
Amplifier A3 processing is crossed, what A2 and A5 were completed is the detection of prime amplified signal minimum value.V12 is delivered to A/D samplings 2 and obtains simultaneously
Corresponding voltage value is transferred to central processing unit.
A6 completes the detection of peak-to-peak value：Distinguish through foregoing treated prime amplified signal high level V11 and low level V12
Difference amplifier A6 is sent into, by adjusting the ratio of Ry and Rx, is exported（V12-V11）*(Ry/Rx).A/D samplings are delivered to simultaneously
3, which obtain corresponding voltage value, is transferred to central processing unit.
1,2,3 voltage values obtained are sampled by above-mentioned A/D and may determine that the frequency of prime amplified signal module output is believed
Number amplitude Characteristics, these signals are fed back to by central processing unit in final stage amplified signal module, complete synchronous phase demodulation.
Here there are one critically important technologies：Substantially in accordance with main schematic diagram, we are only by above-mentioned acquisition（V12-V11）*(Ry/Rx)
Information handle becoming correcting is delivered to voltage-controlled local oscillator with voltage-controlled voltage VX and the voltage-controlled voltage VY summations of conventional synchronization phase demodulation, I
Remember（V12-V11）=VPP、(Ry/Rx)=K.Here K be a gain amplifier it typically rely on and transported in signal feedback module
Put the ratio of the feedback oscillator Ry and Rx of A6, KVPPIt directly determines and adds to the voltage-controlled voltage swing of the amendment of voltage-controlled local oscillator, so
VX must be configured according to the voltage-controlled slope and conventional synchronization phase demodulation of specific voltage-controlled local oscillator with voltage-controlled voltage VY magnitudes, Wo Menyi
As take VX=VY/20 to VX=VY/10 magnitudes
The patent working benefit that above scheme obtains：
The voltage-controlled voltage that we are applied to voltage-controlled local oscillator according to above-mentioned principle is：
VY+VX=VY+（V12-V11）* (Ry/Rx)=VY+KVPP（1）
Here VY is that the synchronous phase demodulation that traditional PLL phaselocked loops obtain is voltage-controlled；K is signal feedback circuit feedback oscillator（Design
When be fixed）；VPPIt is the peak-to-peak value of prime amplified signal.
According to time-domain radio-frequency signal frequency and magnitude relation, Fig. 3：In same time domain frequency signal output system, with defeated
The frequency for going out signal becomes larger, and the peak-to-peak value of signal will become smaller, as shown above.So generated when traditional PLL phase-locked loop circuits
Signal frequency becomes hour, and the prime signal peak-to-peak value of acquisition will become larger, the voltage-controlled voltage obtained by the embodiment of this patent
VY+KVPPIt will become larger（It is V in practicePPBecome larger）, the signal frequency for making voltage-controlled local oscillator output is become larger after acting on voltage-controlled local oscillator
（Because what is selected in practice is the voltage-controlled local oscillator of just voltage-controlled slope）, thus play the role of compensation.
On calibration module
As shown in figure 4, voltage-controlled local oscillation signal is sent respectively through isolated amplifier to DDS1 and DDS2：
When voltage-controlled local frequency is up to a hundred million or even hundreds of megahertzs, it is contemplated that walk hour counter to voltage-controlled local oscillator scope
Limitation, designed in the utility model wherein all the way DDS2 modules to voltage-controlled local oscillation signal carry out 1/100 scaling down processing.It is voltage-controlled
Local oscillator is sent directly into the external clock input terminal of DDS2, reference clock when working as DDS2 after isolated amplifier.
The DDS chip internals actually selected have 2 48 bit frequency control registers（F0、F1）, for the present apparatus without using
Inside DDS during PLL double frequency functions, during the frequency control register F0 full packings 1 of 48, DDS, which has voltage-controlled local oscillator and expire frequency, to be believed
Number output, therefore exported for the frequency signal for obtaining standard to user terminal, it is necessary to set phase to frequency control register F0 in DDS
The frequency dividing numerical value answered, the method specifically calculated are：
（2）
Wherein, D is that the specific of required calculating divides numerical value, f0For voltage-controlled local oscillator output signal frequency.The outside of DDS leads to
News port is connected to central processing unit, and central processing unit is according to formula（2）2 obtained48×10-2Frequency dividing numerical value passes through serial communication
Sequential write DDS2 buffer areas, after the 1/100 crossover rate signal that DDS2 is obtained, send to walk hour counter 1 carry out coarse frequency survey
Amount after central processing unit reads numerical value of the latch 1 to walking the sampling of hour counter 1, is recorded frequency values at this time, is multiplied by
The coarse frequency value F of voltage-controlled local oscillator can be obtained after 100.
Another way is sent to the external clock input terminal of DDS1 by the voltage-controlled local oscillator of isolated amplifier, works as DDS1
When reference clock.The external communication port of DDS1 is connected to central processing unit simultaneously, and central processing unit is according to formula（2）It calculates
To the frequency dividing numerical value with DDS1 communications：, wherein F is counts by walking hour counter 1, central processing unit computing obtains
The coarse frequency value of the voltage-controlled local oscillator arrived, f are the radio frequency signal frequency value of user terminal to be delivered to.And pass through serial communication sequential and incite somebody to action
The specific frequency dividing numerical value write-in DDS1 buffer areas of gained, obtain frequency signal after DDS1, by the frequency signal of gained send again to
Final frequency signal output is obtained after low-pass filtering module.
The utility model is not limited to above-described embodiment, the technical solution of above-mentioned each embodiment of the utility model that
This can form new technical solution with combined crosswise, and in addition all technical solutions formed using equivalent substitution, all fall within this practicality
In the protection domain of new requirement.
Claims (5)
1. a kind of phase-locked loop circuit, it is characterised in that：Including PLL loop modules, prime amplification module, signal feedback module, in
Central processor, final stage amplification module, calibration module and voltage-controlled local oscillator module；
The obtained frequency signal of the PLL loop modules is sent to the prime amplification module, the letter of the prime amplification module
Number output terminal is connected respectively to the signal input part of the signal feedback module and the signal input part of final stage amplification module, described
The parameter output of signal feedback module is connected to the parameter input end of the central processing unit, the control of the central processing unit
End is connected to the controlled end of the final stage amplification module；
The voltage-controlled voltage signal of the final stage amplification module is exported to the voltage-controlled local oscillator module, and the signal of the voltage-controlled local oscillator is defeated
Outlet is connected respectively to the signal input part of the PLL loop modules and the signal input part of calibration module, the central processing
The control terminal of device is also connected to the controlled end of the calibration module.
2. phase-locked loop circuit according to claim 1, it is characterised in that：The calibration module includes isolated amplifier, first
DDS module, the second DDS module walk hour counter, wave filter and latch；
The signal output part of the isolated amplifier is connected respectively to first DDS module and the second DDS module, and described second
The signal output part of DDS module be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch；
The signal output part of first DDS module is connected to filter module.
3. phase-locked loop circuit according to claim 2, it is characterised in that：Second DDS module is suitable for amplifying through isolation
The voltage-controlled local oscillation signal of device input carries out 1/100 scaling down processing.
4. phase-locked loop circuit according to claim 3, it is characterised in that：1/100 point obtained through 1/100 scaling down processing
Frequency signal is sent to hour counter progress coarse frequency measurement is walked, and central processing unit reads the number that latch is sampled to walking hour counter
After value, frequency values at this time are recorded, are multiplied by the coarse frequency value F that voltage-controlled local oscillator can be obtained after 100.
5. phase-locked loop circuit according to claim 4, it is characterised in that：The external communication port of first DDS module connects
Be connected to central processing unit, central processing unit according toThe frequency dividing numerical value with DDS1 communications is calculated,
Wherein f is the radio frequency signal frequency value of user terminal to be delivered to, f0For voltage-controlled local oscillator output signal frequency, and pass through serial communication
The specific frequency dividing numerical value of gained is write the first DDS module buffer area by sequential, and frequency signal is obtained after the first DDS module, will
The frequency signal of gained obtains final frequency signal output after being sent again to wave filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721195288.8U CN207382288U (en) | 2017-09-18 | 2017-09-18 | A kind of phase-locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721195288.8U CN207382288U (en) | 2017-09-18 | 2017-09-18 | A kind of phase-locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207382288U true CN207382288U (en) | 2018-05-18 |
Family
ID=62340178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721195288.8U Expired - Fee Related CN207382288U (en) | 2017-09-18 | 2017-09-18 | A kind of phase-locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207382288U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395199A (en) * | 2017-09-18 | 2017-11-24 | 江汉大学 | A kind of phase-locked loop circuit |
-
2017
- 2017-09-18 CN CN201721195288.8U patent/CN207382288U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395199A (en) * | 2017-09-18 | 2017-11-24 | 江汉大学 | A kind of phase-locked loop circuit |
| CN107395199B (en) * | 2017-09-18 | 2023-11-24 | 江汉大学 | Phase-locked loop circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1794587B (en) | Clock generator for generating accurate and low-jitter clock | |
| CN103684436B (en) | Phase locked loop circuit and method of generating clock signals using the phase locked loop | |
| CN105940610B (en) | The charge pump correction of two-phase phase-locked loop | |
| US20090296869A1 (en) | Communication systems, clock generation circuits thereof, and method for generating clock signal | |
| US20030141936A1 (en) | All-digital frequency synthesis with non-linear differential term for handling frequency perturbations | |
| US20030107442A1 (en) | All-digital frequency synthesis with capacitive re-introduction of dithered tuning information | |
| US20030133522A1 (en) | All-digital frequency synthesis with DCO gain calculation | |
| TW200915727A (en) | Adjustable digital lock detector | |
| CN109861691A (en) | The analog-digital converter circuit of two-step mixed structure SAR TDC based on delay phase-locked loop | |
| CN104485951A (en) | Frequency synthesis source circuit of phase-looked loop (PLL) and control method | |
| TW201324077A (en) | Clock generator and a method of generating a clock signal | |
| CN207382288U (en) | A kind of phase-locked loop circuit | |
| Yoshimura et al. | Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop | |
| CN105306048B (en) | It is a kind of to be used to suppress spuious phase-locked loop circuit and its spurious reduction method | |
| Anand et al. | A 2.75 Gb/s CMOS clock recovery circuit with broad capture range | |
| CN107395199A (en) | A kind of phase-locked loop circuit | |
| Nisa'Minhad et al. | Investigating phase detectors: Advances in mature and emerging phase-frequency and time-to-digital detectors in phase-locked looped systems | |
| CN207801904U (en) | A kind of PLL phase-locked loop systems | |
| CN105337591B (en) | The circuit structure and method of clock recovery are realized based on USB device | |
| CN111224621B (en) | Automatic amplitude control oscillating circuit and crystal-free high-precision clock generator | |
| Rennie et al. | A 5-Gb/s CDR circuit with automatically calibrated linear phase detector | |
| Dutta et al. | Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review | |
| CN203340051U (en) | Phase-locked loop system | |
| CN102104378B (en) | Locking detection method and device for all-digital phase-locked loop | |
| CN103633998B (en) | Low-power phase discriminator used for full digital phase-locked loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180518 Termination date: 20180918 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |