CN107731680B - A kind of channel hole etching technics using hard exposure mask - Google Patents
A kind of channel hole etching technics using hard exposure mask Download PDFInfo
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- CN107731680B CN107731680B CN201711139421.2A CN201711139421A CN107731680B CN 107731680 B CN107731680 B CN 107731680B CN 201711139421 A CN201711139421 A CN 201711139421A CN 107731680 B CN107731680 B CN 107731680B
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- 238000005530 etching Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 84
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 24
- 239000004411 aluminium Substances 0.000 claims abstract description 24
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 239000000460 chlorine Substances 0.000 claims abstract description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000006117 anti-reflective coating Substances 0.000 claims description 24
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 13
- 230000015654 memory Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JKGITWJSGDFJKO-UHFFFAOYSA-N ethoxy(trihydroxy)silane Chemical compound CCO[Si](O)(O)O JKGITWJSGDFJKO-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
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Abstract
The present invention provides a kind of channel hole etching technics using novel hard exposure mask, the technique includes: that metallic aluminium is used above as hard mask layer in buffer oxide (Buffer OX) layer on stacked structure；The thickness of the metallic aluminium hard mask layer is aboutChlorine (Cl is used before etching2) the etching opening metallic aluminium hard mask layer；Then oxidation processes in short-term are carried out using oxygen to metallic aluminium hard mask layer and forms aluminum oxide (Al2O3) protective layer；Then the etching in channel hole is carried out to form channel hole；Finally use boron chloride (BCl3) removal aluminum oxide (Al2O3) protective layer.The hard exposure mask of metallic aluminium will not be etched damage, and thickness can be greatly reduced, to can solve channel bore deformation and the problem of part channel hole is closed and lacks, improve the arc-shaped bend pattern in channel hole, and expand bottom critical dimension (CD).
Description
Technical field
The present invention relates to improve channel hole etching in field of semiconductor manufacture more particularly to a kind of 3D NAND flash memory structure
The method of technique.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and most ask being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND
(3D and non-) flash memory.Currently, in the development process of 3D NAND, with the increase of stacking number, to preparations such as etching, depositions
More stringent requirements are proposed for technique.
Wherein, for etch channel hole (Channel Hole), the prior art before etching, as shown in Figure 1, usual shape
At following stacked structure:
O/N stack layer 1-1 is arranged in face on substrate, wherein deposits about above the sacrificial dielectric layer silicon nitride of top layer
Ethyl orthosilicate (TEOS) 1-2, deposit about above ethyl orthosilicate (TEOS) 1-2
The barrier layer SiN 1-3,
It is formed about on the 1-3 of barrier layer
Buffer oxide nitride layer (Buffer OX) 1-4, in buffer oxide (Buffer
OX about 2.0 μm Kodiak (Kodiak) amorphous carbon layer 1-5, Kodiak (Kodiak) agraphitic carbon) are formed above 1-4
The upper surface of layer 1-5 is formed about
Bottom anti reflective coatings (Barc) or
Dielectric anti-reflective coating (Darc) 1-
6, then be about above
Photoresist layer 1-7.
Among these, about 2.0 μm of Kodiak (Kodiak) amorphous carbon layer 1-5 is intended for hard exposure mask to define ditch
The pattern in road hole simultaneously protects O/N stack layer.Kodiak (Kodiak) amorphous carbon layer is up to the present to can be used most
Hard hard mask layer.However, in deep-hole etching process, the hardness of Kodiak (Kodiak) amorphous carbon layer or inadequate,
And the thickness of Kodiak (Kodiak) amorphous carbon layer is big, will lead to the scattering of plasma ion, and this will be to channel
Sky damages.In addition, being had following defects that as hard exposure mask such as Fig. 2 using Kodiak (Kodiak) amorphous carbon layer
At the top of channel hole shown in the microcosmic schematic diagram of pattern, channel bore deformation and part channel hole are closed and lack；And such as Fig. 3
Shown in the microcosmic schematic diagram of channel hole longitudinal cross-section pattern, channel hole has the bending pattern of arc, and bottom critical dimension
(CD) smaller.
It is above-mentioned to will affect 3D as the defect in channel hole caused by hard exposure mask as Kodiak (Kodiak) amorphous carbon layer
Therefore how the performance of nand flash memory entirety selects hard mask material, to overcome Kodiak (Kodiak) amorphous carbon layer
Drawbacks described above, so that the direction of research is endeavoured always in the channel hole of the higher yield of preparation by those skilled in the art.
Summary of the invention
The purpose of the present invention is to provide a kind of channel hole etching technics using hard exposure mask, by choosing new hard exposure mask
Material overcomes the drawbacks described above of Kodiak (Kodiak) amorphous carbon layer, so as to improve the technique of channel hole etching；And then it mentions
High channel hole process rate.
To achieve the goals above, The technical solution adopted by the invention is as follows:
A kind of channel hole etching technics using hard exposure mask, comprising the following steps:
Substrate is provided；
Face forms O/N stack layer over the substrate；
Ethyl orthosilicate (TEOS) layer is formed on the O/N stack layer；
The barrier layer SiN is deposited on the ethyl orthosilicate (TEOS) layer；
Buffer oxide nitride layer (Buffer OX) layer is formed on the barrier layer；
Metallic aluminium hard mask layer is formed on the buffer oxide (Buffer OX) layer；
Bottom anti reflective coatings (Barc) or dielectric anti-reflective coating are formed in the upper surface of described metallic aluminium hard mask layer
(Darc)；
In the bottom anti reflective coatings (Barc) or dielectric anti-reflective coating (Darc) applied atop photoresist (PR),
And it exposes and forms channel hole litho pattern；
It is etched according to channel hole litho pattern and opens bottom anti reflective coatings (Barc) or dielectric anti-reflective coating
(Darc)；
Continue etching downwards and opens metallic aluminium hard mask layer；
Oxidation processes in short-term are carried out to metallic aluminium hard mask layer and form aluminum oxide (Al2O3) protective layer；
The etching in channel hole is carried out to form channel hole；
Remove aluminum oxide (Al2O3) protective layer.
Further, the thickness of ethyl orthosilicate (TEOS) layer is about
Further, the thickness on the barrier layer SiN is about
Further, the thickness of the buffer oxide nitride layer (Buffer OX) is about
Further, the thickness of the metallic aluminium hard mask layer is about
Further, the bottom anti reflective coatings (Barc) with a thickness ofOr dielectric anti-reflective coating (Darc)
Thickness about
Further, it is described coating photoresist (PR) thickness about
Further, the etching opens metallic aluminium hard mask layer and uses chlorine (Cl2) processing.
It is further, described that the progress of metallic aluminium hard mask layer, oxidation processes are using oxygen (O in short-term2) aoxidized.
Further, the removal aluminum oxide (Al2O3) protective layer be using boron chloride (BCl3) perform etching place
Reason.
Compared with prior art, the beneficial effects are mainly reflected as follows:
First, aluminum oxide (Al2O3) protective layer will not etch by conventional etching gas, therefore, etch in channel hole
Period, the hard exposure mask will not be damaged, to can solve channel bore deformation and the problem of part channel hole is closed and lacks.
Second, the thickness of hard mask layer can reduce by 90% or more compared to Kodiak (Kodiak) amorphous carbon layer, therefore
The ion scattering of plasma will reduce, so as to improve the arc-shaped bend pattern in channel hole.
Third is easy to expand by increasing substrate bias power (bias power) due to that can ignore the damage of hard exposure mask
Bottom critical dimension (CD).
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 uses channel hole of Kodiak (Kodiak) amorphous carbon layer as hard exposure mask to show in the prior art
The schematic diagram of stacked structure before etching；
Fig. 2, for the display prior art using Kodiak (Kodiak) amorphous carbon layer as the ditch after hard mask etching
The microcosmic schematic diagram of pattern at the top of road hole；
Fig. 3, for the display prior art using Kodiak (Kodiak) amorphous carbon layer as the ditch after hard mask etching
The microcosmic schematic diagram of road hole longitudinal cross-section pattern；
Fig. 4, the schematic diagram of stacked structure before being etched using metallic aluminium as the channel hole of hard mask layer for the display present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present invention provides a kind of channel hole etching technics using hard exposure mask, with reference to Fig. 4, comprising the following steps:
S100 provides substrate；
S200, face forms O/N stack layer 100 over the substrate；
S300 forms ethyl orthosilicate (TEOS) layer 200, the ethyl orthosilicate on the O/N stack layer 100
(TEOS) thickness of layer 200 is about
S400 deposits the barrier layer SiN 300, the barrier layer SiN 300 on the ethyl orthosilicate (TEOS) layer 200
Thickness about
S500 forms buffer oxide nitride layer (Buffer OX) 400, the buffer oxide on the barrier layer 300
The thickness of layer (Buffer OX) layer 400 is about
S600 forms metallic aluminium hard mask layer 500, the gold on the buffer oxide (Buffer OX) layer 400
Belong to the thickness of aluminium hard mask layer 500 about
S700, the upper surface of described hard exposure mask 500 of metallic aluminium form bottom anti reflective coatings (Barc) 600 or dielectric counnter attack
Penetrate coating (Darc) 600 ', the bottom anti reflective coatings (Barc) 600 with a thickness of
Or dielectric anti-reflective coating
(Darc) 600 ' thickness is about
S800, the 600 ' applied atop photoetching of the anti-reflection coating (Barc) 600 or dielectric anti-reflective coating (Darc)
Glue (PR) 700, and expose and form channel hole litho pattern, the thickness of coating photoresist (PR) 700 is about
S900, road hole litho pattern etching open bottom anti reflective coatings (Barc) 600 or dielectric anti-reflective coating
(Darc)600′；
S1000, opens metallic aluminium hard mask layer 500, and the etching opens metallic aluminium hard mask layer 500 and uses chlorine
(Cl2) processing；
S1100 carries out oxidation processes in short-term to metallic aluminium hard mask layer 500 and forms aluminum oxide (Al2O3) protective layer,
The oxidation processes are using oxygen (O2) aoxidized；
S1200 carries out the etching in channel hole to form channel hole；
S1300 removes aluminum oxide (Al2O3) protective layer；Removal aluminum oxide (the Al2O3) protective layer be adopt
With boron chloride (BCl3) perform etching processing.
Claims (8)
1. a kind of channel hole etching technics using hard exposure mask, which comprises the following steps:
Substrate is provided；
Face forms O/N stack layer over the substrate；
Ethyl orthosilicate (TEOS) layer is formed on the O/N stack layer；
The barrier layer SiN is deposited on the ethyl orthosilicate (TEOS) layer；
Buffer oxide nitride layer (Buffer OX) layer is formed on the barrier layer；
Metallic aluminium hard mask layer is formed on the buffer oxide (Buffer OX) layer；
Bottom anti reflective coatings (Barc) or dielectric anti-reflective coating are formed in the upper surface of described metallic aluminium hard mask layer
(Darc)；
In the bottom anti reflective coatings (Barc) or dielectric anti-reflective coating (Darc) applied atop photoresist (PR), and expose
Light forms channel hole litho pattern；
It is etched according to channel hole litho pattern and opens bottom anti reflective coatings (Barc) or dielectric anti-reflective coating
(Darc)；
Using chlorine (Cl2) it is that reaction gas continues etching opening metallic aluminium hard mask layer downwards；
Oxidation processes in short-term are carried out to metallic aluminium hard mask layer and form aluminum oxide (Al2O3) protective layer；
The etching in channel hole is carried out to form channel hole；
Using boron chloride (BCl3) perform etching, remove aluminum oxide (Al2O3) protective layer.
2. etching technics as described in claim 1, which is characterized in that the thickness of ethyl orthosilicate (TEOS) layer is about
3. etching technics as described in claim 1, which is characterized in that the thickness on the barrier layer SiN is about
4. etching technics as described in claim 1, which is characterized in that the thickness of the buffer oxide nitride layer (Buffer OX)
About
5. etching technics as described in claim 1, which is characterized in that the thickness of the metallic aluminium hard mask layer is about
6. etching technics as described in claim 1, which is characterized in that the bottom anti reflective coatings (Barc) with a thickness of
Or the thickness of dielectric anti-reflective coating (Darc) is about
7. etching technics as described in claim 1, which is characterized in that the thickness of coating photoresist (PR) is about
8. the etching technics as described in claim 1-7 any one, which is characterized in that described to be carried out to metallic aluminium hard mask layer
Oxidation processes are using oxygen (O in short-term2) aoxidized.
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| CN201711139421.2A CN107731680B (en) | 2017-11-16 | 2017-11-16 | A kind of channel hole etching technics using hard exposure mask |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101558483A (en) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 3D IC method and device |
| US8394280B1 (en) * | 2009-11-06 | 2013-03-12 | Western Digital (Fremont), Llc | Resist pattern protection technique for double patterning application |
| CN105097496A (en) * | 2014-05-16 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
| CN106876396A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | A kind of semiconductor devices and preparation method thereof |
-
2017
- 2017-11-16 CN CN201711139421.2A patent/CN107731680B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101558483A (en) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 3D IC method and device |
| US8394280B1 (en) * | 2009-11-06 | 2013-03-12 | Western Digital (Fremont), Llc | Resist pattern protection technique for double patterning application |
| CN105097496A (en) * | 2014-05-16 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
| CN106876396A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | A kind of semiconductor devices and preparation method thereof |
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