CN107731680B - 一种采用硬掩膜的沟道孔刻蚀工艺 - Google Patents
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Abstract
本发明提供了一种采用新型硬掩膜的沟道孔刻蚀工艺,所述工艺包括:在堆叠结构上面的缓冲氧化物(Buffer OX)层上面采用金属铝作为硬掩膜层;所述金属铝硬掩膜层的厚度约在刻蚀前采用氯气(Cl2)刻蚀打开所述金属铝硬掩膜层;然后对金属铝硬掩膜层采用氧气进行短时氧化处理形成三氧化二铝(Al2O3)保护层;然后进行沟道孔的刻蚀以形成沟道孔;最后采用三氯化硼(BCl3)去除三氧化二铝(Al2O3)保护层。所述金属铝硬掩膜不会被刻蚀损坏,并可大幅降低厚度,从而能解决沟道孔变形以及部分沟道孔被封闭而缺失的问题,改善沟道孔的弧形弯曲形貌,并扩大底部关键尺寸(CD)。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种3D NAND闪存结构中改善沟道孔刻蚀工艺的方法。
背景技术
随着平面型闪存存储器的发展,半导体的生产工艺取得了巨大的进步。但是最近几年,平面型闪存的发展遇到了各种挑战:物理极限,现有显影技术极限以及存储电子密度极限等。在此背景下,为解决平面闪存遇到的困难以及最求更低的单位存储单元的生产成本,各种不同的三维(3D)闪存存储器结构应运而生,例如3D NOR(3D或非)闪存和3D NAND(3D与非)闪存。目前,在3D NAND的发展过程中,随着堆叠层数的增加,对刻蚀、沉积等制备工艺提出了更高的要求。
其中,对于刻蚀沟道孔(Channel Hole),现有技术在刻蚀之前,如图1所示,通常形成如下的堆叠结构:
在衬底上面设置O/N堆叠层1-1,其中最上层的牺牲介质层氮化硅上面沉积约的正硅酸乙酯(TEOS)1-2,正硅酸乙酯(TEOS)1-2上面沉积约的SiN阻挡层1-3,在阻挡层1-3上面形成约的缓冲氧化物层(Buffer OX)1-4,在缓冲氧化物(BufferOX)1-4上面形成约2.0μm的科迪亚克(Kodiak)无定型碳层1-5,科迪亚克(Kodiak)无定型碳层1-5的上面形成约的底部防反射涂层(Barc)或的电介质防反射涂层(Darc)1-6,再上面,是约的光刻胶层1-7。
这其中,约2.0μm的科迪亚克(Kodiak)无定型碳层1-5是用来作为硬掩膜来定义沟道孔的图案并保护O/N堆叠层。科迪亚克(Kodiak)无定型碳层是到目前为止可以使用的最硬的硬掩膜层。然而,在深孔刻蚀工艺中,科迪亚克(Kodiak)无定型碳层的硬度还是不够,并且科迪亚克(Kodiak)无定型碳层的厚度大,将导致等离子体离子的散射,而这将对沟道空造成损害。此外,采用科迪亚克(Kodiak)无定型碳层作为硬掩膜存在如下缺陷:如图2的沟道孔顶部形貌微观示意图所示,沟道孔变形以及部分沟道孔被封闭而缺失;以及如图3的沟道孔纵向截面形貌微观示意图所示,沟道孔具有弧形的弯曲形貌,并且底部关键尺寸(CD)较小。
上述由科迪亚克(Kodiak)无定型碳层作为硬掩膜导致的沟道孔的缺陷将影响3DNAND闪存整体的性能,因此,如何选择硬掩膜材料,以克服科迪亚克(Kodiak)无定型碳层的上述缺陷,从而制备更高良率的沟道孔一直为本领域技术人员所致力研究的方向。
发明内容
本发明的目的在于提供一种采用硬掩膜的沟道孔刻蚀工艺,通过选取新的硬掩膜材料,克服科迪亚克(Kodiak)无定型碳层的上述缺陷,从而改善沟道孔刻蚀的工艺;进而提高沟道孔制程良率。
为了实现上述目的,本发明采用的技术方案如下:
一种采用硬掩膜的沟道孔刻蚀工艺,包括以下步骤:
提供衬底;
在所述衬底上面形成O/N堆叠层;
在所述O/N堆叠层上面形成正硅酸乙酯(TEOS)层;
在所述正硅酸乙酯(TEOS)层上面沉积SiN阻挡层;
在所述阻挡层上面形成缓冲氧化物层(Buffer OX)层;
在所述缓冲氧化物(Buffer OX)层上面形成金属铝硬掩膜层;
在所述金属铝硬掩膜层的上面形成底部防反射涂层(Barc)或电介质防反射涂层(Darc);
在所述底部防反射涂层(Barc)或电介质防反射涂层(Darc)上面涂覆光刻胶(PR),并曝光形成沟道孔光刻图形;
根据所述沟道孔光刻图形刻蚀打开底部防反射涂层(Barc)或电介质防反射涂层(Darc);
继续向下刻蚀打开金属铝硬掩膜层;
对金属铝硬掩膜层进行短时氧化处理形成三氧化二铝(Al2O3)保护层;
进行沟道孔的刻蚀以形成沟道孔;
去除三氧化二铝(Al2O3)保护层。
进一步,所述金属铝硬掩膜层的厚度约
进一步,所述刻蚀打开金属铝硬掩膜层采用氯气(Cl2)处理。
进一步,所述对金属铝硬掩膜层进行短时氧化处理为采用氧气(O2)进行氧化。
进一步,所述去除三氧化二铝(Al2O3)保护层为采用三氯化硼(BCl3)进行刻蚀处理。
与现有技术相比,本发明的有益效果主要体现在:
第一,三氧化二铝(Al2O3)保护层不会被常规的刻蚀气体刻蚀,因此,在沟道孔刻蚀期间,该硬掩膜不会被损坏,从而能解决沟道孔变形以及部分沟道孔被封闭而缺失的问题。
第二,硬掩膜层的厚度相比科迪亚克(Kodiak)无定型碳层能降低90%以上,因此等离子的离子散射将降低,从而可以改善沟道孔的弧形弯曲形貌。
第三,由于可以忽略硬掩膜的损坏,易于通过增加偏压功率(bias power)来扩大底部关键尺寸(CD)。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。在附图中:
图1,为显示现有技术中采用科迪亚克(Kodiak)无定型碳层作为硬掩膜的沟道孔刻蚀前堆叠结构的示意图;
图2,为显示现有技术采用科迪亚克(Kodiak)无定型碳层作为硬掩膜刻蚀后的沟道孔顶部形貌微观示意图;
图3,为显示现有技术采用科迪亚克(Kodiak)无定型碳层作为硬掩膜刻蚀后的沟道孔纵向截面形貌微观示意图;
图4,为显示本发明采用金属铝作为硬掩膜层的沟道孔刻蚀前堆叠结构的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
为了清楚,不描述实际实施例的全部特征。在下列描述中,不详细描述公知的功能和结构,因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中,必须做出大量实施细节以实现开发者的特定目标,例如按照有关系统或有关商业的限制,由一个实施例改变为另一个实施例。另外,应当认为这种开发工作可能是复杂和耗费时间的,但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明提供一种采用硬掩膜的沟道孔刻蚀工艺,参考图4,包括以下步骤:
S100,提供衬底;
S200,在所述衬底上面形成O/N堆叠层100;
S700,所述金属铝硬掩膜500的上面形成底部防反射涂层(Barc)600或电介质防反射涂层(Darc)600′,所述底部防反射涂层(Barc)600的厚度为或电介质防反射涂层(Darc)600′的厚度约
S900,道孔光刻图形刻蚀打开底部防反射涂层(Barc)600或电介质防反射涂层(Darc)600′;
S1000,打开金属铝硬掩膜层500,所述刻蚀打开金属铝硬掩膜层500采用氯气(Cl2)处理;
S1100,对金属铝硬掩膜层500进行短时氧化处理形成三氧化二铝(Al2O3)保护层,所述氧化处理为采用氧气(O2)进行氧化;
S1200,进行沟道孔的刻蚀以形成沟道孔;
S1300,去除三氧化二铝(Al2O3)保护层;所述去除三氧化二铝(Al2O3)保护层为采用三氯化硼(BCl3)进行刻蚀处理。
Claims (8)
1.一种采用硬掩膜的沟道孔刻蚀工艺,其特征在于,包括以下步骤:
提供衬底;
在所述衬底上面形成O/N堆叠层;
在所述O/N堆叠层上面形成正硅酸乙酯(TEOS)层;
在所述正硅酸乙酯(TEOS)层上面沉积SiN阻挡层;
在所述阻挡层上面形成缓冲氧化物层(Buffer OX)层;
在所述缓冲氧化物(Buffer OX)层上面形成金属铝硬掩膜层;
在所述金属铝硬掩膜层的上面形成底部防反射涂层(Barc)或电介质防反射涂层(Darc);
在所述底部防反射涂层(Barc)或电介质防反射涂层(Darc)上面涂覆光刻胶(PR),并曝光形成沟道孔光刻图形;
根据所述沟道孔光刻图形刻蚀打开底部防反射涂层(Barc)或电介质防反射涂层(Darc);
采用氯气(Cl2)为反应气继续向下刻蚀打开金属铝硬掩膜层;
对金属铝硬掩膜层进行短时氧化处理形成三氧化二铝(Al2O3)保护层;
进行沟道孔的刻蚀以形成沟道孔;
采用三氯化硼(BCl3)进行刻蚀,去除三氧化二铝(Al2O3)保护层。
2.如权利要求1所述的刻蚀工艺,其特征在于,所述正硅酸乙酯(TEOS)层的厚度约
5.如权利要求1所述的刻蚀工艺,其特征在于,所述金属铝硬掩膜层的厚度约
8.如权利要求1-7任意一项所述的刻蚀工艺,其特征在于,所述对金属铝硬掩膜层进行短时氧化处理为采用氧气(O2)进行氧化。
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CN101558483A (zh) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 三维ic方法和器件 |
US8394280B1 (en) * | 2009-11-06 | 2013-03-12 | Western Digital (Fremont), Llc | Resist pattern protection technique for double patterning application |
CN105097496A (zh) * | 2014-05-16 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 刻蚀的方法 |
CN106876396A (zh) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | 一种半导体器件及其制作方法 |
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CN101558483A (zh) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 三维ic方法和器件 |
US8394280B1 (en) * | 2009-11-06 | 2013-03-12 | Western Digital (Fremont), Llc | Resist pattern protection technique for double patterning application |
CN105097496A (zh) * | 2014-05-16 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 刻蚀的方法 |
CN106876396A (zh) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | 一种半导体器件及其制作方法 |
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