CN107352503A - The anode linkage method and its application of polycrystalline silicon medium and glass on a kind of silicon substrate insulating barrier - Google Patents
The anode linkage method and its application of polycrystalline silicon medium and glass on a kind of silicon substrate insulating barrier Download PDFInfo
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- CN107352503A CN107352503A CN201610307164.8A CN201610307164A CN107352503A CN 107352503 A CN107352503 A CN 107352503A CN 201610307164 A CN201610307164 A CN 201610307164A CN 107352503 A CN107352503 A CN 107352503A
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- polysilicon
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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Abstract
The invention provides a kind of anode linkage method of polysilicon and glass on silicon substrate insulating barrier, methods described is：(1) layer insulating is deposited on silicon substrate face；(2) mask is made with photoresist, insulating barrier is performed etching, silicon substrate face is exposed to form slotted zones with the region that polysilicon will connect；(3) one layer of polysilicon is deposited on the insulating barrier in silicon substrate face for offering slotted zones, polysilicon turns in described slotted zones with silicon substrate；(4) polysilicon described in carries out anode linkage with glass；When silica glass bonding face region has high pressure sensitive structure, the inventive method makes bonding current, not by these structures, to realize that the electric property of MEMS is protected, while still ensure that the bond strength of polysilicon glass in anodic bonding process.
Description
(1) technical field
The invention belongs to semiconductor (MEMS) manufacturing field, it is related to anode linkage method, more particularly to
It when a kind of silicon on glass bonding face region there are high pressure sensitive structure (such as PN junction), can keep away these structures
The anode linkage method of highfield destruction is opened, to realize that bonding face region carries the MEMS of high pressure sensitive structure
Electric property protection of the device in bonding.
(2) background technology
Anode linkage is mainly used in the surface bond of glass and silicon, silicon-glass in MEMS technology field
The general principle of glass anode linkage is：300~1500V DC power anodes are connect into silicon chip, negative pole connects glass
Piece, because performance of the glass under certain high temperature is similar to electrolyte, and silicon chip be increased to 300 in temperature~
At 400 DEG C, resistivity will be down to 0.1 Ω m because of intrinsic excitation, and now the conducting particles in glass is (such as
Na+ the glass surface of negative electrode) is floated under External Electrical Field, and is left in the glass surface close to silicon chip
Negative electrical charge, because Na+ drift makes to produce electric current flowing in circuit, the glass surface close to silicon chip can be formed
The space-charge region (or depletion layer) that one layer of very thin width is about several microns.Because depletion layer is negatively charged,
Silicon chip is positively charged, so making both closely connect there is larger electrostatic attraction between silicon chip and glass
Touch, and physical-chemical reaction occurs in bonding face, the Si-O covalent bonds of strong bonded are formed, by silicon and glass
Interface is securely attached together.According to this general principle, in general anode linkage, bonding face region n
Be not suitable for the resistance that p doping be present on type silicon
Bar, reason are：The resistor stripe of p doping forms a PN junction with n-type silicon substrate, in anodic bonding process
When middle bonding current is by silicon on glass bonding face, up to 300~1500V bonding voltage is easily by bonding face
The PN junction reverse breakdown in region, causes its electric leakage, destroys the circuit in MEMS, influences device
Performance.
Therefore, for above-mentioned problems of the prior art, it is necessary to provide one kind in si-glass key
When conjunction face region there are high pressure sensitive structure (such as PN junction), these structures can be made to avoid highfield destruction
Anode linkage method, with realize bonding face region with high pressure sensitive structure MEMS bonding when
Electric property is protected.
(3) content of the invention
It is an object of the invention to：A kind of anode linkage method of polysilicon and glass in silicon substrate is provided, this
Kind of method especially suitable for when silicon on glass bonding face region there are high pressure sensitive structure (such as PN junction),
Make bonding current in anodic bonding process not by these structures, to realize the electric property of MEMS
Protection.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of anode linkage method of polysilicon and glass in silicon substrate, methods described are carried out as follows：
(1) layer insulating is deposited on silicon substrate face, the material of the insulating barrier is selected from SiO2, Si3N4
Or SiC；
(2) mask is made with photoresist, insulating barrier is performed etching, silicon substrate face and polysilicon will be connected
Logical region is exposed to form slotted zones；
(3) one layer of polysilicon is deposited on the insulating barrier in silicon substrate face for offering slotted zones, polysilicon exists
Described slotted zones turn on silicon substrate；
(4) polysilicon described in carries out anode linkage with glass.
The anode linkage method of polysilicon and glass in silicon substrate of the present invention, the deposition of insulating barrier in step (1)
It can use
One of following method：1. using plasma enhanced chemical vapor deposition method (PECVD) is in silicon substrate face
Upper depositing insulating layer；2. using the method for low-pressure chemical vapor deposition (LPCVD) process deposits film；It is described
The thickness of insulating barrier is 0.5~1 μm；The insulating barrier covers silicon substrate to ensure high pressure sensitizing range (such as PN
Tie region) insulating properties between bond area.
Insulating barrier, which is performed etching, described in step (2) of the present invention can use RIE etchings (Reaction Ion
Etching, reactive ion etching) or wet etching；The slot area of the insulating barrier will be uniformly distributed as far as possible,
And area is as far as possible big, it should also be noted that the position of fluting will try one's best away from high pressure sensitizing range,
Different slotting positions can be selected by different structures and performance requirement for different devices, the present invention is simultaneously
The position for not having cross-notching is limited, as long as being slotted using depositing insulating layer and photoetching corrosion, and is deposited more
Crystal silicon turns on it with silicon substrate to realize the anode linkage of polysilicon and glass, then it is located in the present invention's
In protection domain.
In step (3) of the present invention the deposition process of polysilicon can using plasma enhanced chemical gas phase sink
Area method is carried out；Non-slotted area's thickness of the polysilicon deposited on the insulating barrier in silicon substrate face is 2~4 μm, excellent
Elect 3 μm as.
The anode linkage method of polysilicon and glass in silicon substrate of the present invention, when being bonded in silicon substrate with glass
There is high pressure sensitive structure in face region, during such as PN junction, preferably using the inventive method, silicon is carried out with this method
The anode linkage of polysilicon and glass on base, make bonding current in anodic bonding process not by these structures,
To realize that the electric property of MEMS is protected
Shield.
Silicon substrate of the present invention can be N or P-type silicon substrate.
In step (4) of the present invention, the technological parameter of anode linkage is：300~1000V of voltage, electric current
15~25mA, 300~400 DEG C, 2000~3000N of pressure, 5~20min of time of temperature；Preferred anodes
The technological parameter of bonding is：450~1000V of voltage, 20~25mA of electric current, 350~380 DEG C of temperature, pressure
2500~3000N of power, 10~20min of time.
The anode linkage method of polysilicon and glass can be applied to wafer level envelope on silicon substrate insulating barrier of the present invention
Dress, wafer-level package or system in package；It should be noted that the region of insulating barrier corrosion needs as far as possible completely
Foot states condition：
(a) as far as possible away from circuit high pressure sensitizing range, avoid big voltage (electric current) destroy device electricity
Learn performance；
(b) it is uniformly distributed as far as possible to ensure that bonding voltage is uniformly distributed；
(c) area is as far as possible big, to ensure that electric current smoothly can lead to polysilicon from silicon substrate；
(d) on the premise of ensureing to meet device architecture with performance requirement, the volume of device is not increased as far as possible,
The quantity of domain is reduced as far as possible.
When in applied to wafer level packaging, the preferably slot area of insulating barrier is in burst groove location, so
Do and meet four conditions of the above well, any other silicon substrate-polysilicon that can meet above-mentioned 4 points requirement
Connected region distribution can all be used, and those skilled in the art can also be taken by actual conditions to above-mentioned condition
House.Compared with prior art, anode linkage method of the present invention possesses following advantage：
High bonding voltage during in general silicon on glass bonding is easily sensitive by the high pressure in bonding face region
Structure (such as PN junction) punctures, and the electric property for causing to be bonded later device is destroyed.This method is dexterously
High pressure sensitizing range is isolated with bonding face using insulating barrier, by corroding fluting and deposit polycrystalline silicon and silicon substrate
Conducting, makes electric current during bonding directly lead to polysilicon from silicon substrate, avoids high pressure sensitive structure in silicon substrate (such as
PN junction), finally realize the anode linkage of polysilicon and glass.Also, by bonding current figure and micro-
Microscopic observation understands that this polycrystalline silicon-glass anodic bonding still can guarantee that the bond strength close to si-glass.
On the other hand, using insulating barrier will be bonded glass and circuit separate can ensure circuit in technical process not by
The metal ion pollution such as Na+ in glass.
(4) illustrate
Fig. 1 is the diagrammatic cross-section of polysilicon and glass anode linkage in silicon substrate of the present invention；
Fig. 2 is the device architecture top view in embodiment 1, embodiment 2 or comparative example；
Fig. 3 (a)~3 (f) is that the technological process section of embodiment 1 or the bonding of the Anodic of embodiment 2 shows
It is intended to；
Fig. 3 (a) is the schematic diagram of depositing insulating layer；
Fig. 3 (b) is the schematic diagram of etching insulating layer；
Fig. 3 (c) is the schematic diagram of deposit polycrystalline silicon；
Fig. 3 (d) is the schematic diagram for etching pin region；
Fig. 3 (e) is the schematic diagram of polysilicon and glass anode linkage；
Fig. 3 (f) is the schematic diagram of scribing；
Fig. 4 is the bonding current figure of embodiment 1；
Fig. 5 is the bonding face microphoto of embodiment 1；
Fig. 6 is the bonding face microphoto of embodiment 2；
Fig. 7 is the diagrammatic cross-section of comparative example silicon-glass anodic bonding；
The implication of each numeral mark is in accompanying drawing：1- bonding glass, 2- polysilicons, 3- insulating barriers, 4- are high
Press sensitive structure, 5- silicon substrates, the 6- senses of current, 7- burst grooves, 8- bonding regions, 9- workspaces, 10-
Concentrated boron area (embodiment 1 or comparative example)/Nong Lin areas (embodiment 2), 11- pins, 12-PN knots.
(5) embodiment
Below by specific embodiment, the invention will be further described, but protection scope of the present invention is not
It is only limitted to this.
Embodiment 1
One kind is based on n-type silicon substrate, makees conductor connecting pipe pin and anode linkage region overlay with dense boron
Device in the case of the domain of concentrated boron area, as shown in Figure 2.Because bond area is there is multiple PN junctions, if directly
Connect the anode linkage using si-glass, it is likely that cause PN junction breakdown, influence the electric property of device.
Bond area can then be protected using the inventive method
PN junction, the electric property of protection device.
Fig. 3 (a)~3 (f) is shown under the above situation in order to avoid PN junction region has big voltage (electricity
Stream) used in anode linkage method, detailed process is as follows：
(1) as shown in Fig. 3 (a), PECVD grows a layer insulating 3 on silicon substrate 5；Institute
It is n-type silicon substrate to state silicon substrate；The insulating barrier is Si3N4 insulating barriers, and thickness is 1 μm；PECVD
Technological parameter：365 DEG C of temperature, gas flow SiH4: N2: NH3=10/100/500, pressure 2Torr, high frequency
300W, speedTime 36min.
(2) as shown in Fig. 3 (b), rotation smears the photoresist of 8 μ m-thick 4620 and makees mask lithography burst
Groove region, RIE etch Si3N4 insulating barriers to silicon substrate；RIE technological parameters：Gas flow
CF4/RF=40/200, pressure 3Pa, speedTime 14min.In the present embodiment, selection point
Runner region is used as the corrosion area (connected region of silicon substrate-polysilicon) of insulating barrier, has following excellent
Point：
(a) burst groove location and device PN junction are distant, are avoided that the big voltage (electric current) during bonding
These PN junctions are destroyed, influence device electric property；
(b) burst groove location is uniformly distributed in disk, ensures that bonding voltage is uniformly distributed；
(c) burst groove location area is sufficiently large, to ensure that electric current smoothly can lead to polysilicon from silicon substrate；
(d) connected region of the burst groove location as silicon substrate-polysilicon is selected, can ensure to meet device
On the premise of structure and performance requirement, do not increase the volume of device as far as possible, reduce the quantity of domain as far as possible.
(3) as shown in Fig. 3 (c), PECVD grows one layer of polysilicon 2, the thickness of the polysilicon
For 3 μm；Pecvd process parameter：365 DEG C of temperature, gas flow SiH4: N2=30/1000, pressure
2.4Torr, high frequency 350W, speedTime 30min.
(4) as shown in Fig. 3 (d), the AZ4620 photoresists that rotation smears 8 μm make mask lithography pipe
The region of pin 11, is sequentially etched polysilicon and Si3N4 insulating barriers；Described etching technics uses RIE；RIE
Technological parameter：Gas flow CF4/RF=60/200, pressure 3Pa, time 28min.
(5) as shown in Fig. 3 (e), polysilicon and glass anode linkage.
Anode linkage technique uses following technological parameter：
| Voltage (V) | Electric current (mA) | Temperature (DEG C) | Pressure (N) | Time (min) |
| 450 | 20 | 360 | 2400 | 20 |
It is observed that from Fig. 4, Fig. 5：On the one hand, polysilicon and glass anode linkage completely into
Work(, and there is preferable bond strength, on the other hand, current curve, which can be seen that electric current, from Fig. 4 is
Turned on by silicon-polycrystalline si-glass, and turned on not by silicon-intermediate layer (insulating barrier)-glass.
(6) as shown in Fig. 3 (f), scribing is to realize the encapsulation of one single chip.Scribing makes two bites at a cherry,
First time scribing, remove glass above pin；Second of scribing, scratches structure in burst groove, and separation is single
Chip simultaneously is completed to encapsulate.
Embodiment 2
One kind is based on p-type silicon substrate, makees conductor connecting pipe pin and anode linkage region overlay with dense phosphorus
Device under dense phosphorus areas case, as shown in Figure 2.Same as Example 1, bond area equally exists
Multiple PN junctions, if directly using the anode linkage of si-glass, it is likely that cause PN junction breakdown, influence device
The electric property of part.The PN junction of bond area, the electrical property of protection device can be then protected using the inventive method
Energy.
Fig. 3 (a)~3 (f) is shown under the above situation in order to avoid PN junction region has big voltage (electricity
Stream) used in anode linkage method, detailed process is as follows：
(1) as shown in Fig. 3 (a), PECVD grows a layer insulating on a silicon substrate；The silicon lining
Bottom is p-type silicon substrate；The insulating barrier is SiO2 insulating barriers, and thickness is 1 μm；Pecvd process is joined
Number：365 DEG C of temperature, gas flow SiH4: N2: NO2=9/900/900, pressure 2Torr, high frequency 300W,
SpeedTime 29min.
(2) as shown in Fig. 3 (b), rotation smears the photoresist of 8 μ m-thick 4620 and makees mask lithography burst
Groove region, RIE etch SiO2 to silicon substrate；RIE technological parameters：Gas flow CF4/RF=40/300,
Pressure 3Pa, speedTime 18min.In the present embodiment, a point runner region is selected to be used as absolutely
The corrosion area (connected region of silicon substrate-polysilicon) of edge layer, there is following advantage：
(a) burst groove location and device PN junction are distant, are avoided that the big voltage (electric current) during bonding
These PN junctions are destroyed, influence device electric property；
(b) burst groove location is uniformly distributed in disk, ensures that bonding voltage is uniformly distributed；
(c) burst groove location area is sufficiently large, to ensure that electric current smoothly can lead to polysilicon from silicon substrate；
(d) connected region of the burst groove location as silicon substrate-polysilicon is selected, can ensure to meet device
On the premise of structure and performance requirement, do not increase the volume of device as far as possible, reduce the quantity of domain as far as possible.
(3) as shown in Fig. 3 (c), PECVD grows one layer of polysilicon；The thickness of the polysilicon
For 2 μm；
Pecvd process parameter：365 DEG C of temperature, gas flow SiH4: N2=30/1000, pressure 2.4Torr are high
Frequency 350W, speedTime 20min.
(4) as shown in Fig. 3 (d), the AZ4620 photoresists that rotation smears 8 μm make mask lithography pipe
Pin region, it is sequentially etched polysilicon and SiO2 insulating barriers；Described etching technics uses RIE；RIE works
Skill parameter：Gas flow CF4/RF=60/200, pressure 3Pa, time 25nin.
(5) as shown in Fig. 3 (e), polysilicon and glass anode linkage.
Anode linkage technique uses following technological parameter：
| Voltage (V) | Electric current (mA) | Temperature (DEG C) | Pressure (N) | Time (min) |
| 450 | 20 | 360 | 2400 | 20 |
From Fig. 6 it is observed that：Polysilicon has been completely successful with glass anode linkage, and with preferable
Bond strength.
(6) as shown in Fig. 3 (f), scribing is to realize the encapsulation of one single chip.Scribing makes two bites at a cherry,
First time scribing, remove glass above pin；Second of scribing, scratches structure in burst groove, and separation is single
Chip simultaneously is completed to encapsulate.
Comparative example：
One kind is based on n-type silicon substrate, makees conductor connecting pipe pin and anode linkage region overlay with dense boron
Device in the case of the domain of concentrated boron area, as shown in Figure 2.Bond area is there is multiple PN junctions, here directly
Using the anode linkage of si-glass.Show in Fig. 7 and be directly bonded using silicon-glass anodic bonding scheme
When the sense of current, the sense of current along n-type silicon (N)-dense boron (P)-glass, in bonding process silicon and
The resistance very little of glass, can regard an equipotentiality body as, and the big voltage in anodic bonding process is applied directly to key
On conjunction face, PN junction direction in figure is punctured, causes the electric current that encapsulation is loaded on pin later directly by dense
Boron flows to silicon substrate, device is produced leaky.
Existing anode linkage Technical comparing is ripe, is a special kind of skill known to various equivalent modifications,
But very big voltage is needed when its shortcoming is bonding, and is concentrated mainly on bond area surface, because
Bond area should not typically have high voltage sensitive structure (for example PN junction) during this design, even if having to
It can typically be adopted if high voltage sensitive structure being present
Take other packaged types.
But this patent is used as middle conductting layer by polysilicon, will directly add electric current on a silicon substrate
" drawing ", on polysilicon, the height of bond area was avoided by using the sense of current of silicon-polycrystalline si-glass
Voltage-sensitive structure is destroyed, and protects the electric property of whole circuit, this anode linkage method for packing
It can be used for wafer level packaging, can be used for wafer-level package.
Claims (10)
1. a kind of anode linkage method of polysilicon and glass in silicon substrate, it is characterised in that methods described is as follows
Carry out：
(1) deposit a layer insulating in silicon-based substrate, the material of the insulating barrier be selected from SiO2, Si3N4 or
SiC；
(2) mask layer is made with photoresist, insulating barrier is performed etching, silicon substrate face will be connected with polysilicon
Region is exposed to form slotted zones；
(3) one layer of polysilicon is deposited on the insulating barrier in silicon substrate face for offering slotted zones, polysilicon is described
Slotted zones turn on silicon substrate；
(4) polysilicon described in carries out anode linkage with glass.
2. the anode linkage method of polysilicon and glass on silicon substrate insulating barrier as claimed in claim 1, its feature exist
The deposition of insulating barrier is using one of following method in step (1)：1. use PECVD plasma enhancings
Type chemical vapour deposition technique depositing insulating layer on silicon substrate face；2. use LPCVD low-pressure chemical vapor depositions
The method of process deposits film.
3. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 1, it is characterised in that step
(1) thickness of insulating barrier is 0.5~1 μm in.
4. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 1, it is characterised in that step
(2) insulating barrier is performed etching described in using RIE etchings or wet etching.
5. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 1, it is characterised in that step
(3) deposition process of polysilicon is carried out using PECVD plasma enhanced chemical vapor depositions method in.
6. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 1, it is characterised in that step
(3) non-slotted area's thickness of the polysilicon deposited on the insulating barrier in silicon substrate face is 2~4 μm.
7. the anode linkage method of polysilicon and glass in the silicon substrate as described in one of claim 1~6, its feature
It is high pressure sensitive structure be present with glass bonding face region in described silicon substrate.
8. the anode linkage method of polysilicon and glass in the silicon substrate as described in one of claim 1~6, its feature
It is that described silicon substrate is N or P-type silicon substrate.
9. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 1, it is characterised in that step
(4) in, technological parameter when described polysilicon carries out anode linkage with glass is：300~1000V of voltage,
15~25mA of electric current, 300~400 DEG C, 2000~3000N of pressure, 5~20min of time of temperature.
10. the anode linkage method of polysilicon and glass in silicon substrate as claimed in claim 9, it is characterised in that step
Suddenly in (4), the when technological parameter that described polysilicon carries out anode linkage with glass is：450~1000V of voltage,
20~25mA of electric current, 350~380 DEG C, 2500~3000N of pressure, 10~20min of time of temperature.
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| CN201610307164.8A CN107352503A (en) | 2016-05-09 | 2016-05-09 | The anode linkage method and its application of polycrystalline silicon medium and glass on a kind of silicon substrate insulating barrier |
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| WO2019169728A1 (en) * | 2018-03-06 | 2019-09-12 | 苏州大学张家港工业技术研究院 | Nano-gap in-situ activation-based composite anodic bonding method |
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Application publication date: 20171117 |