CN1067773A - The circuit of sensing back-bias level in semiconductor memory device - Google Patents
The circuit of sensing back-bias level in semiconductor memory device Download PDFInfo
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Abstract
Be used for an anti-level sensor partially of semiconductor device, wherein the current sensor (I50) in order to sensing reversed bias voltage (VBB) is prevented from flowing directly into substrate (or reversed bias voltage terminal).The grid of a PMOS transistor (50) is provided to this reversed bias voltage, and its source electrode is provided to ground voltage, at reversed bias voltage (VBB) when being lower than predetermined voltage level, a pump circuit (300) thus carrying out the pumping operation increases reversed bias voltage.Otherwise, remove excitation, thereby reduce reversed bias voltage pump circuit (300).
Description
The present invention relates to semiconductor storage unit, be specifically related in order to the circuit of sensing by the back-bias level of reverse bias generator generation.
The negative voltage of predetermined level will be provided for the substrate of semiconductor storage unit usually, so that the threshold level of the MOS transistor that is comprised in the memory device is stable, thus the bad work that prevents to produce parasitic transistor and prevent the memory device that the undershoot (undershoot) owing to external signal produces.For example, have under the situation in the DRAM unit as the nmos pass transistor of memory cell and a N type conductive polycrystalline silicon capacitor (or capacitor) with N type conductive type diffusion, must go up the utmost point in substrate the plate electrode of capacitor (or) to apply-2V is to the specific voltage of-2.5V.This voltage is called reversed bias voltage or underlayer voltage.In general, have in order to the circuit (hereinafter referred is " a reverse bias generator ") that produces reversed bias voltage: a pump circuit, in order to keep the constant negative voltage that reversed bias voltage is a predetermined level; One in order to drive the oscillator of said pump circuit; And an anti-level sensor partially, control above-mentioned oscillator in order to the reversed bias voltage level that sensing is current with the response sensing signal.
With reference to Fig. 1, the figure shows the schematic diagram of such reverse bias generator, oscillator 100 normally is made up of a chain of inverters among the figure, and pump circuit 300 comprises a capacitor, in order to response by oscillator 100 through driver 200 to the pumping frequency clock signal of its supply with the pumping reversed bias voltage.Again reversed bias voltage VBB is fed back to oscillator 100 through anti-level sensor 400 partially.Anti-level sensor partially 400 responds the output that the sensing signal of current anti-level VBB is partially changed oscillator 100.Also in other words, if current anti-level partially is lower than required level (in this case, owing to must improve anti-level partially), anti-level sensor 400 partially is to this situation of oscillator 100 " reflection ", so oscillator 100 responds the output signal of anti-level sensor 400 partially and produces a control signal (or pumping frequency clock signal) in order to excitation pump circuit 300.For this reason, pump circuit 300 is carried out the pumping operation, can make low reversed bias voltage level VBB be elevated to required voltage level whereby.
It should be noted that for convenience's sake, anti-in this manual level partially refers to absolute value.Under opposite situation, if current reversed bias voltage VBB is higher than required level (being somebody's turn to do anti-inclined to one side level owing to reducing in this case), oscillator 100 responses are produced a control signal to stop pump circuit 300 execution pumping operations by the sensing signal of anti-inclined to one side level sensor 400.
To the anti-basic demand of level sensor partially is sensing reversed bias voltage VBB and reversed bias voltage VBB not being had a direct impact itself effectively.The voltage divider that a traditional anti-example of level sensor has partially used resistance or resistance element to form, this device was disclosed in the laid-open U.S. Patents 4,471,290 on September 11st, 1984.In the disclosure patent, anti-level sensor partially comprise form by series resistance R1 and R2, be connected a voltage divider between reversed bias voltage and the ground voltage.The input of the connected node of series resistance and a level sensor is coupled.
In view of the above, the connected node of this voltage divider is to have its value for VBBR2/(R1+R2) reversed bias voltage, then with this voltage level of dividing potential drop compare with a reference level at the level sensor place.Level sensor is given oscillator with this comparison signal " reflection ".Yet, always between reversed bias voltage terminal and ground voltage terminal, form electric current through series resistance R1 and R2, the result, not only because the hole current in the Semiconductor substrate, and because the electric current (that is, electric current) of the series resistance of flowing through and cause the deterioration (degradation) of reverse bias from the ground voltage terminal to the reversed bias voltage terminal.
Traditional anti-another example of level sensor partially is shown in Fig. 2.This circuit utilization connects into the rectification characteristic of the MOS transistor of diode.As shown in the figure, PMOS transistor 21 and nmos pass transistor 23 conducting always, the bleeder mechanism that the voltage of its connected node 22 is made up of MOS transistor 21,23 and 24 is determined.Be connected with the oscillator 100 of Fig. 1 through a delay circuit 26 with 23 connected node 22 with supply voltage VCC MOS transistor 21 that be coupled, that be connected in series.PMOS transistor 24 is coupling between nmos pass transistor 23 and the reversed bias voltage VBB, and raceway groove one end of PMOS transistor 24 and grid coupled in common are to reversed bias voltage VBB, and the raceway groove of the other end of raceway groove and nmos pass transistor 23 is coupled.The voltage of connected node 22 imposes on oscillator 100 through delay circuit 26, and this voltage can be adjusted on the voltage VBBD by the size that changes MOS transistor 21,23 and 24 in advance.
Below with reference to Fig. 3 A to 3F the anti-operation of level sensor partially that this is traditional is described.In these accompanying drawings, show reversed bias voltage VBB respectively, flow to the passage current Ix of reversed bias voltage terminal VBB, the voltage V22 of connected node 22, the output voltage V 28 of delay circuit 26, the output voltage V osc and the anti-detailed voltage response of level sensor partially of oscillator 100 from supply voltage VCC.It should be noted that passage current Ix is directly proportional with reversed bias voltage VBB.As shown in Fig. 3 A, till t1 constantly, voltage VBB is the negative value that is lower than voltage VBBD, thereby passage current Ix is greater than t1 electric current constantly, its reason is that passage current Ix flows into reversed bias voltage terminal VBB, therefore, owing to the hole current of passage current Ix(and substrate) the reversed bias voltage level has undesirably been improved.This existing picture is called " deterioration of reversed bias voltage ".
Simultaneously, become equal fully mutually at t1 moment voltage VBB and VBBD.After this absolute value of voltage VBB is gradually less than voltage VBBD, thereby passage current Ix descends, and the voltage level of connected node 22 raises.In this moment, the passage current Ix that flows into reversed bias voltage terminal VBB descends.So the voltage V22 of connected node 22 raises, thereby make delay circuit 26 output voltage V 28 output, that impose on oscillator 100 become logic high (seeing Fig. 3 C and 3D).After this, oscillator 100 is allowed to work, thereby and produces pumping frequency clock signal shown in Fig. 3 E, that be applied to pump circuit 300 so that pump circuit 300 is carried out the pumping operation of reversed bias voltage constantly from t2.In carrying out voltage pumping operation, if intersect with voltage VBBD value at t3 moment voltage VBB, then the voltage V22 of connected node 22 reduces, thereby makes the input voltage of oscillator 100 become logic low constantly at last at t4, shown in Fig. 3 E,, pumping suspends constantly so that operating in t4.Because at this moment passage current Ix just flowed into reversed bias voltage terminal VBB when pumping operated in t4 and suspends constantly, thereby the absolute value of reversed bias voltage will descend once more.Meanwhile, be lower than voltage VBBD if reversed bias voltage VBB becomes constantly at t5, then above-mentioned operation will repeat.
Refer again to the anti-concrete working curve of level sensor 400 partially that Fig. 3 F illustrates Fig. 2.In the figure, curve V22, V27 and V29 represent the voltage at connected node 22,27 and 29 places respectively.Because for the anti-grid of the PMOS transistor 21 of level sensor 400 partially provides ground voltage VSS, so gate source voltage Vgs has a constant voltage, and this voltage and power source voltage Vcc have nothing to do.Because the variation of supply voltage, the voltage at output node 22 places is subjected to quite big influence, shown in Fig. 3 F.In addition,, passage current Ix needs considerable time, so anti-transducer partially has the slow-response characteristic owing to flowing through two MOS transistor 23 and 24.
As mentioned above, traditional anti-level sensor partially shown in Figure 2 is designed such that reversed bias voltage terminal VBB sensing reversed bias voltage under the direct influence of passage current, therefore causes the deterioration of reversed bias voltage mainly due to the hole current of passage current (being used for the anti-level partially of sensing) and substrate.Consequently: oscillator 100 in the traditional reverse bias generator of connection/shutoff and pump circuit 300 are just inevitable continually, thereby make the anti-reliability decrease of level sensor partially, also make the total current drain quantitative change height of reverse bias generator.Moreover, as shown in Figure 3A,, on reversed bias voltage terminal VBB, produce peak current owing to the pumping operation changes under the situation of a different voltage level reversed bias voltage VBB suddenly.If because extremely frequent pumping operation and often produce this peak current, then this device may experience bad operation and has defective in other words, in the worst case, the dielectric breakdown phenomenon of PMOS transistor 24 will take place at its grid oxic horizon.Under this United States Patent (USP) and Fig. 2 both of these case, in view of being subjected to its current sensor, reversed bias voltage directly influences this fact, and above-mentioned identical worst case all can take place in them.Specifically, owing to the voltage and the independent of power voltage that in the circuit of Fig. 2, are applied on load PMOS transistor 21 grids, therefore because the variation of supply voltage makes this anti-level sensor partially be subjected to very big influence.Utilize anti-any reverse bias generator of level sensor partially all can have same problem as mentioned above for those skilled in the art should further appreciate that.
For this reason, an object of the present invention is to provide a kind of, sensing anti-partially circuit of level that use, that have high reliability for the reverse bias generator.
Another object of the present invention provides a kind of reverse bias generator with low current drain.
Another purpose of the present invention provides a kind of circuit quick sense operation and high reliability, the anti-inclined to one side level of sensing that has.
According to an aspect of the present invention, the circuit in order to sensing reversed bias voltage level in having the reverse bias generator of pump circuit contains: a control terminal that is coupled with reversed bias voltage; A sensing terminals that is coupled with pump circuit by the driver of driving pump circuit; And a conducting channel, in order to response reversed bias voltage level, and with sensing terminals and the electric connection of ground reference voltage terminal, this raceway groove is insulated on electric with control terminal mutually by insulation component.
According to a further aspect in the invention, the reverse bias generator (this generator has: a pump circuit, in order to the reversed bias voltage with preset level to be provided to substrate; With an oscillator, in order to the pumping frequency clock signal to be provided to pump circuit) in the circuit in order to sensing reversed bias voltage level contain: a PMOS transistor, the voltage VCC/2 that its grid and container flat voltage (cell plate voltage) generator comes is coupled, one end and the supply voltage of its raceway groove are coupled, and the input terminal of the other end of its raceway groove and oscillator is coupled; And the 2nd PMOS transistor, its grid and reversed bias voltage are coupled, and an end and the ground voltage of its raceway groove are coupled, and the other end of its raceway groove and the transistorized raceway groove of a PMOS are coupled.
In order to understand the present invention better and in order to show how the present invention is implemented, referring now to following exemplary accompanying drawing:
Fig. 1 illustrates the block diagram as the reverse bias generator citation form of prior art;
Fig. 2 illustrates traditional anti-block diagram of level sensor partially;
Fig. 3 A to 3F illustrates traditional anti-working waveform figure of level sensor partially of Fig. 2;
Fig. 4 illustrates an anti-embodiment of level sensor partially of the present invention;
Fig. 5 illustrates anti-another embodiment of level sensor partially of the present invention;
Fig. 6 illustrates anti-another embodiment of level sensor partially of the present invention;
Fig. 7 illustrates the reverse bias transducer of the present invention that is used for Fig. 1 reverse bias generator;
Fig. 8 A to 8F illustrates the anti-working waveform figure of level sensor partially of the present invention.
With reference to Fig. 4, an anti-embodiment of level sensor partially of the present invention has: PMOS transistor 31, nmos pass transistor 33 and a delay circuit 36 to connect with the traditional anti-partially mode that level sensor is identical.Yet PMOS transistor 34 is connected between nmos pass transistor 33 and the ground voltage level Vss, and the grid of PMOS transistor 34 and reversed bias voltage VBB are coupled.The voltage level at MOS transistor 31 that is connected in series and 33 connected node 32 places is relevant with the work of PMOS transistor 34.
Referring now to another embodiment of the present invention shown in Figure 5.As shown in the figure, the grid of load PMOS transistor 11 provides container flat voltage VCC/2, and an end and the supply voltage of its raceway groove are coupled, and the other end of raceway groove and output node 12 are coupled.In addition, the grid and the reversed bias voltage VBB that drive PMOS transistor 13 are coupled, and an end and the ground voltage of its raceway groove are coupled, and the other end of its raceway groove and output node 12 are coupled.Here should be noted that this embodiment has the driving element of being made up of single PMOS transistor 13, thereby, to compare with the circuit of Fig. 2 and Fig. 4, it has quickish response characteristic.Being appreciated that by mentioned earlier that this embodiment is designed to be makes electric current not flow into reverse bias terminal VBB from power supply voltage terminal VCC, and provide constant voltage VCC/2 to the grid of PMOS transistor 11, so it can prevent the sudden change of the passage current Ix that causes owing to mains voltage variations.Simultaneously, the known container flat voltage of those of skill in the art VP is the voltage that is produced by container flat voltage generator (not drawing among the figure), is generally VCC/2.
With reference to Fig. 6, anti-another embodiment of level sensor partially of the present invention has a plurality of PMOS transistors 41,44,46, each transistorized grid all is connected with an end of each raceway groove, and these three PMOS transistors are connected in series between supply voltage VCC and the ground voltage VSS mutually.Tie point place in PMOS transistor 44 and 46 forms bias voltage node 45. PMOS transistor 41,44,46 forms bias circuit with bias voltage node 45, and the voltage of bias voltage node 45 is 1/3VCC, if these three PMOS transistors all have identical size.Bias voltage node 45 is coupled with the grid of PMOS transistor 48, and the raceway groove of this transistor 48 is connected between supply voltage VCC and the sense node 49.The grid of PMOS transistor 48 provides constant voltage by bias voltage node 45, so that PMOS transistor 48 is as a load elements, constant current flows through this load elements and flows into sense node 49.The grid of PMOS transistor 50 provides reversed bias voltage VBB, and this transistor 50 is coupling between sense node 49 and the ground voltage VSS.With Fig. 4 and embodiment illustrated in fig. 5 identical, the voltage level of sense node 49 is relevant with the work of PMOS transistor 50.
With reference to Fig. 4 and Fig. 6, should be noted that transistor 34,13 and 50 all is the PMOS transistor, its grid all is coupled with reversed bias voltage VBB, however the semiconductor device of other type that channel current can be controlled by insulated gate can use according to identical purpose.
With reference to Fig. 7, of the present invention anti-level sensor 40 partially shown in Figure 6 is used for reverse bias generator shown in Figure 1.As shown in the figure, reversed bias voltage VBB coupled in common is to the output of pump circuit 300 and the grid of the PMOS transistor 50 in the anti-level sensor 40 partially.The sense node 49 of anti-level sensor 40 partially is coupled through an input of the input nand gate 61 in delay circuit 51 and the oscillator 100.Be understood that oscillator 100 is allowed to work or is not allowed to work in response to the logical value of NAND gate 61 inputs (that is: sense node 49 is connected with this input of this NAND gate 61).Oscillator 100 is known circuit, and inverter 62 and 63 output 101 and 102 are applied on the pump circuit 300 through driver 200 respectively in it.Pump circuit 300 comprises a plurality of PMOS capacitors and a plurality of PMOS transistor, is appreciated that reversed bias voltage VBB is increased sharp when the pumping clock signal from pump signal line 301-304 all is logic low, thereby increases the absolute value of reversed bias voltage VBB.It should be noted that in Fig. 7, except anti-level sensor 40 partially, oscillator 100, driver 200 and pump circuit 300 all are known traditional circuit.
Hereinafter illustrate the working condition of anti-level sensor partially of the present invention and reverse bias generator with reference to Fig. 8 A to 8F.Show reversed bias voltage VBB(Fig. 8 A among these figure respectively), flow to current sensor I50(Fig. 8 B of ground voltage VSS through PMOS transistor 50 from anti-level sensor partially), at voltage V49(Fig. 8 C that sense node 49 changes with sensing electric current I 50), output voltage V 52(Fig. 8 D of delay circuit 51), output voltage V 101 and V102(Fig. 8 E on the line 101 and 102 of oscillator 100) and the voltage response (Fig. 8 F) of V49 and Va.
With reference to Fig. 8 F, curve Va and V49 represent the node " a " of delay circuit 51 and the voltage characteristic of output node 49 respectively especially.When contrasting with Fig. 3 F, it should be noted that response characteristic is improved significantly, this is because the result that the driving stage of anti-level sensor is partially simplified.
Refer again to Fig. 7 and Fig. 8 A to 8F now conversely, hereinafter will describe the anti-working condition of level sensor partially of the present invention by way of example.
At first it should be noted, hereinafter for for simplicity, only the situation that the anti-level sensor 40 partially of Fig. 6 is used for the reverse bias generator of Fig. 1 is considered as an example, but its working condition is considered to carry out in an identical manner in the situation of the anti-level sensor 30 partially of application drawing 4 and Fig. 5.
In Fig. 8 A, up to T11 constantly before, reversed bias voltage VBB(hereinafter refers to its absolute value) voltage level be higher than the voltage level VBBD that can allow oscillator 100 work so that reverse bias is cancelled excitation.Meanwhile, descend if supply with the reversed bias voltage VBB of PMOS transistor 50 grids, then PMOS transistor 50 little by little becomes nonconducting state.At last, be lower than voltage VBBD if reversed bias voltage VBB becomes constantly through T11, then current sensor I50 will reduce.
From T11 forward, the voltage V49 at sense node 49 places reduces along with I50 and raise gradually (seeing Fig. 8 C) constantly.The voltage V49 that has been risen in sense node 49 places is applied on the delay circuit 51, so delay circuit 51 is constantly providing the voltage V52(of logic high to see Fig. 8 D to oscillator 100 after a while constantly that is at T12).In other words, this situation can be considered: because current reversed bias voltage VBB is in the state of deterioration, so it must increase sharp to required normal voltage level.
Now with regard to oscillator 100, its response is applied to the logic high V52 on NAND gate 61 inputs and is allowed to work.When oscillator 100 is allowed to work, that is voltage V52 is when having logic-high value, and the bell signal shown in Fig. 8 E produces at inverter 62 and 63 places.In addition, for this same time interval (from the T12 moment to T13 constantly promptly), pump circuit 300 work are so that reversed bias voltage is brought up to required normal level.
Reversed bias voltage rise to normal level during in, because reversed bias voltage VBB becomes and is higher than voltage VBBD, thereby current sensor I50 increase again immediately, sensing voltage V49 descends simultaneously, therefore, oscillator 100 is operated this situation and is quit work constantly at T13 according to needs pumping no longer.Certainly, because the output of driver 200 and the output of oscillator 100 all are logic lows, so pump circuit 300 can not be carried out the pumpings operation in this moment.
In view of the above, if the reversed bias voltage deterioration that causes owing to substrate hole electricity constantly at T13 makes not inflow place terminal of current sensor I50, then reversed bias voltage is kept current level.Be appreciated that from the above, according to the present invention, reversed bias voltage only can be subjected to because the deterioration that substrate self characteristics (being hole current) causes, thereby it can make oscillator work under the situation that the reversed bias voltage that causes owing to any reason descends, reversed bias voltage is risen to required normal level.Yet, for traditional anti-level sensor partially, because the anti-current sensor of level partially of sensing directly causes the reversed bias voltage deterioration.For this reason, be appreciated that from above description the relation between the current sensor and reversed bias voltage and this relation the prior art differ widely in the present invention.
In the above-described embodiments, the PMOS transistor is used as sensing transistor, and it is controlled by reversed bias voltage.Yet, those skilled in the art will appreciate that the insulated gate MOS transistor of other type or have the semiconductor transistor that specific work disconnects level and all can use.Even, although the present invention illustrated with negative reversed bias voltage, also can use positive reversed bias voltage.In this case, the PMOS transistor 13,34 shown in Fig. 4-7 and 50 should constitute with the insulated gate MOS transistor of positive threshold voltage, and the pump circuit among Fig. 7 300 should be made up of nmos pass transistor and NMOS capacitor.
Moreover, though the above embodiments are applied directly to reversed bias voltage on the grid of PMOS transistor 50, it will be apparent to those skilled in the art that and under the situation of the spirit and scope of the present invention, can make concrete modification.And supply voltage can be outside supply voltage, also can be to be converted into the internal power source voltage that is lower than outer power voltage, and this depends on to have the above-mentioned anti-employed operating voltage of semiconductor device of level sensor circuit partially.
Be appreciated that from the above, reverse bias generator response reversed bias voltage level of the present invention is controlled current sensor, and have the current sensor path that directly is not connected, can reduce whereby because the deterioration of the reversed bias voltage that current sensor causes with the reversed bias voltage end.
In addition, reverse bias generator of the present invention prevents too frequent pumping operation, thereby produces low current drain.Have, device of the present invention has reduced the crest voltage amount that the reversed bias voltage terminal produces again, and this crest voltage is to induct to the normal voltage transition period from the voltage of deterioration at reversed bias voltage, so that the noise component(s) that is produced by crest voltage can obtain restriction.And anti-inclined to one side level sensor of the present invention is structurally very simple, thereby its response characteristic is significantly improved.
Claims (20)
1, a kind of in the reverse bias generator that contains pump circuit (300) in order to the circuit of sensing reversed bias voltage level, it is characterized in that comprising:
A control terminal (VBB) is coupled with described reversed bias voltage;
A sensing terminals (49) is through being coupled in order to drive unit and the said pump circuit (300) that drives the said pump circuit; And
An electric raceway groove is connected with ground reference voltage terminal above-mentioned sensing terminals (49) in order to respond above-mentioned reversed bias voltage level on electric, above-mentioned raceway groove insulate on electric with above-mentioned control terminal (VBB) mutually by insulation component.
2, circuit according to claim 1, its spy is, described sensing terminals (49) controllably responds above-mentioned reversed bias voltage and is coupled with an end of the described raceway groove of an insulated gate MOS transistor (50).
3, circuit according to claim 1 is characterized in that, described drive unit in order to driving said pump circuit (300) comprises:
Oscillator arrangement (100), it responds the voltage level of above-mentioned sensing terminals (49); And
A driver (200) is coupled with above-mentioned oscillator arrangement, is sent to said pump circuit (300) in order to the output with above-mentioned oscillator arrangement (100).
4, circuit according to claim 1 is characterized in that, described raceway groove is conducting when above-mentioned control terminal (VBB) is in first voltage level, and is non-conduction when above-mentioned control terminal is in second voltage level.
5, circuit according to claim 4 is characterized in that, described drive unit is only just worked when above-mentioned control terminal is in second voltage level.
6, a kind of in the reverse bias generator that contains pump circuit (300) and oscillator arrangement (100) in order to the circuit of sensing reversed bias voltage level, said pump circuit (300) is in order to provide the above-mentioned reversed bias voltage with preset level to the first conducting type substrate, above-mentioned oscillator arrangement (100) is characterized in that comprising in order to provide the pumping clock signal to above-mentioned pump circuit (300):
First MOS transistor (50), the output of its grid and said pump circuit (300) is coupled, and an end of its raceway groove is connected with ground reference voltage terminal (VSS), and the other end of its raceway groove is connected with the input of above-mentioned oscillator arrangement (100); And
Second MOS transistor (48), its grid are connected in order to receive a constant bias voltage, and an end of its raceway groove is connected with the raceway groove of above-mentioned first MOS transistor (50), and the other end of above-mentioned raceway groove is connected with supply voltage.
7, circuit according to claim 6 is characterized in that, described second MOS transistor (48) has a threshold voltage that is lower than above-mentioned constant bias.
8, circuit according to claim 6 is characterized in that, described supply voltage is the supply voltage of an outside, or is converted to an internal power source voltage that is lower than the said external supply voltage from the said external supply voltage.
9, circuit according to claim 6 is characterized in that, described oscillator arrangement (100) only just is energized during through the above-mentioned raceway groove discharge of above-mentioned first MOS transistor (50) at the voltage of the connected node of above-mentioned first and second MOS transistor.
10, circuit according to claim 6 is characterized in that also comprising a delay circuit (51), and it is connected between the input of above-mentioned connected node and above-mentioned oscillator arrangement (100).
11, circuit according to claim 6 is characterized in that also comprising a bias generator, and this bias generator comprises:
The 3rd PMOS transistor (41), an end of its grid and raceway groove intercouples, and the other end and the supply voltage of its raceway groove are coupled;
The 4th PMOS transistor (44), an end of its grid and raceway groove intercouples, and the raceway groove of the other end of its raceway groove and above-mentioned the 3rd PMOS transistor (41) is coupled;
The 5th PMOS transistor (46), an end of its grid and raceway groove intercouples, and the other end of its raceway groove and above-mentioned the 4th PMOS transistor (44) are coupled; And
A bias voltage generation terminal (45) that forms at the tie point place of above-mentioned the 4th transistor (44) and the 5th PMOS transistor (46) is in order to produce above-mentioned bias voltage, to offer the grid of above-mentioned the 2nd PMOS transistor (48).
12, circuit according to claim 11 is characterized in that, above-mentioned bias voltage is VCC/3, and here, VCC is a supply voltage.
13, circuit according to claim 6 is characterized in that, described bias voltage is provided by a container flat voltage generator.
14, circuit according to claim 13 is characterized in that, described bias voltage is VCC/2, and here, VCC is a supply voltage.
15, a kind of in the reverse bias generator that contains a pump circuit (300) and an oscillator arrangement (100) in order to the circuit of sensing reversed bias voltage level, said pump circuit (300) is in order to provide above-mentioned reversed bias voltage to a Semiconductor substrate, above-mentioned oscillator arrangement (100) is characterized in that comprising in order to provide the pumping clock signal to above-mentioned pump circuit:
A node (32) is in order to the above-mentioned reversed bias voltage level of sensing;
The first fixed resistance device (31) is coupling between above-mentioned node (31) and the power supply voltage terminal;
The second fixed resistance device (33), one end and above-mentioned node (32) are coupled; And
A dynamic electric resistor device (34) is coupling between the other end and ground reference voltage terminal of above-mentioned second fixed resistance (33), and the output of the control terminal of above-mentioned dynamic electric resistor device (34) and said pump circuit (300) is coupled.
16, circuit according to claim 15 is characterized in that, the voltage level of above-mentioned node (32) responds the above-mentioned first fixed resistance device (31) when above-mentioned control terminal is in first state; The voltage level of described node (32) responds described second fixed resistance device (33) and described dynamic electric resistor device when described control end is in second state.
17, circuit according to claim 16 is characterized in that, above-mentioned dynamic electric resistor device (34) is conducting during above-mentioned second state only.
18, circuit according to claim 16 is characterized in that, described oscillator arrangement (100) only is energized during above-mentioned first state.
19, circuit according to claim 15 is characterized in that, the described first fixed resistance device (31) is a PMOS transistor, and its grid is coupled with the ground reference voltage end.
20, circuit according to claim 15 is characterized in that, the described second solid resistance device (33) is a nmos pass transistor, and its grid and supply voltage are coupled.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910009999A KR930001236A (en) | 1991-06-17 | 1991-06-17 | Substrate voltage level sensing circuit with insensitive to power supply voltage fluctuations |
| KR9997/91 | 1991-06-17 | ||
| KR1019910009997A KR940008150B1 (en) | 1991-06-17 | 1991-06-17 | Semiconductor memory device |
| KR9999/91 | 1991-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1067773A true CN1067773A (en) | 1993-01-06 |
Family
ID=26628647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN91110773A Pending CN1067773A (en) | 1991-06-17 | 1991-11-15 | The circuit of sensing back-bias level in semiconductor memory device |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPH04368691A (en) |
| CN (1) | CN1067773A (en) |
| DE (1) | DE4135148C2 (en) |
| FR (1) | FR2677771A1 (en) |
| GB (1) | GB2256950A (en) |
| IT (1) | IT1251721B (en) |
| NL (1) | NL9101710A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466108C (en) * | 2003-06-10 | 2009-03-04 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| CN108777150A (en) * | 2018-05-02 | 2018-11-09 | 友达光电股份有限公司 | Sensing circuit |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5337284A (en) * | 1993-01-11 | 1994-08-09 | United Memories, Inc. | High voltage generator having a self-timed clock circuit and charge pump, and a method therefor |
| KR0123849B1 (en) * | 1994-04-08 | 1997-11-25 | 문정환 | Internal voltage generator of semiconductor device |
| KR0127318B1 (en) * | 1994-04-13 | 1998-04-02 | 문정환 | Back bias voltage generator |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4229667A (en) * | 1978-08-23 | 1980-10-21 | Rockwell International Corporation | Voltage boosting substrate bias generator |
| JPS5694654A (en) * | 1979-12-27 | 1981-07-31 | Toshiba Corp | Generating circuit for substrate bias voltage |
| US4739191A (en) * | 1981-04-27 | 1988-04-19 | Signetics Corporation | Depletion-mode FET for the regulation of the on-chip generated substrate bias voltage |
| JPS57199335A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Generating circuit for substrate bias |
| US4547682A (en) * | 1983-10-27 | 1985-10-15 | International Business Machines Corporation | Precision regulation, frequency modulated substrate voltage generator |
| US4581546A (en) * | 1983-11-02 | 1986-04-08 | Inmos Corporation | CMOS substrate bias generator having only P channel transistors in the charge pump |
| IT1220982B (en) * | 1983-11-30 | 1990-06-21 | Ates Componenti Elettron | CIRCUIT REGULATOR OF THE POLARIZATION VOLTAGE OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT WITH FIELD-EFFECT TRANSISTORS |
| JP2501590B2 (en) * | 1987-07-29 | 1996-05-29 | 沖電気工業株式会社 | Driving circuit for semiconductor device |
| JPH0262071A (en) * | 1988-08-26 | 1990-03-01 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0783254B2 (en) * | 1989-03-22 | 1995-09-06 | 株式会社東芝 | Semiconductor integrated circuit |
| JP2841480B2 (en) * | 1989-06-21 | 1998-12-24 | 日本電気株式会社 | Substrate potential setting circuit |
-
1991
- 1991-09-30 FR FR9111986A patent/FR2677771A1/en active Pending
- 1991-10-14 NL NL9101710A patent/NL9101710A/en not_active Application Discontinuation
- 1991-10-24 DE DE4135148A patent/DE4135148C2/en not_active Expired - Fee Related
- 1991-11-06 IT ITMI912939A patent/IT1251721B/en active IP Right Grant
- 1991-11-15 GB GB9124294A patent/GB2256950A/en not_active Withdrawn
- 1991-11-15 CN CN91110773A patent/CN1067773A/en active Pending
-
1992
- 1992-02-21 JP JP4033906A patent/JPH04368691A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466108C (en) * | 2003-06-10 | 2009-03-04 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| CN108777150A (en) * | 2018-05-02 | 2018-11-09 | 友达光电股份有限公司 | Sensing circuit |
| CN108777150B (en) * | 2018-05-02 | 2021-02-23 | 友达光电股份有限公司 | Sensing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI912939A0 (en) | 1991-11-06 |
| ITMI912939A1 (en) | 1993-05-06 |
| FR2677771A1 (en) | 1992-12-18 |
| NL9101710A (en) | 1993-01-18 |
| IT1251721B (en) | 1995-05-22 |
| JPH04368691A (en) | 1992-12-21 |
| DE4135148C2 (en) | 1995-02-02 |
| GB2256950A (en) | 1992-12-23 |
| DE4135148A1 (en) | 1992-12-24 |
| GB9124294D0 (en) | 1992-01-08 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |